JP4426988B2 - pチャネルMOSトランジスタの製造方法 - Google Patents
pチャネルMOSトランジスタの製造方法 Download PDFInfo
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- 238000004519 manufacturing process Methods 0.000 title claims description 33
- 238000000034 method Methods 0.000 title claims description 22
- 239000000758 substrate Substances 0.000 claims description 68
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 64
- 229910052710 silicon Inorganic materials 0.000 claims description 64
- 239000010703 silicon Substances 0.000 claims description 64
- 229910000577 Silicon-germanium Inorganic materials 0.000 claims description 20
- 230000008569 process Effects 0.000 claims description 10
- 238000002425 crystallisation Methods 0.000 claims description 9
- 230000008025 crystallization Effects 0.000 claims description 9
- 239000013078 crystal Substances 0.000 description 27
- 239000012535 impurity Substances 0.000 description 22
- 239000010410 layer Substances 0.000 description 22
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 14
- 229920005591 polysilicon Polymers 0.000 description 14
- 239000004065 semiconductor Substances 0.000 description 14
- 229910021332 silicide Inorganic materials 0.000 description 14
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 14
- 238000009792 diffusion process Methods 0.000 description 8
- 239000006104 solid solution Substances 0.000 description 8
- 238000005468 ion implantation Methods 0.000 description 6
- 150000002500 ions Chemical class 0.000 description 5
- 239000011229 interlayer Substances 0.000 description 4
- 239000000203 mixture Substances 0.000 description 4
- 238000002513 implantation Methods 0.000 description 3
- 238000002955 isolation Methods 0.000 description 3
- 230000007246 mechanism Effects 0.000 description 3
- 229910052814 silicon oxide Inorganic materials 0.000 description 3
- 230000001133 acceleration Effects 0.000 description 2
- 239000000969 carrier Substances 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 230000006872 improvement Effects 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 230000009471 action Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 230000006835 compression Effects 0.000 description 1
- 238000007906 compression Methods 0.000 description 1
- 230000007850 degeneration Effects 0.000 description 1
- 239000002019 doping agent Substances 0.000 description 1
- 239000007943 implant Substances 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 238000010884 ion-beam technique Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 238000003825 pressing Methods 0.000 description 1
- 238000001953 recrystallisation Methods 0.000 description 1
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- H01L29/7848—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate the means being located in the source/drain region, e.g. SiGe source and drain
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Description
前記第1および第2の領域をアモルファス状態に形成する工程は、前記シリコン基板中に、前記第1および第2の領域に対応してそれぞれ第1および第2の溝を形成し、前記溝をアモルファスSiGeにより充填することにより実行されることを特徴とするpチャネルMOSトランジスタの製造方法を提供する。
図3は、本発明の第1実施例による半導体集積回路装置20の構成を示す図である。
[第2実施例]
以下、図4〜図8を参照しながら、図3の半導体集積回路装置20の製造工程を、本発明の第2実施例として説明する。
[第3実施例]
図9〜図13は、本発明の第3実施例による、半導体装置の製造工程を示す。ただし図中、先に説明した部分に対応する部分には同一の参照符号を付し、説明を省略する。
シリコン基板と、
前記シリコン基板上に、チャネル領域に対応して、ゲート絶縁膜を介して形成され、両側壁面上にそれぞれの側壁絶縁膜を担持するゲート電極と、
前記基板中、前記側壁絶縁膜の外側に形成された、p型のソースおよびドレイン領域とよりなるpチャネルMOSトランジスタであって、
前記ソースおよびドレイン領域の各々は、p型の多結晶領域を内包し、
前記多結晶領域は、圧縮応力を蓄積することを特徴とするpチャネルMOSトランジスタ。
前記多結晶領域はポリシリコンよりなり、Siよりも原子半径の大きな不純物元素を含むことを特徴とする付記1記載のpチャネルMOSトランジスタ。
前記多結晶領域は前記不純物元素を、Si結晶中における前記不純物元素の固溶限界近傍の濃度で含むことを特徴とする付記2記載のpチャネルMOSトランジスタ。
前記多結晶領域は前記不純物元素を、Si結晶中における前記不純物元素の固溶限界を超えた濃度で含むことを特徴とする付記2記載のpチャネルMOSトランジスタ。
前記不純物元素は、InまたはGeよりなることを特徴とする付記2〜4のうち、いずれか一項記載のpチャネルMOSトランジスタ。
前記多結晶領域はポリシリコンよりなり、不純物元素が、前記不純物元素を構成する原子が集合したクラスタの形で含まれていることを特徴とする付記1記載のpチャネルMOSトランジスタ。
前記多結晶領域はSiGe多結晶よりなることを特徴とする付記1記載のpチャネルMOSトランジスタ。
前記SiGe多結晶はGeを、Si結晶に対する固溶限界組成近傍の濃度で含むことを特徴とする付記7記載のpチャネルMOSトランジスタ。
前記SiGe多結晶はGeを、Si結晶に対する固溶限界組成を超えた濃度で含むことを特徴とする付記7記載のpチャネルMOSトランジスタ。
pチャネルMOSトランジスタの製造方法であって、
シリコン基板上に、チャネル領域に対応して、ゲート絶縁膜を介してゲート電極を形成する工程と、
前記ゲート絶縁膜の両側壁面上に、それぞれ側壁絶縁膜を形成する工程と、
前記シリコン基板中、前記側壁絶縁膜の外側に、p型のソース領域およびドレイン領域を形成する工程を含み、
前記p型のソース領域およびドレイン領域を形成する工程は、
それぞれ前記ソース領域およびドレイン領域に内包される第1および第2の領域をアモルファス状態に形成する工程と、
前記第1および第2の領域を結晶化して、前記第1および第2の領域を、前記シリコン基板に対して圧縮歪みを蓄積した多結晶領域とする工程とよりなることを特徴とするpチャネルMOSトランジスタの製造方法。
前記結晶化工程は、前記シリコン基板上に、前記ゲート電極を除き、前記第1および第2の領域を覆うように、剛性を有するマスクを形成して実行されることを特徴とする付記10記載のpチャネルMOSトランジスタの製造方法。
前記第1および第2の領域をアモルファス状態に形成する工程は、前記シリコン基板中に、前記第1および第2の領域に対応して、Si原子より原子半径の大きな原子をイオン注入することにより実行されることを特徴とする付記10または11記載のpチャネルMOSトランジスタの製造方法。
前記第1および第2の領域をアモルファス状態に形成する工程は、前記シリコン基板中に、前記第1および第2の領域に対応して、イオンクラスタを注入することにより実行されることを特徴とする付記10または11記載のpチャネルMOSトランジスタの製造方法。
前記第1および第2の領域をアモルファス状態に形成する工程は、前記シリコン基板中に、前記第1および第2の領域に対応してそれぞれ第1および第2の溝を形成し、前記溝をアモルファスSiGeにより充填することにより実行されることを特徴とする付記10または11記載のpチャネルMOSトランジスタの製造方法。
pチャネルMOSトランジスタの製造方法であって、
シリコン基板上に、チャネル領域に対応して、ゲート絶縁膜を介してゲート電極を形成する工程と、
前記ゲート絶縁膜の両側壁面上に、それぞれ側壁絶縁膜を形成する工程と、
前記シリコン基板中、前記側壁絶縁膜の外側に、p型のソース領域およびドレイン領域を形成する工程を含み、
前記p型のソース領域およびドレイン領域を形成する工程は、
それぞれ前記ソース領域およびドレイン領域に内包される第1および第2の領域を、前記シリコン基板に対して圧縮歪みを蓄積した多結晶状態に形成する工程とよりなることを特徴とするpチャネルMOSトランジスタの製造方法。
1A,21A,21B 素子領域
1I,21I 素子分離領域
1a,11a,21a,21e ソースエクステンション領域
1b,11b,21b,21f ドレインエクステンション領域
2,12,22A,22B ゲート絶縁膜
3,13,23A,23B ゲート電極
4A,4B,4C、21SA,21SB,23SA,23SB シリサイド層
5 引張り応力膜
11A,11B SiGe混晶層領域
13A,13B,23WA,23WB ゲート側壁絶縁膜
21SG 多結晶領域
21SG´ アモルファス領域
24A 引張り応力膜
24B 無応力または圧縮応力膜
25 層間絶縁膜
25A〜25D コンタクトホール
26A〜26D コンタクトプラグ
31,32 CVD酸化膜
Claims (4)
- pチャネルMOSトランジスタの製造方法であって、
シリコン基板上に、チャネル領域に対応して、ゲート絶縁膜を介してゲート電極を形成する工程と、
前記ゲート絶縁膜の両側壁面上に、それぞれ側壁絶縁膜を形成する工程と、
前記シリコン基板中、前記側壁絶縁膜の外側に、p型のソース領域およびドレイン領域を形成する工程を含み、
前記p型のソース領域およびドレイン領域を形成する工程は、
それぞれ前記ソース領域およびドレイン領域に内包される第1および第2の領域をアモルファス状態に形成する工程と、
前記第1および第2の領域を結晶化して、前記第1および第2の領域を、前記シリコン基板に対して圧縮歪みを蓄積した多結晶領域とする工程とよりなり、
前記結晶化工程は、前記シリコン基板上に、前記ゲート電極を除き、前記第1および第2の領域を覆うように、剛性を有するマスクを形成して実行されることを特徴とするpチャネルMOSトランジスタの製造方法。 - 前記第1および第2の領域をアモルファス状態に形成する工程は、前記シリコン基板中に、前記第1および第2の領域に対応して、イオンクラスタを注入することにより実行されることを特徴とする請求項1記載のpチャネルMOSトランジスタの製造方法。
- 前記第1および第2の領域をアモルファス状態に形成する工程は、前記シリコン基板中に、前記第1および第2の領域に対応してそれぞれ第1および第2の溝を形成し、前記溝をアモルファスSiGeにより充填することにより実行されることを特徴とする請求項1記載のpチャネルMOSトランジスタの製造方法。
- pチャネルMOSトランジスタの製造方法であって、
シリコン基板上に、チャネル領域に対応して、ゲート絶縁膜を介してゲート電極を形成する工程と、
前記ゲート絶縁膜の両側壁面上に、それぞれ側壁絶縁膜を形成する工程と、
前記シリコン基板中、前記側壁絶縁膜の外側に、p型のソース領域およびドレイン領域を形成する工程を含み、
前記p型のソース領域およびドレイン領域を形成する工程は、
それぞれ前記ソース領域およびドレイン領域に内包される第1および第2の領域をアモルファス状態に形成する工程と、
前記第1および第2の領域を結晶化して、前記第1および第2の領域を、前記シリコン基板に対して圧縮歪みを蓄積した多結晶領域とする工程とよりなり、
前記第1および第2の領域をアモルファス状態に形成する工程は、前記シリコン基板中に、前記第1および第2の領域に対応してそれぞれ第1および第2の溝を形成し、前記溝をアモルファスSiGeにより充填することにより実行されることを特徴とするpチャネルMOSトランジスタの製造方法。
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US7221024B1 (en) * | 2005-10-27 | 2007-05-22 | International Business Machines Corporation | Transistor having dielectric stressor elements for applying in-plane shear stress |
JP5018780B2 (ja) * | 2006-09-27 | 2012-09-05 | 富士通株式会社 | 半導体装置およびその製造方法 |
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JP5003515B2 (ja) | 2007-03-20 | 2012-08-15 | ソニー株式会社 | 半導体装置 |
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US7993997B2 (en) * | 2007-10-01 | 2011-08-09 | Globalfoundries Singapore Pte. Ltd. | Poly profile engineering to modulate spacer induced stress for device enhancement |
US7776699B2 (en) * | 2008-02-05 | 2010-08-17 | Chartered Semiconductor Manufacturing, Ltd. | Strained channel transistor structure and method |
US7935601B1 (en) * | 2009-09-04 | 2011-05-03 | The United States Of America As Represented By The Administrator Of National Aeronautics And Space Administration | Method for providing semiconductors having self-aligned ion implant |
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US6255214B1 (en) * | 1999-02-24 | 2001-07-03 | Advanced Micro Devices, Inc. | Method of forming junction-leakage free metal silicide in a semiconductor wafer by amorphization of source and drain regions |
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US20040262683A1 (en) * | 2003-06-27 | 2004-12-30 | Bohr Mark T. | PMOS transistor strain optimization with raised junction regions |
US6891192B2 (en) | 2003-08-04 | 2005-05-10 | International Business Machines Corporation | Structure and method of making strained semiconductor CMOS transistors having lattice-mismatched semiconductor regions underlying source and drain regions |
US7118979B2 (en) * | 2003-11-05 | 2006-10-10 | Texas Instruments Incorporated | Method of manufacturing transistor having germanium implant region on the sidewalls of the polysilicon gate electrode |
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