JP5195747B2 - 半導体装置の製造方法 - Google Patents
半導体装置の製造方法 Download PDFInfo
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- JP5195747B2 JP5195747B2 JP2009506176A JP2009506176A JP5195747B2 JP 5195747 B2 JP5195747 B2 JP 5195747B2 JP 2009506176 A JP2009506176 A JP 2009506176A JP 2009506176 A JP2009506176 A JP 2009506176A JP 5195747 B2 JP5195747 B2 JP 5195747B2
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- 239000004065 semiconductor Substances 0.000 title claims description 49
- 238000004519 manufacturing process Methods 0.000 title claims description 39
- 229910021417 amorphous silicon Inorganic materials 0.000 claims description 53
- 239000012535 impurity Substances 0.000 claims description 39
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 31
- 238000010438 heat treatment Methods 0.000 claims description 25
- 238000000034 method Methods 0.000 claims description 25
- 125000006850 spacer group Chemical group 0.000 claims description 19
- 238000000137 annealing Methods 0.000 claims description 16
- 230000004913 activation Effects 0.000 claims description 14
- 229910052710 silicon Inorganic materials 0.000 claims description 11
- 238000002513 implantation Methods 0.000 claims description 9
- 230000015572 biosynthetic process Effects 0.000 claims description 7
- 150000002500 ions Chemical class 0.000 claims description 7
- 239000000758 substrate Substances 0.000 claims description 7
- 229910000577 Silicon-germanium Inorganic materials 0.000 claims description 6
- 229910052698 phosphorus Inorganic materials 0.000 claims description 6
- 229910052731 fluorine Inorganic materials 0.000 claims description 5
- 229910052757 nitrogen Inorganic materials 0.000 claims description 4
- 229910052732 germanium Inorganic materials 0.000 claims description 3
- 238000009792 diffusion process Methods 0.000 claims description 2
- 239000010410 layer Substances 0.000 description 66
- 229920005591 polysilicon Polymers 0.000 description 23
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 8
- 239000010703 silicon Substances 0.000 description 8
- 238000001459 lithography Methods 0.000 description 7
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 6
- 229910052814 silicon oxide Inorganic materials 0.000 description 6
- 229910052581 Si3N4 Inorganic materials 0.000 description 5
- 238000005229 chemical vapour deposition Methods 0.000 description 5
- 238000001312 dry etching Methods 0.000 description 5
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 5
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 4
- 230000000694 effects Effects 0.000 description 4
- 238000005468 ion implantation Methods 0.000 description 4
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 3
- 229910052787 antimony Inorganic materials 0.000 description 3
- 239000013078 crystal Substances 0.000 description 3
- 238000000151 deposition Methods 0.000 description 3
- 239000002245 particle Substances 0.000 description 3
- 239000011574 phosphorus Substances 0.000 description 3
- 239000002356 single layer Substances 0.000 description 3
- 229910015890 BF2 Inorganic materials 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 2
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 2
- PXGOKWXKJXAPGV-UHFFFAOYSA-N Fluorine Chemical compound FF PXGOKWXKJXAPGV-UHFFFAOYSA-N 0.000 description 2
- 206010037660 Pyrexia Diseases 0.000 description 2
- 229910052785 arsenic Inorganic materials 0.000 description 2
- 229910052796 boron Inorganic materials 0.000 description 2
- 229910052799 carbon Inorganic materials 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000009826 distribution Methods 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 239000011737 fluorine Substances 0.000 description 2
- 239000011810 insulating material Substances 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- 229910021332 silicide Inorganic materials 0.000 description 2
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 2
- WGTYBPLFGIVFAS-UHFFFAOYSA-M tetramethylammonium hydroxide Chemical compound [OH-].C[N+](C)(C)C WGTYBPLFGIVFAS-UHFFFAOYSA-M 0.000 description 2
- 230000006866 deterioration Effects 0.000 description 1
- 239000007772 electrode material Substances 0.000 description 1
- 238000010030 laminating Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 230000007261 regionalization Effects 0.000 description 1
- 238000003892 spreading Methods 0.000 description 1
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- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
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Description
(a)半導体基板上に第1の非晶質シリコン膜を形成し、
(b)前記第1の非晶質シリコン膜のnMOS領域に、P、Ge、Siから選択される少なくとも1の不純物イオンを注入し、
(c)前記第1の非晶質シリコン膜上に、第2の非晶質シリコン膜を積層し、
(d)前記第1および第2の非晶質シリコン膜をゲート電極パタンに加工し、
(e)前記ゲート電極パタンの形成よりも後の工程で、熱処理を施すことによって、前記nMOS領域の第1の非晶質シリコン膜を多結晶化する
ステップを含む。
7,25 サイドウォールスペーサ
8、32b、33a、33b 小粒径のポリシリコン層
9、20 ゲート電極
10 半導体装置
11 半導体基板
12 素子分離領域
13 ゲート絶縁膜
17、27 サイドウォールスペーサ
21 エクステンション
22 ポケット
26 ソース・ドレイン
41 SiGe歪み生成層
(第1実施形態)
図2Aから図2Kは、第1実施形態の半導体装置の製造工程図である。まず、図2Aに示すように、通常のCMOSプロセスにより素子分離(STI)12、ゲート絶縁膜13を形成する。ゲート絶縁膜13上に、ゲート電極を構成することになる第1の層として非晶質シリコン膜14を10nm〜50nm堆積する。
(第2実施形態)
次に、図3A〜図3Cを参照して、第2実施形態の半導体装置の製造工程を説明する。上述した第1実施形態では、ソース・ドレイン形成後に活性化アニールを行うことで、非晶質シリコンを多結晶化していた。第2実施形態では、活性化アニールとは独立に、別途熱処理を行うことで多結晶化する。
(第3実施形態)
次に、図4A〜図4Cを参照して、第3実施形態の半導体装置の製造工程を説明する。第1実施形態では、活性化アニールを行うことで非晶質シリコンを多結晶化していたが、第3実施形態では、活性化アニールではなく選択エピタキシャル成長時の熱により多結晶化する。
(第4実施形態)
次に、図5A〜5Cを参照して、第4実施形態の半導体装置の製造工程を説明する。第1実施形態では、活性化アニールを行うことで非晶質シリコンを多結晶化していたが、第4実施形態では、活性化アニールではなく、サイドウォールスペーサ形成時の熱により多結晶化する。
Claims (9)
- 半導体基板上に第1の非晶質シリコン膜を形成し、
前記第1の非晶質シリコン膜のnMOS領域に、P、Ge、Siから選択される少なくとも1の不純物イオンを注入し、
前記不純物イオンが注入された前記第1の非晶質シリコン膜上に、第2の非晶質シリコン膜を積層し、
前記第1および第2の非晶質シリコン膜をゲート電極パタンに加工し、
前記ゲート電極パタンの形成よりも後の工程で、熱処理を施すことによって、前記nMOS領域の第1の非晶質シリコン膜を、第1の粒径を有する第1多結晶シリコン膜とするとともに、前記第2の非晶質シリコン膜を、前記第1の粒径よりも小さい第2の粒径を有する第2多結晶シリコン膜とする、
ステップを含むことを特徴とする半導体装置の製造方法。 - 前記第1の非晶質シリコン膜のpMOS領域に、B、BF2、N、Fから選択される少なくとも1の不純物イオンを注入する、
ステップをさらに含むことを特徴とする請求項1に記載の半導体装置の製造方法。 - 前記熱処理は、ソース・ドレイン注入後の活性化アニールで行うことを特徴とする請求項1又は2に記載の半導体装置の製造方法。
- 前記熱処理は、ソース・ドレイン注入後の活性化アニールとは別途独立して行うことを特徴とする請求項1又は2に記載の半導体装置の製造方法。
- 前記熱処理を、選択エピタキシャル成長時の熱を利用して行うことを特徴とする請求項1又は2に記載の半導体装置の製造方法。
- 前記熱処理を、ゲート電極の側壁へのサイドウォールスペーサの形成時の熱で行うことを特徴とする請求項1又は2に記載の半導体装置の製造方法。
- 前記ゲート電極パタン形成後に、pMOS領域のソース・ドレイン領域を掘り込む、
ステップをさらに含み、前記熱処理は、前記掘り込み部分に、選択エピタキシャル成長でSiGe層を形成する際の熱を利用して行うことを特徴とする請求項1又は2に記載の半導体装置の製造方法。 - 前記サイドウォールスペーサの形成は、前記ゲート電極パタンを覆う第1の絶縁膜を形成する工程と、前記第1絶縁膜上の第2の絶縁膜を形成する工程を含み、
前記熱処理は、前記第2の絶縁膜形成時の熱を利用して行うことを特徴とする請求項6に記載の半導体装置の製造方法。 - 前記第1の絶縁膜は、非晶質シリコンが結晶化しない温度で形成し、前記第2の絶縁膜は、不純物の拡散が生じず、かつ前記非晶質シリコンが結晶化する温度で形成する、
ことを特徴とする請求項8に記載の半導体装置の製造方法。
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US8048750B2 (en) * | 2008-03-10 | 2011-11-01 | Texas Instruments Incorporated | Method to enhance channel stress in CMOS processes |
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US20170365528A1 (en) | 2017-12-21 |
JPWO2008117464A1 (ja) | 2010-07-08 |
US20100078729A1 (en) | 2010-04-01 |
US9786565B2 (en) | 2017-10-10 |
US20180294195A1 (en) | 2018-10-11 |
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