WO2008117464A1 - 半導体装置およびその製造方法 - Google Patents

半導体装置およびその製造方法 Download PDF

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Publication number
WO2008117464A1
WO2008117464A1 PCT/JP2007/056458 JP2007056458W WO2008117464A1 WO 2008117464 A1 WO2008117464 A1 WO 2008117464A1 JP 2007056458 W JP2007056458 W JP 2007056458W WO 2008117464 A1 WO2008117464 A1 WO 2008117464A1
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WIPO (PCT)
Prior art keywords
gate electrode
nmos
semiconductor device
laminated
polycrystalline silicon
Prior art date
Application number
PCT/JP2007/056458
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English (en)
French (fr)
Inventor
Hidenobu Fukutome
Hiroyuki Ohta
Mitsugu Tajima
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Fujitsu Microelectronics Limited
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Publication date
Application filed by Fujitsu Microelectronics Limited filed Critical Fujitsu Microelectronics Limited
Priority to PCT/JP2007/056458 priority Critical patent/WO2008117464A1/ja
Priority to JP2009506176A priority patent/JP5195747B2/ja
Publication of WO2008117464A1 publication Critical patent/WO2008117464A1/ja
Priority to US12/567,084 priority patent/US9786565B2/en
Priority to US15/692,752 priority patent/US20170365528A1/en
Priority to US16/004,035 priority patent/US20180294195A1/en

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    • HELECTRICITY
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    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232Field-effect technology
    • H01L21/8234MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238Complementary field-effect transistors, e.g. CMOS
    • H01L21/823828Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
    • H01L21/823842Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008Making conductor-insulator-semiconductor electrodes
    • H01L21/28017Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28035Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232Field-effect technology
    • H01L21/8234MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238Complementary field-effect transistors, e.g. CMOS
    • H01L21/823807Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
    • HELECTRICITY
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    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/4916Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen
    • H01L29/4925Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
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    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007Multistep manufacturing processes
    • H01L29/66075Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409Unipolar field-effect transistors
    • H01L29/66477Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568Lateral single gate silicon transistors
    • H01L29/66636Lateral single gate silicon transistors with source or drain recessed by etching or first recessed by etching and then refilled
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    • H01L29/7842Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
    • H01L29/7845Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate the means being a conductive material, e.g. silicided S/D or Gate
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    • H01L29/7848Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate the means being located in the source/drain region, e.g. SiGe source and drain
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    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/7833Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
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    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/7833Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
    • H01L29/7834Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's with a non-planar structure, e.g. the gate or the source or the drain being non-planar

Abstract

 半導体装置(10)は、少なくとも2層の多結晶シリコン膜が積層された積層ゲート電極を有するトランジスタ構造を含み、nMOS領域に形成されるnMOSゲート電極(9、20N)の最下層の多結晶シリコン膜(2、32)の粒径は、上層のゲート電極膜(8、32b)の粒径よりも大きい。nMOSゲート電極底部での粒径増大に伴う体積膨張により、ゲート電極直下のチャネル領域(CH)に対して鉛直方向に応力を印加する。
PCT/JP2007/056458 2007-03-27 2007-03-27 半導体装置およびその製造方法 WO2008117464A1 (ja)

Priority Applications (5)

Application Number Priority Date Filing Date Title
PCT/JP2007/056458 WO2008117464A1 (ja) 2007-03-27 2007-03-27 半導体装置およびその製造方法
JP2009506176A JP5195747B2 (ja) 2007-03-27 2007-03-27 半導体装置の製造方法
US12/567,084 US9786565B2 (en) 2007-03-27 2009-09-25 Semiconductor device and method of manufacturing the semiconductor device
US15/692,752 US20170365528A1 (en) 2007-03-27 2017-08-31 Semiconductor device and method of manufacturing the semiconductor device
US16/004,035 US20180294195A1 (en) 2007-03-27 2018-06-08 Semiconductor device and method of manufacturing the semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/JP2007/056458 WO2008117464A1 (ja) 2007-03-27 2007-03-27 半導体装置およびその製造方法

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US12/567,084 Continuation US9786565B2 (en) 2007-03-27 2009-09-25 Semiconductor device and method of manufacturing the semiconductor device

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WO2008117464A1 true WO2008117464A1 (ja) 2008-10-02

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Cited By (2)

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US20110312144A1 (en) * 2008-03-10 2011-12-22 Texas Instruments Incorporated Novel method to enhance channel stress in cmos processes
WO2016110990A1 (ja) * 2015-01-09 2016-07-14 株式会社日立製作所 パワー半導体素子、パワーモジュール、および電力変換装置

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US8999861B1 (en) * 2011-05-11 2015-04-07 Suvolta, Inc. Semiconductor structure with substitutional boron and method for fabrication thereof
US9112057B1 (en) 2012-09-18 2015-08-18 Mie Fujitsu Semiconductor Limited Semiconductor devices with dopant migration suppression and method of fabrication thereof
US9299801B1 (en) 2013-03-14 2016-03-29 Mie Fujitsu Semiconductor Limited Method for fabricating a transistor device with a tuned dopant profile
KR101993321B1 (ko) * 2013-11-11 2019-06-26 에스케이하이닉스 주식회사 트랜지스터, 트랜지스터의 제조 방법 및 트랜지스터를 포함하는 전자장치
KR102133490B1 (ko) * 2013-11-11 2020-07-13 에스케이하이닉스 주식회사 트랜지스터, 트랜지스터의 제조 방법 및 트랜지스터를 포함하는 전자장치
KR102618607B1 (ko) * 2016-09-06 2023-12-26 삼성전자주식회사 반도체 장치 및 그 제조 방법
CN111051257B (zh) 2017-09-08 2022-12-09 J2原料公司 金刚石和形成金刚石的异质外延方法
US10790145B2 (en) * 2018-09-05 2020-09-29 Micron Technology, Inc. Methods of forming crystallized materials from amorphous materials
US10707298B2 (en) 2018-09-05 2020-07-07 Micron Technology, Inc. Methods of forming semiconductor structures
US11018229B2 (en) 2018-09-05 2021-05-25 Micron Technology, Inc. Methods of forming semiconductor structures

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20110312144A1 (en) * 2008-03-10 2011-12-22 Texas Instruments Incorporated Novel method to enhance channel stress in cmos processes
WO2016110990A1 (ja) * 2015-01-09 2016-07-14 株式会社日立製作所 パワー半導体素子、パワーモジュール、および電力変換装置

Also Published As

Publication number Publication date
US20170365528A1 (en) 2017-12-21
JPWO2008117464A1 (ja) 2010-07-08
JP5195747B2 (ja) 2013-05-15
US20100078729A1 (en) 2010-04-01
US20180294195A1 (en) 2018-10-11
US9786565B2 (en) 2017-10-10

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