JP2007528593A5 - - Google Patents

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JP2007528593A5
JP2007528593A5 JP2006536715A JP2006536715A JP2007528593A5 JP 2007528593 A5 JP2007528593 A5 JP 2007528593A5 JP 2006536715 A JP2006536715 A JP 2006536715A JP 2006536715 A JP2006536715 A JP 2006536715A JP 2007528593 A5 JP2007528593 A5 JP 2007528593A5
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pfet
channel
nfet
material layer
substrate
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JP2006536715A
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JP2007528593A (ja
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Priority claimed from US10/689,506 external-priority patent/US7303949B2/en
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Claims (19)

  1. ｐ型電界効果トランジスタ（ｐＦＥＴ）チャネルおよびｎ型電界効果トランジスタ（ｎＦＥＴ）チャネルを基板内に形成するステップと、
    前記ｐＦＥＴチャネルにｐＦＥＴスタックを、前記ｎＦＥＴチャネルにｎＦＥＴスタックを形成するステップと、
    前記ｐＦＥＴスタックに関連するソース／ドレイン領域に、前記基板の基礎格子定数と異なる格子定数を有する第１の材料層を準備して、前記ｐＦＥＴチャネル内で圧縮状態を生成するステップと、
    前記ｎＦＥＴスタックに関連するソース／ドレイン領域に、前記基板の基礎格子定数と異なる格子定数を有する第２の材料層を準備して、前記ｎＦＥＴチャネルで、引張状態を生成するステップとを含む、半導体構造の製造方法。
  2. 前記第１の材料層は、ＳｉＧｅであり、前記第２の材料層は、Ｓｉ：Ｃである、請求項１に記載の方法。
  3. 前記Ｓｉ：Ｃは、４％以下のＣ含有量を有する、請求項２に記載の方法。
  4. 前記第１の材料層は、非緩和ＳｉＧｅであり、前記第２の材料層は、非緩和Ｓｉ：Ｃであり、１０〜１００ｎｍの厚みに形成される、請求項１に記載の方法。
  5. 前記第１の材料層は、前記ｎＦＥＴチャネル上にマスクを配置し、前記ｐＦＥＴスタックの領域をエッチングし、前記ｐＦＥＴチャネルの領域内の前記第１の材料層を選択的に成長させることにより形成され、
    前記第２の材料層は、前記ｐＦＥＴチャネル上にマスクを配置し、前記ｎＦＥＴスタッ
    クの領域をエッチングし、前記ｎＦＥＴチャネルの領域内の前記第２の材料層を選択的に
    成長させることによって形成される、請求項１に記載の方法。
  6. 前記ｐＦＥＴスタックの領域のエッチングに先立って、前記マスク下で前記ｐＦＥＴスタックを覆って保護層を準備し、前記第１の材料層を選択的に成長させるステップと、
    前記ｐＦＥＴスタックの領域のエッチングに先立って、前記マスク下で前記ｎＦＥＴスタックを覆って保護層を準備し、前記第２の材料層を選択的に成長させるステップとをさらに含む、請求項６に記載の方法。
  7. 前記第１の材料層および前記第２の材料層は、厚さ１０〜１００ｎｍに成長されている、請求項１に記載の方法。
  8. 前記第１の材料層および前記第２の材料層は、前記基板に埋め込まれている、請求項１に記載の方法。
  9. ｐ型電界効果トランジスタ（ｐＦＥＴ）チャネルおよびｎ型電界効果トランジスタ（ｎＦＥＴ）チャネルを基板内に形成するステップと、
    前記ｐＦＥＴチャネルおよび前記ｎＦＥＴチャネルのそれぞれに関連して、前記ｐＦＥＴ構造およびｎＦＥＴ構造を基板上に形成するステップと、
    前記ｐＦＥＴ構造および前記ｎＦＥＴ構造の領域をエッチングするステップと、
    前記ｐＦＥＴ構造の領域内に、前記基板の基礎格子定数と異なる格子定数を有する第１の材料を形成して、前記ｐＦＥＴチャネルに圧縮応力を付与するステップと、
    前記ｎＦＥＴ構造の領域内に、前記基板の基礎格子定数と異なる格子定数を有する第２の材料を形成して、前記ｎＦＥＴチャネルに引張応力を付与するステップと、
    前記ｎＦＥＴおよびｐＦＥＴ構造のソースおよびドレイン領域をドーピングするステップとを含む、半導体構造の製造方法。
  10. 前記第１の材料は、ＳｉＧｅであり、前記第２の材料は、Ｓｉ：Ｃである、請求項９に記載の方法。
  11. 前記第１の材料は、前記ｐＦＥＴチャネル内に圧縮応力を生成し、前記第２の材料は、ｎＦＥＴチャネル内に引張応力を生成する、請求項９に記載の方法。
  12. 前記第１の材料は、前記ｎＦＥＴ構造および前記ｐＦＥＴ構造を覆って保護層を配置し、前記ｐＦＥＴチャネルのソースおよびドレイン領域内に、前記第１の材料を成長させることにより形成され、
    前記第２の材料は、前記ｐＦＥＴ構造および前記ｎＦＥＴ構造のソースおよびドレイン領域を覆って保護層を配置し、前記ｎＦＥＴチャネルのソースおよびドレイン領域内に、前記第２の材料を成長させることにより形成される、請求項９に記載の方法。
  13. 前記第１の材料および前記第２の材料は、前記基板に埋め込まれている、請求項９に記
    載の方法。
  14. 前記第１の材料および前記第２の材料は、前記基板の表面上に隆起される、請求項９に記載の方法。
  15. 前記第１の材料は、非緩和ＳｉＧｅである、請求項９に記載の方法。
  16. 前記第１の材料をｐ型ドーピングで、前記第２の材料をｎ型ドーピングでそのままでドープして、それぞれｐＦＥＴおよびｎＦＥＴのソースおよびドレイン領域を形成する、請求項９に記載の方法。
  17. 基板内に形成されたｐ型電界効果トランジスタ（ｐＦＥＴ）チャネルと、
    前記基板内に形成されたｎ型電界効果トランジスタ（ｎＦＥＴ）チャネルと、
    前記基板の格子定数と異なる格子定数を有するｐＦＥＴチャネルのソースおよびドレイン領域内の第１の材料層と、
    前記基板の格子定数と異なる格子定数を有するｎＦＥＴチャネルのソースおよびドレイン領域内の第２の材料層とを含む、半導体構造。
  18. 前記第１の材料層は、ＳｉＧｅであり、前記第２の材料層は、Ｓｉ：Ｃである、請求項１７に記載の構造。
  19. 前記第１の材料層および前記第２の材料層は、前記ｐＦＥＴチャネルおよび前記ｎＦＥＴチャネルで、異なる種類の応力をそれぞれ生成する、請求項１７に記載の構造。
JP2006536715A 2003-10-20 2004-10-19 Ｓｉ：ＣおよびＳｉＧｅエピタキシャル成長ソース／ドレインを用いた高性能で応力が向上されたＭＯＳＦＥＴおよび製造方法 Pending JP2007528593A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/689,506 US7303949B2 (en) 2003-10-20 2003-10-20 High performance stress-enhanced MOSFETs using Si:C and SiGe epitaxial source/drain and method of manufacture
PCT/US2004/034562 WO2005043591A2 (en) 2003-10-20 2004-10-19 HIGH PERFORMANCE STRESS-ENHANCED MOSFETs USING Si:C AND SiGe EPITAXIAL SOURCE/DRAIN AND METHOD OF MANUFACTURE

Publications (2)

Publication Number Publication Date
JP2007528593A JP2007528593A (ja) 2007-10-11
JP2007528593A5 true JP2007528593A5 (ja) 2007-11-22

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Country Status (7)

Country Link
US (5) US7303949B2 (ja)
EP (1) EP1676297A4 (ja)
JP (1) JP2007528593A (ja)
KR (1) KR100985935B1 (ja)
CN (1) CN100562972C (ja)
TW (1) TWI351762B (ja)
WO (1) WO2005043591A2 (ja)

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