US20100001317A1 - Cmos transistor and the method for manufacturing the same - Google Patents

Cmos transistor and the method for manufacturing the same Download PDF

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US20100001317A1
US20100001317A1 US12/168,062 US16806208A US2010001317A1 US 20100001317 A1 US20100001317 A1 US 20100001317A1 US 16806208 A US16806208 A US 16806208A US 2010001317 A1 US2010001317 A1 US 2010001317A1
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thin film
transistor
pmos transistor
drain
source
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US12/168,062
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Yi-Wei Chen
Teng-Chun Tsai
Chien-Chung Huang
Jei-Ming Chen
Tsai-fu Hsiao
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United Microelectronics Corp
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United Microelectronics Corp
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Priority to US12/168,062 priority Critical patent/US20100001317A1/en
Assigned to UNITED MICROELECTRONICS CORP. reassignment UNITED MICROELECTRONICS CORP. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: CHEN, JEI-MING, CHEN, YI-WEI, HSIAO, TSAI-FU, HUANG, CHIEN-CHUNG, TSAI, TENG-CHUN
Publication of US20100001317A1 publication Critical patent/US20100001317A1/en
Priority to US14/060,568 priority patent/US9502305B2/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823814—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
    • H01L21/26513—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors of electrically active species
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823807—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System
    • H01L29/161—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System including two or more of the elements provided for in group H01L29/16, e.g. alloys
    • H01L29/165—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System including two or more of the elements provided for in group H01L29/16, e.g. alloys in different semiconductor regions, e.g. heterojunctions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66613—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation
    • H01L29/66628—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation recessing the gate by forming single crystalline semiconductor material at the source or drain location
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
    • H01L29/7843—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate the means being an applied insulating layer

Definitions

  • the present invention is related to a CMOS transistor and a method for manufacturing the same, and particularly, to a CMOS transistor capable of preventing Ge out-diffusion and a method for manufacturing the same.
  • CMOS complementary metal-oxide semiconductor
  • PMOS p-type MOS
  • NMOS n-type MOS
  • the strained-silicon technique substantially includes a substrate-strained based method and a process-induced strain based method.
  • the substrate-strained based system is performed with a strained-silicon substrate or a selective epitaxial growth process that results in lattice constant discrepancy.
  • the process-induced strain based method is performed with several unique processes to form a strained thin film upon a surface of the MOS transistor that exert tensile stress or compressive stress upon the MOS transistor. Both of the strained-silicon techniques introduce strain into the channel region and reduce carrier mobile resistance thereby improving carrier mobility and MOS transistor performance.
  • FIG. 1 is a schematic diagram illustrating a conventional CMOS transistor 10 .
  • the CMOS transistor 10 includes a PMOS transistor 12 and an NMOS transistor 14 disposed on a substrate 16 .
  • a plurality of shallow trench isolations (STI) 30 is disposed on the substrate 16 to prevent short-circuiting between the PMOS transistor 12 and the NMOS transistor 14 .
  • the NMOS transistor 14 having a source/drain 20 A and a gate structure 22 A is disposed on a P well 18 formed in the substrate 16 .
  • the PMOS transistor 12 having a source/drain 20 B and a gate structure 22 B is disposed on an N well 24 formed in the substrate 16 .
  • the source/drain 20 B of the PMOS transistor 12 is a silicon germanium (SiGe) epitaxial layer.
  • a compressive strain resulting from the lattice constant discrepancy of SiGe epitaxial layer is induced into the channel region of the PMOS transistor 12 .
  • Nickel silicide layers 26 are respectively formed on the surface of the source/drain 20 A, 20 B for increasing the Ohmic contact capability between metals and the silicon substrate.
  • a high tensile thin film 28 is formed on the CMOS transistor 10 .
  • the high tensile thin film 28 is disposed covering the gate structure 22 A, 22 B and the source/drain 20 A, 20 B.
  • an UV curing process is performed by a UV radiation to enhance the tensile strain of the high tensile thin film 28 that results in elongating the distance of the lattice of the channel region positioned under the gate structure 22 A of the NMOS transistor 14 . Therefore, the NMOS transistor 14 has a higher driving current and a better electron mobility in the channel region.
  • Tensile strain of the high tensile thin film 28 is adjusted by the UV curing process for improving performance of NMOS transistor 14 .
  • the tensile strain results in Ge-out diffusion at the source/drain 20 B of the PMOS transistor 12 .
  • FIG. 2 which is a SEM photo of the CMOS transistor 10
  • a plurality of black spots are formed on the surface of the nickel silicide layer 26 , in which is the evidence of the Ge-out diffusion.
  • Ge-out diffusion results in silicide agglomeration that increases resistance, reduces the concentration of the Ge in the SiGe epitaxial layer, and affects the accuracy of the threshold voltage of the PMOS transistor 12 .
  • the present invention provides a method of manufacturing a CMOS transistor, which is capable of preventing Ge-out diffusion.
  • a semiconductor substrate having at least a PMOS transistor and an NMOS transistor is provided.
  • the source/drain of the PMOS transistor has Ge therein.
  • a carbon-doped layer is formed at the top portion of the source/drain of the PMOS transistor.
  • a self-aligned silicide process is performed.
  • At least a tensile thin film is formed covering the semiconductor substrate, the NMOS transistor, and the PMOS transistor.
  • a surface treatment is performed upon the tensile thin film.
  • the present invention further discloses a CMOS transistor.
  • the CMOS transistor has a semiconductor substrate, at least a NMOS transistor and at least a PMOS transistor disposed on the semiconductor substrate, and a CESL disposed on the PMOS transistor and the NMOS transistor.
  • the PMOS transistor has a source/drain, which includes Ge therein.
  • a carbon-doped layer is disposed in the top portion of the source/drain of the PMOS transistor, and so that, the CMOS transistor of the present invention is capable of preventing Ge-out diffusion.
  • the CMOS transistor formed by the method of the present invention has a carbon-doped layer in the top portion of the source/drain of the PMOS transistor. Therefore, the concentration of the Ge dopant is maintained in the source/drain of the PMOS transistor and the issue of Ge-out diffusion is solved.
  • FIG. 1 is a schematic diagram illustrating a conventional CMOS transistor.
  • FIG. 2 is a SEM photo of the conventional CMOS transistor.
  • FIG. 3 to FIG. 9 are schematic diagrams illustrating a method for manufacturing a CMOS transistor according to a preferred embodiment of the present invention.
  • FIG. 10 is a flow diagram of the method of the present invention to manufacture the CMOS transistor for preventing Ge-out diffusion.
  • FIG. 11 is a SEM photo of the CMOS transistor manufactured by the method of the present invention.
  • FIG. 3 to FIG. 9 are schematic diagrams illustrating a method for manufacturing a CMOS transistor according to a preferred embodiment of the present invention.
  • FIG. 10 is a flow diagram of the method of the present invention to manufacture the CMOS transistor for preventing Ge-out diffusion.
  • a semiconductor substrate 30 is provided, in which the semiconductor substrate 30 has at least a PMOS transistor 32 and an NMOS transistor 34 disposed thereon.
  • the NMOS transistor 34 is formed in a P well 36 disposed in the semiconductor substrate 30 .
  • the NMOS transistor 34 includes a gate structure 38 A formed on the surface of the semiconductor substrate 30 and a source/drain 40 disposed beside the gate structure 38 A.
  • the PMOS transistor 32 is formed in an N well 44 .
  • the PMOS transistor 32 includes a gate structure 38 B formed on the surface of the semiconductor substrate 30 and a source/drain 46 disposed beside the gate structure 38 B.
  • Each of the gate structure 38 A, 38 B includes a gate dielectric layer 50 , a gate 52 , and a cap layer 54 .
  • the gate dielectric layer 50 may include dielectric materials including silicon oxide, oxynitride, and silicon nitride; high-k dielectric materials including metal oxide, metal silicate, metal aluminate, and metal oxynitride; or combinations thereof.
  • the gate dielectric layer 50 may be formed by a thermal oxidation process, a nitridation process, or a chemical vapor deposition (CVD) process.
  • the gate 52 may use polysilicon, SiGe, metal, silicide, metal nitride, metal oxide, or combinations thereof as material.
  • the material of the cap layer 54 may include silicon oxide, oxynitride, silicon nitride, or silicon carbide (SiC).
  • a thermal oxide layer 56 and a spacer 58 are respectively formed on the sidewall of the gate structure 38 A, 38 B.
  • the spacers 58 may be a single-layered structure or a multi-layered structure.
  • the preferred material of the first spacers 58 may use silicon oxide, silicon nitride, oxynitride, or other adoptable dielectric material.
  • a plurality of isolation structures is disposed between the MOS transistors to prevent short-circuiting, such as shallow trench isolations 48 formed between the PMOS transistor 32 and the NMOS transistor 34 .
  • the CMOS transistor 30 has lightly doped drain 50 A, 50 B respectively disposed beside the gate structure 38 A, 38 B to prevent hot electron effect in the PMOS transistor 32 or the NMOS transistor 34 .
  • the source/drain 46 of the PMOS transistor 32 has Ge therein.
  • the source/drain 46 of the PMOS transistor 32 of the present embodiment is formed by several processes.
  • a patterned photoresist (not shown) is formed on the PMOS transistor 32 , and an etch process is performed to form at least a recess (not shown) on the surface of the semiconductor substrate 30 beside the gate structure 38 B of the PMOS transistor 32 .
  • a selective epitaxial growth process is performed to form a SiGe epitaxial layer in the recess, wherein the SiGe epitaxial layer has a greater lattice constant than that of the semiconductor substrate 30 , and is slightly extended approaching to the channel.
  • the SiGe epitaxial layer is slightly projected from the top surface of the semiconductor substrate 30 to compress the channel and to keep silicide formed in the following steps from the interface between the source/drain in a distance.
  • the top surface of the SiGe epitaxial layer may be substantially leveled with or lower than the top surface of semiconductor substrate 30 .
  • a heavy doped (P + ) implantation process is performed to implant P-type dopant, such as boron (B), into the SiGe epitaxial layer.
  • P-type dopant such as boron (B)
  • a mask (not shown) is formed covering the NMOS transistor 34 , and a carbon implantation process is performed to implant carbon into the source/drain 46 of the PMOS transistor 32 .
  • a carbon-doped layer 60 is formed in the top portion of the source/drain 46 , and the carbon-doped layer 60 has a thickness between 100 angstrom ( ⁇ ) and 500 ⁇ , preferably between 200 ⁇ and 300 ⁇ .
  • the implantation energy is determined by the depth of the dopant.
  • the preferred implantation energy of the carbon implantation process is approximately between 1 KeV and 5 KeV, and the implantation dosage is approximately between 10 13 atom/cm 2 and 10 16 atom/cm 2 .
  • the preferred implantation energy of the present embodiment is about 2 KeV, and the preferred implantation dosage is about 1.05 ⁇ 10 15 atom/cm 2 .
  • the carbon implantation of the present invention may also be performed on the NMOS transistor 32 simultaneously.
  • An annealing process is optionally performed using a furnace or a rapid thermal process (RTP) to activate the doped carbon and to repair the lattice structure of the semiconductor substrate 30 at approximately between 1000° C. and 1050° C.
  • RTP rapid thermal process
  • a self-aligned silicide process is performed to form silicide layer 62 on the surface of the source/drain 40 , 46 .
  • the silicide layer 62 may include nickel and platinum, and has a thickness between 50 ⁇ and 500 ⁇ , preferably between 100 ⁇ and 300 ⁇ .
  • the steps of the salicide process are well known, and will not be described in detail.
  • a first liner 64 and a tensile thin film 65 are respectively formed covering the PMOS transistor 32 , the NMOS transistor 34 and the semiconductor substrate 30 .
  • the tensile thin film 65 of the present invention is a multi-layered tensile thin film, and includes a buffered tensile thin film 66 and a high tensile thin film 68 .
  • the buffered tensile thin film has a lower tensile stress than that of the high tensile thin film.
  • a surface treatment is optional performed, i.e. an RTP or an UV curing process, to enhance the tensile strain of the tensile thin film 65 .
  • a second liner 70 is formed.
  • the spacers 58 disposed on the sidewall of the PMOS transistor 32 and the NMOS transistor 34 may be removed before the formation of the first liner 64 , the tensile thin film 65 , and the second liner 70 . Accordingly, the tensile thin film 65 may induce tensile stress into the channel region of the NMOS transistor 34 more effectively.
  • a first patterned photoresist 72 is formed on the NMOS transistor 34 after the second liner 70 is formed.
  • the formation of the first patterned photoresist 72 includes steps of coating the photoresist, an exposing process and a developing process to define the pattern.
  • An etch process is performed, such as an isotropic etch process, using the first patterned photoresist 72 as an etch mask to remove the buffered tensile thin film 66 , the high tensile thin film 68 , and the second liner 70 formed on the PMOS transistor 32 .
  • the first liner 64 acts as an etch stop layer and protects the PMOS transistor 32 during the etch process. As shown in FIG.
  • the first pattern photoresist 72 is removed and a high compressive thin film 74 is formed covering the PMOS transistor 32 and the NMOS transistor 34 .
  • the high compressive thin film 74 of the present embodiment is formed by another PECVD process, and other methods for depositing the high compressive thin film 74 are allowable.
  • a second patterned photoresist 76 is formed on the NMOS transistor 32 .
  • the formation of the second patterned photoresist 76 includes steps of: coating the photoresist, an exposing process and a developing process to define the pattern.
  • Another etch process is performed using the second patterned photoresist 76 as an etch mask to remove the exposed thin film, for instance, the high compressive thin film 74 and the second liner 70 disposed on the NMOS transistor 34 , and so that the high compressive thin film 74 disposed on the gate structure 38 B and the surface of the source/drain 46 of the PMOS 74 is protected.
  • the second patterned photoresist 76 disposed on the PMOS transistor 32 is removed, and therefore, the basic structure of a CMOS transistor 78 is formed by the method of the present invention.
  • the tensile thin film 65 disposed on the NMOS 34 and the high compressive thin film 74 disposed on the PMOS transistor 32 may act as a CESL of the CMOS transistor 78 .
  • an inter-layer dielectric (ILD) layer (not shown) and a patterned photoresist (not shown) are formed, and an anisotropic etching process is performed using the patterned photoresist as an etching mask to form a plurality of contact holes (not shown) in the ILD layer and the CESL (the tensile thin film 65 and the high compressive thin film 74 ).
  • the contact holes are the connections between the gate structures 38 A, 38 B or the sources/drains 40 , 46 of the PMOS transistor 32 and the NMOS transistor 34 with other electrical devices.
  • FIG. 10 is a flow diagram illustrating the method of manufacturing the CMOS transistor of the present invention. The steps of the present embodiment are illustrated as follows.
  • Step 100 A semiconductor substrate is provided.
  • the semiconductor substrate has at least a PMOS transistor and at least an NMOS transistor formed thereon.
  • the source/drain of the PMOS transistor is a SiGe epitaxial layer.
  • Step 102 A carbon implantation process is performed upon the source/drain of the PMOS transistor.
  • a carbon-doped layer is formed in the top portion of the source/drain of the PMOS transistor.
  • Step 104 A salicide process is performed to form a silicide layer on the respective source/drain of the PMOS transistor and the NMOS transistor.
  • Step 106 A tensile thin film is formed.
  • the tensile thin film includes a buffered tensile thin film and a high tensile thin film.
  • the high tensile thin film has a greater stress status than that of the buffered tensile thin film.
  • Step 108 A surface treatment is performed, such as an RTP or an UV curing process, to strengthen the stress status of the tensile thin film.
  • Step 110 A portion of the tensile thin film disposed on the PMOS transistor is removed.
  • Step 112 A high compressive thin film is formed covering the PMOS transistor and the NMOS transistor.
  • Step 114 A portion of the high compressive thin film disposed on the NMOS transistor is removed.
  • the tensile thin film 65 disposed on the PMOS transistor 78 may be preserved for simplifying steps of fabricating the CMOS transistor 78 of the present invention.
  • the formation of the high compressive thin film 78 on the PMOS transistor 32 is optional.
  • FIG. 11 is a SEM photo of the CMOS transistor 78 manufactured by the method of the present invention.
  • Ge-out diffusion occurs at the conventional CMOS transistor 10 and forms a plurality of black spots on the nickel silicide layer 26 shown in FIG. 2 .
  • no black spot is observed on the silicide 62 of the CMOS transistor 78 formed by the method of the present invention.
  • the present invention utilizing a carbon implantation process prior to the formation of the silicide, to implant carbon, which has a smaller radius than the silicon and is neutral, into the source/drain 46 of the PMOS transistor 32 , in which the source drain 46 of the PMOS transistor 32 comprises SiGe epitaxial layer.
  • the buffered tensile thin film 66 is formed between the high tensile thin film 68 and the silicide layer 62 .
  • the Ge-out diffusion is suppressed in proportion to the thickness of the buffered tensile thin film 66 .
  • thickness increase of the buffered tensile thin film 66 reduces the ion gain effect of the CMOS transistor 78 .
  • the present invention using the carbon implantation process to implant carbon as dopant into the lattice of the SiGe epitaxial layer for stabilizing the Ge atom in the SiGe epitaxial layer, reducing the thickness of the buffered tensile thin film 66 and maintaining the ion gain effect of the CMOS transistor 78 . And accordingly, the present invention combines the carbon-doped layer 60 formed by the carbon implantation process and the buffered tensile thin film 66 to prevent Ge-out diffusion.
  • other amorphous dopants i.e. Ar, Ge, In, which have a smaller radius than the silicon and are neutral, are useless for preventing Ge-out diffusion.
  • the formation of the carbon-doped layer in the top portion of the source/drain 46 of the 32 is not limited to be formed prior to the formation of the silicide, which are illustrated in the preferred embodiment.
  • the carbon-doped layer may be formed during the formation of the source/drain 46 of the PMOS transistor 32 .
  • a carbon implantation process is performed prior to the heavy doped implantation process for implanting P-type dopants into the semiconductor substrate 30 .
  • the carbon implantation process may be performed after the heavy doped implantation process.
  • the carbon-doped layer may be formed during the selective epitaxial growth process for forming the SiGe epitaxial layer.
  • carbon may be added as material of the epitaxial layer during the selective epitaxial growth process.
  • the concentration of the carbon may be increased during the formation of the SiGe epitaxial layer. Therefore, a carbon-doped layer is formed, in which the concentration of the carbon is higher in the later formed SiGe epitaxial layer than in the prior formed SiGe epitaxial layer.
  • a buffered tensile thin film and a high tensile thin film are formed on the CMOS transistor to prevent Ge-out diffusion.
  • another carbon implantation process may be performed on the SiGe epitaxial layer having the carbon-doped layer thereof to increase the concentration of the carbon in the top portion of the source/drain of the PMOS transistor.
  • the present invention utilizes a carbon implantation process to implant carbon into the top portion of the source/drain of the PMOS transistor, particularly to the portion approaching to the surface of the source/drain of the PMOS transistor.
  • the carbon implantation process is performed before the salicide process.
  • a silicide layer and a CESL having tensile strain or compressive strain are formed on the NMOS transistor and the PMOS transistor. Therefore, the CMOS transistor of the present invention is formed.
  • the carbon-doped layer may act as a barrier layer during several high temperature processes, such as the salicide process, the annealing process, and the RTP process.
  • the CMOS transistor is silicon cap-free, and therefore, the SiGe epitaxial layer has a facet near the spacer for providing a better compressive strain into the channel region of the PMOS for increasing carrier mobility thereof.

Abstract

A CMOS transistor and a method for manufacturing the same are disclosed. A semiconductor substrate having at least a PMOS transistor and an NMOS transistor is provided. The source/drain of the PMOS transistor comprises SiGe epitaxial layer. A carbon implantation process is performed to form a carbon-doped layer in the top portion of the source/drain of the PMOS transistor. A silicide layer is formed on the source/drain. A CESL is formed on the PMOS transistor and the NMOS transistor. The formation of the carbon-doped layer is capable of preventing Ge out-diffusion.

Description

    BACKGROUND OF THE INVENTION
  • 1. Field of the Invention
  • The present invention is related to a CMOS transistor and a method for manufacturing the same, and particularly, to a CMOS transistor capable of preventing Ge out-diffusion and a method for manufacturing the same.
  • 2. Description of the Prior Art
  • Industrial circles are used to reducing device dimensions to improve the performance of metal-oxide semiconductor (MOS) transistors. However, this method has encountered difficulties with high-expenses and technical bottlenecks in recent years. For these reasons, the industrial circles seek other methods to improve MOS transistor performance. And accordingly, a popular method is to utilize the material characteristics to cause strain effect on MOS transistors.
  • In order to increase the driving current of a complementary metal-oxide semiconductor (CMOS) transistor including a p-type MOS (PMOS) transistor and an n-type MOS (NMOS) transistor, the industrial circles develop a strained-silicon technique, which uses unique processes or lattice constant discrepancy to increase driving current. The strained-silicon technique substantially includes a substrate-strained based method and a process-induced strain based method. The substrate-strained based system is performed with a strained-silicon substrate or a selective epitaxial growth process that results in lattice constant discrepancy. The process-induced strain based method is performed with several unique processes to form a strained thin film upon a surface of the MOS transistor that exert tensile stress or compressive stress upon the MOS transistor. Both of the strained-silicon techniques introduce strain into the channel region and reduce carrier mobile resistance thereby improving carrier mobility and MOS transistor performance.
  • Please refer to FIG. 1, which is a schematic diagram illustrating a conventional CMOS transistor 10. The CMOS transistor 10 includes a PMOS transistor 12 and an NMOS transistor 14 disposed on a substrate 16. A plurality of shallow trench isolations (STI) 30 is disposed on the substrate 16 to prevent short-circuiting between the PMOS transistor 12 and the NMOS transistor 14. The NMOS transistor 14 having a source/drain 20A and a gate structure 22A is disposed on a P well 18 formed in the substrate 16. The PMOS transistor 12 having a source/drain 20B and a gate structure 22B is disposed on an N well 24 formed in the substrate 16. The source/drain 20B of the PMOS transistor 12 is a silicon germanium (SiGe) epitaxial layer. A compressive strain resulting from the lattice constant discrepancy of SiGe epitaxial layer is induced into the channel region of the PMOS transistor 12. Nickel silicide layers 26 are respectively formed on the surface of the source/ drain 20A, 20B for increasing the Ohmic contact capability between metals and the silicon substrate. In order to enhance carrier mobility of the channel region of the NMOS transistor 14, a high tensile thin film 28 is formed on the CMOS transistor 10. The high tensile thin film 28 is disposed covering the gate structure 22A, 22B and the source/ drain 20A, 20B. Thereafter, an UV curing process is performed by a UV radiation to enhance the tensile strain of the high tensile thin film 28 that results in elongating the distance of the lattice of the channel region positioned under the gate structure 22A of the NMOS transistor 14. Therefore, the NMOS transistor 14 has a higher driving current and a better electron mobility in the channel region.
  • Tensile strain of the high tensile thin film 28 is adjusted by the UV curing process for improving performance of NMOS transistor 14. However, the tensile strain results in Ge-out diffusion at the source/drain 20B of the PMOS transistor 12. As shown in FIG. 2, which is a SEM photo of the CMOS transistor 10, a plurality of black spots are formed on the surface of the nickel silicide layer 26, in which is the evidence of the Ge-out diffusion. Besides, Ge-out diffusion results in silicide agglomeration that increases resistance, reduces the concentration of the Ge in the SiGe epitaxial layer, and affects the accuracy of the threshold voltage of the PMOS transistor 12.
    • SUMMARY OF THE INVENTION
  • In order to overcome the issue of Ge-out diffusion, the present invention provides a method of manufacturing a CMOS transistor, which is capable of preventing Ge-out diffusion. Initially, a semiconductor substrate having at least a PMOS transistor and an NMOS transistor is provided. The source/drain of the PMOS transistor has Ge therein. A carbon-doped layer is formed at the top portion of the source/drain of the PMOS transistor. A self-aligned silicide process is performed. At least a tensile thin film is formed covering the semiconductor substrate, the NMOS transistor, and the PMOS transistor. A surface treatment is performed upon the tensile thin film.
  • In addition, the present invention further discloses a CMOS transistor. The CMOS transistor has a semiconductor substrate, at least a NMOS transistor and at least a PMOS transistor disposed on the semiconductor substrate, and a CESL disposed on the PMOS transistor and the NMOS transistor. The PMOS transistor has a source/drain, which includes Ge therein. A carbon-doped layer is disposed in the top portion of the source/drain of the PMOS transistor, and so that, the CMOS transistor of the present invention is capable of preventing Ge-out diffusion.
  • The CMOS transistor formed by the method of the present invention has a carbon-doped layer in the top portion of the source/drain of the PMOS transistor. Therefore, the concentration of the Ge dopant is maintained in the source/drain of the PMOS transistor and the issue of Ge-out diffusion is solved.
  • These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings.
    • BRIEF DESCRIPTION OF THE DRAWINGS
  • FIG. 1 is a schematic diagram illustrating a conventional CMOS transistor.
  • FIG. 2 is a SEM photo of the conventional CMOS transistor.
  • FIG. 3 to FIG. 9 are schematic diagrams illustrating a method for manufacturing a CMOS transistor according to a preferred embodiment of the present invention.
  • FIG. 10 is a flow diagram of the method of the present invention to manufacture the CMOS transistor for preventing Ge-out diffusion.
  • FIG. 11 is a SEM photo of the CMOS transistor manufactured by the method of the present invention.
    •  DETAILED DESCRIPTION
  • Please refer to FIG. 3 through FIG. 10. FIG. 3 to FIG. 9 are schematic diagrams illustrating a method for manufacturing a CMOS transistor according to a preferred embodiment of the present invention. FIG. 10 is a flow diagram of the method of the present invention to manufacture the CMOS transistor for preventing Ge-out diffusion. Please refer to FIG. 3. A semiconductor substrate 30 is provided, in which the semiconductor substrate 30 has at least a PMOS transistor 32 and an NMOS transistor 34 disposed thereon. The NMOS transistor 34 is formed in a P well 36 disposed in the semiconductor substrate 30. The NMOS transistor 34 includes a gate structure 38A formed on the surface of the semiconductor substrate 30 and a source/drain 40 disposed beside the gate structure 38A. The PMOS transistor 32 is formed in an N well 44. The PMOS transistor 32 includes a gate structure 38B formed on the surface of the semiconductor substrate 30 and a source/drain 46 disposed beside the gate structure 38B.
  • Each of the gate structure 38A, 38B includes a gate dielectric layer 50, a gate 52, and a cap layer 54. The gate dielectric layer 50 may include dielectric materials including silicon oxide, oxynitride, and silicon nitride; high-k dielectric materials including metal oxide, metal silicate, metal aluminate, and metal oxynitride; or combinations thereof. The gate dielectric layer 50 may be formed by a thermal oxidation process, a nitridation process, or a chemical vapor deposition (CVD) process. The gate 52 may use polysilicon, SiGe, metal, silicide, metal nitride, metal oxide, or combinations thereof as material. The material of the cap layer 54 may include silicon oxide, oxynitride, silicon nitride, or silicon carbide (SiC). A thermal oxide layer 56 and a spacer 58 are respectively formed on the sidewall of the gate structure 38A, 38B. The spacers 58 may be a single-layered structure or a multi-layered structure. The preferred material of the first spacers 58 may use silicon oxide, silicon nitride, oxynitride, or other adoptable dielectric material. In addition, a plurality of isolation structures is disposed between the MOS transistors to prevent short-circuiting, such as shallow trench isolations 48 formed between the PMOS transistor 32 and the NMOS transistor 34. The CMOS transistor 30 has lightly doped drain 50A, 50B respectively disposed beside the gate structure 38A, 38B to prevent hot electron effect in the PMOS transistor 32 or the NMOS transistor 34.
  • In order to enhance the carrier mobility of the channel region of the PMOS transistor disposed under the gate structure 38, the source/drain 46 of the PMOS transistor 32 has Ge therein. The source/drain 46 of the PMOS transistor 32 of the present embodiment is formed by several processes. A patterned photoresist (not shown) is formed on the PMOS transistor 32, and an etch process is performed to form at least a recess (not shown) on the surface of the semiconductor substrate 30 beside the gate structure 38B of the PMOS transistor 32. A selective epitaxial growth process is performed to form a SiGe epitaxial layer in the recess, wherein the SiGe epitaxial layer has a greater lattice constant than that of the semiconductor substrate 30, and is slightly extended approaching to the channel. Preferably, the SiGe epitaxial layer is slightly projected from the top surface of the semiconductor substrate 30 to compress the channel and to keep silicide formed in the following steps from the interface between the source/drain in a distance. The top surface of the SiGe epitaxial layer may be substantially leveled with or lower than the top surface of semiconductor substrate 30. A heavy doped (P+) implantation process is performed to implant P-type dopant, such as boron (B), into the SiGe epitaxial layer. Thus, the formation of the source/drain 46 of the PMOS transistor 34 is accomplished.
  • As shown in FIG. 4, a mask (not shown) is formed covering the NMOS transistor 34, and a carbon implantation process is performed to implant carbon into the source/drain 46 of the PMOS transistor 32. A carbon-doped layer 60 is formed in the top portion of the source/drain 46, and the carbon-doped layer 60 has a thickness between 100 angstrom (Å) and 500 Å, preferably between 200 Å and 300 Å. The implantation energy is determined by the depth of the dopant. The preferred implantation energy of the carbon implantation process is approximately between 1 KeV and 5 KeV, and the implantation dosage is approximately between 1013 atom/cm2 and 1016 atom/cm2. The preferred implantation energy of the present embodiment is about 2 KeV, and the preferred implantation dosage is about 1.05×1015 atom/cm2. In addition, the carbon implantation of the present invention may also be performed on the NMOS transistor 32 simultaneously. An annealing process is optionally performed using a furnace or a rapid thermal process (RTP) to activate the doped carbon and to repair the lattice structure of the semiconductor substrate 30 at approximately between 1000° C. and 1050° C. Thereafter, a self-aligned silicide process (salicide process) is performed to form silicide layer 62 on the surface of the source/ drain 40, 46. The silicide layer 62 may include nickel and platinum, and has a thickness between 50 Å and 500 Å, preferably between 100 Å and 300 Å. The steps of the salicide process are well known, and will not be described in detail.
  • As shown in FIG. 5, a first liner 64 and a tensile thin film 65 are respectively formed covering the PMOS transistor 32, the NMOS transistor 34 and the semiconductor substrate 30. The tensile thin film 65 of the present invention is a multi-layered tensile thin film, and includes a buffered tensile thin film 66 and a high tensile thin film 68. The buffered tensile thin film has a lower tensile stress than that of the high tensile thin film. A surface treatment is optional performed, i.e. an RTP or an UV curing process, to enhance the tensile strain of the tensile thin film 65. Then, a second liner 70 is formed. In addition, the spacers 58 disposed on the sidewall of the PMOS transistor 32 and the NMOS transistor 34 may be removed before the formation of the first liner 64, the tensile thin film 65, and the second liner 70. Accordingly, the tensile thin film 65 may induce tensile stress into the channel region of the NMOS transistor 34 more effectively.
  • Please refer to FIG. 6, in which a first patterned photoresist 72 is formed on the NMOS transistor 34 after the second liner 70 is formed. The formation of the first patterned photoresist 72 includes steps of coating the photoresist, an exposing process and a developing process to define the pattern. An etch process is performed, such as an isotropic etch process, using the first patterned photoresist 72 as an etch mask to remove the buffered tensile thin film 66, the high tensile thin film 68, and the second liner 70 formed on the PMOS transistor 32. The first liner 64 acts as an etch stop layer and protects the PMOS transistor 32 during the etch process. As shown in FIG. 7, the first pattern photoresist 72 is removed and a high compressive thin film 74 is formed covering the PMOS transistor 32 and the NMOS transistor 34. The high compressive thin film 74 of the present embodiment is formed by another PECVD process, and other methods for depositing the high compressive thin film 74 are allowable.
  • As shown in FIG. 8, a second patterned photoresist 76 is formed on the NMOS transistor 32. The formation of the second patterned photoresist 76 includes steps of: coating the photoresist, an exposing process and a developing process to define the pattern. Another etch process is performed using the second patterned photoresist 76 as an etch mask to remove the exposed thin film, for instance, the high compressive thin film 74 and the second liner 70 disposed on the NMOS transistor 34, and so that the high compressive thin film 74 disposed on the gate structure 38B and the surface of the source/drain 46 of the PMOS 74 is protected.
  • As shown in FIG. 9, the second patterned photoresist 76 disposed on the PMOS transistor 32 is removed, and therefore, the basic structure of a CMOS transistor 78 is formed by the method of the present invention. The tensile thin film 65 disposed on the NMOS 34 and the high compressive thin film 74 disposed on the PMOS transistor 32 may act as a CESL of the CMOS transistor 78. Furthermore, an inter-layer dielectric (ILD) layer (not shown) and a patterned photoresist (not shown) are formed, and an anisotropic etching process is performed using the patterned photoresist as an etching mask to form a plurality of contact holes (not shown) in the ILD layer and the CESL (the tensile thin film 65 and the high compressive thin film 74). The contact holes are the connections between the gate structures 38A, 38B or the sources/drains 40, 46 of the PMOS transistor 32 and the NMOS transistor 34 with other electrical devices.
  • Please refer to FIG. 10, which is a flow diagram illustrating the method of manufacturing the CMOS transistor of the present invention. The steps of the present embodiment are illustrated as follows.
  • Step 100: A semiconductor substrate is provided. The semiconductor substrate has at least a PMOS transistor and at least an NMOS transistor formed thereon. The source/drain of the PMOS transistor is a SiGe epitaxial layer.
  • Step 102: A carbon implantation process is performed upon the source/drain of the PMOS transistor. A carbon-doped layer is formed in the top portion of the source/drain of the PMOS transistor.
  • Step 104: A salicide process is performed to form a silicide layer on the respective source/drain of the PMOS transistor and the NMOS transistor.
  • Step 106: A tensile thin film is formed. The tensile thin film includes a buffered tensile thin film and a high tensile thin film. The high tensile thin film has a greater stress status than that of the buffered tensile thin film.
  • Step 108: A surface treatment is performed, such as an RTP or an UV curing process, to strengthen the stress status of the tensile thin film.
  • Step 110: A portion of the tensile thin film disposed on the PMOS transistor is removed.
  • Step 112: A high compressive thin film is formed covering the PMOS transistor and the NMOS transistor.
  • Step 114: A portion of the high compressive thin film disposed on the NMOS transistor is removed.
  • Additionally, the tensile thin film 65 disposed on the PMOS transistor 78 may be preserved for simplifying steps of fabricating the CMOS transistor 78 of the present invention. The formation of the high compressive thin film 78 on the PMOS transistor 32 is optional.
  • Please refer to FIG. 11, which is a SEM photo of the CMOS transistor 78 manufactured by the method of the present invention. Referring to FIG. 2 and FIG. 11, Ge-out diffusion occurs at the conventional CMOS transistor 10 and forms a plurality of black spots on the nickel silicide layer 26 shown in FIG. 2. In contrast, no black spot is observed on the silicide 62 of the CMOS transistor 78 formed by the method of the present invention.
  • As described above, the present invention utilizing a carbon implantation process prior to the formation of the silicide, to implant carbon, which has a smaller radius than the silicon and is neutral, into the source/drain 46 of the PMOS transistor 32, in which the source drain 46 of the PMOS transistor 32 comprises SiGe epitaxial layer. Additionally, the buffered tensile thin film 66 is formed between the high tensile thin film 68 and the silicide layer 62. According to our experiment, the Ge-out diffusion is suppressed in proportion to the thickness of the buffered tensile thin film 66. However, thickness increase of the buffered tensile thin film 66 reduces the ion gain effect of the CMOS transistor 78. Therefore, the present invention using the carbon implantation process to implant carbon as dopant into the lattice of the SiGe epitaxial layer for stabilizing the Ge atom in the SiGe epitaxial layer, reducing the thickness of the buffered tensile thin film 66 and maintaining the ion gain effect of the CMOS transistor 78. And accordingly, the present invention combines the carbon-doped layer 60 formed by the carbon implantation process and the buffered tensile thin film 66 to prevent Ge-out diffusion. However, other amorphous dopants, i.e. Ar, Ge, In, which have a smaller radius than the silicon and are neutral, are useless for preventing Ge-out diffusion.
  • Furthermore, the formation of the carbon-doped layer in the top portion of the source/drain 46 of the 32 is not limited to be formed prior to the formation of the silicide, which are illustrated in the preferred embodiment. The carbon-doped layer may be formed during the formation of the source/drain 46 of the PMOS transistor 32. For instance, a carbon implantation process is performed prior to the heavy doped implantation process for implanting P-type dopants into the semiconductor substrate 30. In addition, the carbon implantation process may be performed after the heavy doped implantation process. On the other hand, the carbon-doped layer may be formed during the selective epitaxial growth process for forming the SiGe epitaxial layer. For instance, carbon may be added as material of the epitaxial layer during the selective epitaxial growth process. The concentration of the carbon may be increased during the formation of the SiGe epitaxial layer. Therefore, a carbon-doped layer is formed, in which the concentration of the carbon is higher in the later formed SiGe epitaxial layer than in the prior formed SiGe epitaxial layer. After the SiGe epitaxial layer having the carbon-doped layer is formed, a buffered tensile thin film and a high tensile thin film are formed on the CMOS transistor to prevent Ge-out diffusion. In addition, another carbon implantation process may be performed on the SiGe epitaxial layer having the carbon-doped layer thereof to increase the concentration of the carbon in the top portion of the source/drain of the PMOS transistor.
  • According to afore-mentioned embodiment, the present invention utilizes a carbon implantation process to implant carbon into the top portion of the source/drain of the PMOS transistor, particularly to the portion approaching to the surface of the source/drain of the PMOS transistor. The carbon implantation process is performed before the salicide process. After that, a silicide layer and a CESL having tensile strain or compressive strain are formed on the NMOS transistor and the PMOS transistor. Therefore, the CMOS transistor of the present invention is formed. The carbon-doped layer may act as a barrier layer during several high temperature processes, such as the salicide process, the annealing process, and the RTP process. In addition, the CMOS transistor is silicon cap-free, and therefore, the SiGe epitaxial layer has a facet near the spacer for providing a better compressive strain into the channel region of the PMOS for increasing carrier mobility thereof.
  • Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention.

Claims (20)

1. A method of forming a CMOS transistor, comprising:
providing a semiconductor substrate having at least an NMOS transistor and at least a PMOS transistor thereon, and a source/drain of the PMOS transistor comprising germanium (Ge);
forming a carbon-doped layer in the top portion of the source/drain of the PMOS transistor;
performing a self-aligned silicide process;
forming at least a tensile thin film covering the semiconductor substrate, the NMOS transistor, and the PMOS transistor; and
performing a surface treatment on the tensile thin film.
2. The method of claim 1, wherein the carbon-doped layer is formed by a carbon implantation process.
3. The method of claim 2, wherein the carbon implantation process is performed with an implantation energy between 1 KeV and 5 KeV, and with an implantation dosage between 1013 atom/cm2 and 1016 atom/cm2.
4. The method of claim 2, wherein the source/drain of the PMOS transistor is formed comprising a step of a heavy doped implantation process to implant P-type dopant into the semiconductor substrate, and the carbon implantation process is performed before the heavy doped implantation process.
5. The method of claim 2, wherein the source/drain of the PMOS transistor is formed comprising a step of a heavy doped implantation process to implant P-type dopant into the semiconductor substrate, and the carbon implantation process is performed after the heavy doped implantation process.
6. The method of claim 1, wherein the source/drain of the PMOS transistor is formed comprising steps of:
performing a etch process to form at least a recess on the surface of the semiconductor substrate in the PMOS transistor; and
performing a selective epitaxial growth process to form a SiGe epitaxial layer in the recess, wherein the carbon-doped layer is formed during the selective epitaxial growth process.
7. The method of claim 6, wherein the selective growth process comprises carbon as material.
8. The method of claim 7, wherein the concentration of the carbon is increased during the formation of the SiGe epitaxial layer.
9. The method of claim 1, wherein the surface treatment comprises a rapid thermal process (RTP) or an UV curing process.
10. The method of claim 1, wherein the tensile thin film comprises a multi-layered tensile thin film.
11. The method of claim 10, wherein the multi-layered tensile thin film comprises a buffered tensile thin film and a high tensile thin film, and the buffered tensile thin film has a lower tensile stress than that of the high tensile thin film.
12. The method of claim 1, further comprising forming a high compressive thin film covering the PMOS transistor after the tensile thin film is formed.
13. A CMOS transistor, comprising:
a semiconductor substrate;
at least an NMOS transistor disposed on the semiconductor substrate, the NMOS transistor comprising a P well , a gate structure disposed on a surface of the P well, and a source/drain beside the gate structure;
at least a PMOS transistor disposed on the semiconductor substrate, the PMOS transistor comprising an N well, a gate structure disposed on a surface of the N well, and a source/drain beside the gate structure, wherein the source/drain of the PMOS transistor comprises a carbon-doped layer in the top portion thereof; and
a contact hole etch stop layer (CESL) disposed on the NMOS transistor and the PMOS transistor.
14. The CMOS transistor of claim 13, wherein the source/drain of the PMOS transistor comprises Ge.
15. The CMOS transistor of claim 14, wherein the source/drain of the PMOS transistor comprises a SiGe epitaxial layer.
16. The CMOS transistor of claim 13, wherein the carbon-doped layer has a thickness between 100 angstrom (Å) and 500 Å.
17. The CMOS transistor of claim 13, wherein a salicide layer is disposed on each of the source/drain, and the silicide layer has a thickness between 50 Å and 500 Å.
18. The CMOS transistor of claim 10, wherein a portion of the CESL disposed on the NMOS comprises a tensile thin film, and the other portion of the CESL disposed on the PMOS comprises a high compressive thin film.
19. The CMOS transistor of claim 18, wherein the tensile thin film comprises a multi-layered tensile thin film.
20. The CMOS transistor of claim 19, wherein the multi-layered tensile thin film comprises a buffered tensile thin film and a high tensile thin film, and the buffered tensile thin film has a lower tensile stress than that of the high tensile thin film.
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