JP2012516036A5 - - Google Patents

Download PDF

Info

Publication number
JP2012516036A5
JP2012516036A5 JP2011546308A JP2011546308A JP2012516036A5 JP 2012516036 A5 JP2012516036 A5 JP 2012516036A5 JP 2011546308 A JP2011546308 A JP 2011546308A JP 2011546308 A JP2011546308 A JP 2011546308A JP 2012516036 A5 JP2012516036 A5 JP 2012516036A5
Authority
JP
Japan
Prior art keywords
layer
device region
dielectric layer
dielectric
silicon germanium
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2011546308A
Other languages
English (en)
Other versions
JP5582582B2 (ja
JP2012516036A (ja
Filing date
Publication date
Priority claimed from US12/357,057 external-priority patent/US8017469B2/en
Application filed filed Critical
Publication of JP2012516036A publication Critical patent/JP2012516036A/ja
Publication of JP2012516036A5 publication Critical patent/JP2012516036A5/ja
Application granted granted Critical
Publication of JP5582582B2 publication Critical patent/JP5582582B2/ja
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Claims (5)

  1. 半導体製造方法であって、
    ＮＭＯＳデバイス領域およびＰＭＯＳデバイス領域を有する第１半導体層を備えたウェハを提供するステップと、
    少なくとも前記ＰＭＯＳデバイス領域の上に、圧縮シリコンゲルマニウム層を形成するステップと、
    前記圧縮シリコンゲルマニウム層の上に、堆積された第１高Ｋ誘電体層を選択的に形成するステップであって、第１高Ｋ誘電体層は７．０またはそれより高い第１誘電率を有する第１誘電体材料から形成されるステップと、
    前記ＮＭＯＳデバイス領域の前記第１半導体層上に、および前記ＰＭＯＳデバイス領域の前記第１半導体層上に、第２高Ｋ誘電体層を堆積させるステップであって、第２高Ｋ誘電体層は前記第１誘電率より高い誘電率を有する第２誘電体材料から形成されるステップと、
    前記第２高Ｋ誘電体層上に、１つまたは複数のゲート電極層を堆積するステップと、
    を含む方法。
  2. 請求項１に記載の半導体製造方法であって、
    前記圧縮シリコンゲルマニウム層を形成するステップは、シリコンゲルマニウムを所定厚までエピタキシャル成長させるステップを含む方法。
  3. 請求項１に記載の半導体製造方法であって、
    前記堆積された前記第１高Ｋ誘電体層を選択的に形成するステップは、前記圧縮シリコンゲルマニウム層からゲルマニウム拡散を減少または除去するために選択された温度で行う堆積工程で、シリケートまたは金属酸窒化材料を堆積させることを含む方法。
  4. 請求項１に記載の半導体製造方法であって、
    前記堆積された前記第１高Ｋ誘電体層を選択的に形成するステップは、
    前記ＮＭＯＳデバイス領域および前記ＰＭＯＳデバイス領域上に、前記第１高Ｋ誘電体層をブランケット堆積するステップと、
    前記ＰＭＯＳデバイス領域の前記圧縮シリコンゲルマニウム層を覆うように、パターン化エッチングマスクを形成するステップと、
    前記圧縮シリコンゲルマニウム層上の第１高Ｋ誘電体層を残しつつＮＭＯＳデバイス領域を露出させるように、前記第１高Ｋ誘電体層を選択的にエッチングするステップと、
    を含む方法。
  5. 請求項１に記載の半導体製造方法であって、
    前記第２高Ｋ誘電体層を堆積させるステップは、前記ＰＭＯＳデバイス領域の前記第１高Ｋ誘電体層上に、および前記ＮＭＯＳデバイス領域の前記第１半導体層上に、ＨｆＯ２の層を堆積させることを含む方法。
JP2011546308A 2009-01-21 2010-01-13 ＳｉＧｅチャネルを有するデュアル高Ｋ酸化物 Active JP5582582B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US12/357,057 US8017469B2 (en) 2009-01-21 2009-01-21 Dual high-k oxides with sige channel
US12/357,057 2009-01-21
PCT/US2010/020849 WO2010088039A2 (en) 2009-01-21 2010-01-13 Dual high-k oxides with sige channel

Publications (3)

Publication Number Publication Date
JP2012516036A JP2012516036A (ja) 2012-07-12
JP2012516036A5 true JP2012516036A5 (ja) 2013-02-28
JP5582582B2 JP5582582B2 (ja) 2014-09-03

Family

ID=42337293

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2011546308A Active JP5582582B2 (ja) 2009-01-21 2010-01-13 ＳｉＧｅチャネルを有するデュアル高Ｋ酸化物

Country Status (6)

Country Link
US (2) US8017469B2 (ja)
EP (1) EP2389684A2 (ja)
JP (1) JP5582582B2 (ja)
CN (1) CN102292800B (ja)
TW (1) TWI523149B (ja)
WO (1) WO2010088039A2 (ja)

Families Citing this family (38)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010147104A (ja) * 2008-12-16 2010-07-01 Toshiba Corp 半導体装置の製造方法
KR101589440B1 (ko) * 2009-02-09 2016-01-29 삼성전자주식회사 듀얼 게이트 반도체 장치의 제조 방법
US8048791B2 (en) * 2009-02-23 2011-11-01 Globalfoundries Inc. Method of forming a semiconductor device
US8076730B2 (en) * 2009-06-09 2011-12-13 Infineon Technologies Ag Transistor level routing
CN101964345B (zh) * 2009-07-22 2013-11-13 中国科学院微电子研究所 控制阈值电压特性的CMOSFETs器件结构及其制造方法
US8105892B2 (en) * 2009-08-18 2012-01-31 International Business Machines Corporation Thermal dual gate oxide device integration
US8278165B2 (en) * 2009-10-12 2012-10-02 GlobalFoundries, Inc. Methods for protecting film layers while removing hardmasks during fabrication of semiconductor devices
KR20120107762A (ko) * 2011-03-22 2012-10-04 삼성전자주식회사 반도체 소자의 제조 방법
US20120319207A1 (en) * 2011-06-17 2012-12-20 Toshiba America Electronic Components, Inc. Semiconductor device with threshold voltage control and method of fabricating the same
CN102856203B (zh) * 2011-06-29 2015-04-29 中芯国际集成电路制造(上海)有限公司 Mos晶体管及其形成方法
CN102856204B (zh) * 2011-06-29 2016-04-20 中芯国际集成电路制造(上海)有限公司 晶体管及其形成方法
US8703594B2 (en) * 2011-10-25 2014-04-22 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device having a treated gate structure and fabrication method thereof
US9087687B2 (en) 2011-12-23 2015-07-21 International Business Machines Corporation Thin heterostructure channel device
US20130277766A1 (en) * 2012-04-23 2013-10-24 Globalfoundries Inc. Multiple high-k metal gate stacks in a field effect transistor
US9029959B2 (en) * 2012-06-29 2015-05-12 International Business Machines Corporation Composite high-k gate dielectric stack for reducing gate leakage
US9136177B2 (en) * 2012-07-30 2015-09-15 Globalfoundries Inc. Methods of forming transistor devices with high-k insulation layers and the resulting devices
US8890264B2 (en) * 2012-09-26 2014-11-18 Intel Corporation Non-planar III-V field effect transistors with conformal metal gate electrode and nitrogen doping of gate dielectric interface
US9064726B2 (en) * 2013-03-07 2015-06-23 Texas Instruments Incorporated Low-cost CMOS structure with dual gate dielectrics and method of forming the CMOS structure
KR102054834B1 (ko) 2013-03-15 2019-12-12 삼성전자주식회사 반도체 메모리 소자 및 그 제조 방법
US9087716B2 (en) * 2013-07-15 2015-07-21 Globalfoundries Inc. Channel semiconductor alloy layer growth adjusted by impurity ion implantation
US9373691B2 (en) 2013-08-07 2016-06-21 GlobalFoundries, Inc. Transistor with bonded gate dielectric
KR20160055784A (ko) * 2013-09-27 2016-05-18 인텔 코포레이션 공통 기판 상의 상이한 일함수를 가지는 비-평면 ｉ／ｏ 및 논리 반도체 디바이스들
CN105556676B (zh) 2013-09-27 2019-03-19 英特尔公司 具有ⅲ-ⅴ族材料有源区和渐变栅极电介质的半导体器件
US20150140838A1 (en) * 2013-11-19 2015-05-21 Intermolecular Inc. Two Step Deposition of High-k Gate Dielectric Materials
US9590037B2 (en) 2014-03-19 2017-03-07 International Business Machines Corporation p-FET with strained silicon-germanium channel
US9627608B2 (en) * 2014-09-11 2017-04-18 Lam Research Corporation Dielectric repair for emerging memory devices
FR3030882B1 (fr) * 2014-12-22 2018-03-09 Commissariat A L'energie Atomique Et Aux Energies Alternatives Circuit integre comportant des transistors pmos a tensions de seuil distinctes
KR102365687B1 (ko) 2015-04-21 2022-02-21 삼성전자주식회사 집적회로 소자 및 그 제조 방법
KR102395061B1 (ko) * 2015-07-02 2022-05-10 삼성전자주식회사 반도체 장치 및 그 제조 방법
KR20170036966A (ko) 2015-09-24 2017-04-04 삼성전자주식회사 반도체 소자의 제조하는 방법
US9735061B1 (en) * 2016-02-03 2017-08-15 Globalfoundries Inc. Methods to form multi threshold-voltage dual channel without channel doping
US20180233574A1 (en) * 2017-02-10 2018-08-16 Purdue Research Foundation Silicon carbide power transistor apparatus and method of producing same
US10002939B1 (en) 2017-02-16 2018-06-19 International Business Machines Corporation Nanosheet transistors having thin and thick gate dielectric material
US10504912B2 (en) 2017-07-28 2019-12-10 Taiwan Semiconductor Manufacturing Co., Ltd. Seal method to integrate non-volatile memory (NVM) into logic or bipolar CMOS DMOS (BCD) technology
KR20190034822A (ko) * 2017-09-25 2019-04-03 삼성전자주식회사 반도체 장치
FR3091622B1 (fr) 2019-01-09 2021-09-17 Soitec Silicon On Insulator Structure semi-conductrice optoélectronique comprenant une couche d’injection de type p à base d’InGaN
CN110556341B (zh) * 2019-09-25 2022-02-01 上海华力集成电路制造有限公司 半导体器件的制造方法
CN114765132A (zh) * 2021-01-11 2022-07-19 长鑫存储技术有限公司 半导体结构制作方法及半导体结构

Family Cites Families (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6787421B2 (en) 2002-08-15 2004-09-07 Freescale Semiconductor, Inc. Method for forming a dual gate oxide device using a metal oxide and resulting device
US6921913B2 (en) 2003-03-04 2005-07-26 Taiwan Semiconductor Manufacturing Co., Ltd. Strained-channel transistor structure with lattice-mismatched zone
TWI258811B (en) * 2003-11-12 2006-07-21 Samsung Electronics Co Ltd Semiconductor devices having different gate dielectrics and methods for manufacturing the same
US7662689B2 (en) 2003-12-23 2010-02-16 Intel Corporation Strained transistor integration for CMOS
JP4542807B2 (ja) * 2004-03-31 2010-09-15 東京エレクトロン株式会社 成膜方法および成膜装置、ならびにゲート絶縁膜の形成方法
US8399934B2 (en) * 2004-12-20 2013-03-19 Infineon Technologies Ag Transistor device
US20060157732A1 (en) * 2004-11-09 2006-07-20 Epispeed Sa Fabrication of MOS-gated strained-Si and SiGe buried channel field effect transistors
US7564108B2 (en) 2004-12-20 2009-07-21 Taiwan Semiconductor Manufacturing Company, Ltd. Nitrogen treatment to improve high-k gate dielectrics
JP4588483B2 (ja) * 2005-02-21 2010-12-01 ルネサスエレクトロニクス株式会社 半導体装置
US7524707B2 (en) * 2005-08-23 2009-04-28 Freescale Semiconductor, Inc. Modified hybrid orientation technology
TWI267926B (en) * 2005-09-23 2006-12-01 Ind Tech Res Inst A new method for high mobility enhancement strained channel CMOS with single workfunction metal-gate
US7265004B2 (en) 2005-11-14 2007-09-04 Freescale Semiconductor, Inc. Electronic devices including a semiconductor layer and a process for forming the same
DE102006025218B4 (de) 2006-05-29 2009-02-19 Infineon Technologies Austria Ag Leistungshalbleiterbauelement mit Ladungskompensationsstruktur und Verfahren zur Herstellung desselben
JP4282691B2 (ja) * 2006-06-07 2009-06-24 株式会社東芝 半導体装置
US7709331B2 (en) 2007-09-07 2010-05-04 Freescale Semiconductor, Inc. Dual gate oxide device integration
US8460996B2 (en) 2007-10-31 2013-06-11 Freescale Semiconductor, Inc. Semiconductor devices with different dielectric thicknesses
JP2009229117A (ja) 2008-03-19 2009-10-08 Omron Healthcare Co Ltd 電子体温計
JP5203905B2 (ja) * 2008-12-02 2013-06-05 株式会社東芝 半導体装置およびその製造方法

Similar Documents

Publication Publication Date Title
JP2012516036A5 (ja)
US9331200B1 (en) Semiconductor device and method for fabricating the same
US9876079B2 (en) Nanowire device and method of manufacturing the same
US10084033B2 (en) Semiconductor device and method for forming same
US8951852B2 (en) Semiconductor device and manufacturing method thereof
JP2007311796A (ja) シリコン・ナイトライド・キャップを用いて内因性の応力を加えられたシリサイドを有するｃｍｏｓデバイスを形成するための構造および方法
JP2012504345A5 (ja)
TW201034126A (en) Dual high-k oxides with SiGe channel
US8766371B2 (en) Semiconductor structure and method for manufacturing the same
US8835209B2 (en) Complementary transistors comprising high-k metal gate electrode structures and epitaxially formed semiconductor materials in the drain and source areas
JP2008172234A (ja) 高性能ｃｍｏｓ技術のための低コストの歪みｓｏｉ基板
WO2013059972A1 (zh) 具有双金属栅的cmos器件及其制造方法
JP2006210555A5 (ja)
US20080242020A1 (en) Method of manufacturing a mos transistor device
US9054188B2 (en) Curved wafer processing on method and apparatus
US8692332B2 (en) Strained-silicon transistor and method of making the same
JP2012049248A (ja) 半導体装置およびその製造方法
US8802518B2 (en) Semiconducor device and method for manufacturing the same
JP2011091265A (ja) 半導体装置及びその製造方法
CN108122742A (zh) 半导体装置结构的制造方法
US20160086952A1 (en) Preventing epi damage for cap nitride strip scheme in a fin-shaped field effect transistor (finfet) device
US10312084B2 (en) Semiconductor device and fabrication method thereof
WO2013138952A1 (zh) Cmos器件及其制造方法
TWI591729B (zh) 雙閘極石墨烯場效電晶體及其製造方法
US20110309452A1 (en) Methods of manufacturing semiconductor devices