WO2008126729A1 - 半導体素子およびその製造方法、並びに該半導体素子を備える電子デバイス - Google Patents

半導体素子およびその製造方法、並びに該半導体素子を備える電子デバイス Download PDF

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Publication number
WO2008126729A1
WO2008126729A1 PCT/JP2008/056501 JP2008056501W WO2008126729A1 WO 2008126729 A1 WO2008126729 A1 WO 2008126729A1 JP 2008056501 W JP2008056501 W JP 2008056501W WO 2008126729 A1 WO2008126729 A1 WO 2008126729A1
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WO
WIPO (PCT)
Prior art keywords
semiconductor element
film
laminating
manufacturing
electronic device
Prior art date
Application number
PCT/JP2008/056501
Other languages
English (en)
French (fr)
Inventor
Masao Urayama
Masashi Kawasaki
Hideo Ohno
Original Assignee
Sharp Kabushiki Kaisha
Tohoku University
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sharp Kabushiki Kaisha, Tohoku University filed Critical Sharp Kabushiki Kaisha
Priority to US12/530,552 priority Critical patent/US8173487B2/en
Priority to CN2008800082201A priority patent/CN101632179B/zh
Priority to JP2009509266A priority patent/JPWO2008126729A1/ja
Publication of WO2008126729A1 publication Critical patent/WO2008126729A1/ja

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78696—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/914—Doping
    • Y10S438/922—Diffusion along grain boundaries

Abstract

　本発明の薄膜トランジスタ（１）は、絶縁性基板（２）上にゲート電極（３）を所定の形状に形成された後に、ゲート絶縁膜（４）と該ゲート絶縁膜（４）上に多結晶ＺｎＯである半導体層（５）を順次積層する。半導体層（５）を、不純物を溶解させた溶液中に浸漬することにより、多結晶ＺｎＯ膜の粒界部分に選択的に不純物をドープする。この後、ソース電極（６）およびドレイン電極（７）を所定の形状に形成し、さらに保護膜（８）を積層する。これにより、サブスレッシュホールド特性に優れ、活性層のベースとして酸化亜鉛膜を有する薄膜トランジスタを実現できる。
PCT/JP2008/056501 2007-04-06 2008-04-01 半導体素子およびその製造方法、並びに該半導体素子を備える電子デバイス WO2008126729A1 (ja)

Priority Applications (3)

Application Number Priority Date Filing Date Title
US12/530,552 US8173487B2 (en) 2007-04-06 2008-04-01 Semiconductor element, method for manufacturing same, and electronic device including same
CN2008800082201A CN101632179B (zh) 2007-04-06 2008-04-01 半导体元件及其制造方法、以及包括该半导体元件的电子器件
JP2009509266A JPWO2008126729A1 (ja) 2007-04-06 2008-04-01 半導体素子およびその製造方法、並びに該半導体素子を備える電子デバイス

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2007101133 2007-04-06
JP2007-101133 2007-04-06

Publications (1)

Publication Number Publication Date
WO2008126729A1 true WO2008126729A1 (ja) 2008-10-23

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Family Applications (1)

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PCT/JP2008/056501 WO2008126729A1 (ja) 2007-04-06 2008-04-01 半導体素子およびその製造方法、並びに該半導体素子を備える電子デバイス

Country Status (4)

Country Link
US (1) US8173487B2 (ja)
JP (1) JPWO2008126729A1 (ja)
CN (1) CN101632179B (ja)
WO (1) WO2008126729A1 (ja)

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JP2010165922A (ja) * 2009-01-16 2010-07-29 Idemitsu Kosan Co Ltd 電界効果型トランジスタ、電界効果型トランジスタの製造方法及び半導体素子の製造方法
JP2010182818A (ja) * 2009-02-04 2010-08-19 Sony Corp 薄膜トランジスタおよび表示装置
JP2010267955A (ja) * 2009-04-16 2010-11-25 Semiconductor Energy Lab Co Ltd 半導体装置及びその作製方法
JP2011205081A (ja) * 2010-03-05 2011-10-13 Semiconductor Energy Lab Co Ltd 半導体装置、及び半導体装置の作製方法
JP2012049516A (ja) * 2010-07-27 2012-03-08 Semiconductor Energy Lab Co Ltd 半導体装置及びその作製方法
JP2012216806A (ja) * 2011-04-01 2012-11-08 Semiconductor Energy Lab Co Ltd 半導体装置の作製方法
JP2014068026A (ja) * 2008-11-07 2014-04-17 Semiconductor Energy Lab Co Ltd 半導体装置の作製方法
JP2014525143A (ja) * 2011-07-13 2014-09-25 アプライド マテリアルズ インコーポレイテッド 薄膜トランジスタデバイスの製造方法
JP2015111653A (ja) * 2013-10-30 2015-06-18 株式会社リコー 電界効果型トランジスタ、表示素子、画像表示装置、及びシステム
JP2015133499A (ja) * 2009-07-17 2015-07-23 株式会社半導体エネルギー研究所 表示装置
JP2016186655A (ja) * 2009-08-27 2016-10-27 株式会社半導体エネルギー研究所 表示装置
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JP2017050569A (ja) * 2010-07-02 2017-03-09 株式会社半導体エネルギー研究所 半導体装置
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JP2018186308A (ja) * 2013-10-30 2018-11-22 株式会社リコー 電界効果型トランジスタ、表示素子、画像表示装置、及びシステム
JP2018186279A (ja) * 2010-07-02 2018-11-22 株式会社半導体エネルギー研究所 半導体装置
JP2020077846A (ja) * 2009-09-16 2020-05-21 株式会社半導体エネルギー研究所 表示装置
JP2021040161A (ja) * 2009-12-08 2021-03-11 株式会社半導体エネルギー研究所 半導体装置の作製方法
JP2022033795A (ja) * 2009-10-09 2022-03-02 株式会社半導体エネルギー研究所 表示装置

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Publication number Publication date
US8173487B2 (en) 2012-05-08
CN101632179A (zh) 2010-01-20
JPWO2008126729A1 (ja) 2010-07-22
CN101632179B (zh) 2012-05-30
US20100044702A1 (en) 2010-02-25

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