JP2012216806A - 半導体装置の作製方法 - Google Patents
半導体装置の作製方法 Download PDFInfo
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- JP2012216806A JP2012216806A JP2012070515A JP2012070515A JP2012216806A JP 2012216806 A JP2012216806 A JP 2012216806A JP 2012070515 A JP2012070515 A JP 2012070515A JP 2012070515 A JP2012070515 A JP 2012070515A JP 2012216806 A JP2012216806 A JP 2012216806A
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- oxide semiconductor
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- 239000004986 Cholesteric liquid crystals (ChLC) Substances 0.000 description 1
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/4908—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET for thin film semiconductor, e.g. gate of TFT
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66969—Multistep manufacturing processes of devices having semiconductor bodies not comprising group 14 or group 13/15 materials
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
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Abstract
【解決手段】酸化物半導体層を含むトランジスタの作製工程において、ゲート電極を形成後、インライン装置にて、酸化アルミニウム膜と酸化シリコン膜と酸化物半導体膜を大気暴露することなく連続的に形成し、さらに同インライン装置にて加熱および酸素添加処理を行い、他の酸化アルミニウム膜でトランジスタを覆った後、熱処理を行うことで、水素原子を含む不純物が除去され、且つ、化学量論比を超える酸素を含む領域を有する酸化物半導体膜を形成する。該酸化物半導体膜を用いたトランジスタは、バイアス−熱ストレス試験(BT)試験前後においてもトランジスタのしきい値電圧の変化量が低減されており、信頼性の高いトランジスタとすることができる。
【選択図】図4
Description
本実施の形態では、半導体装置および半導体装置の作製方法の一形態を、図1乃至図3を用いて説明する。本実施の形態では、半導体装置の一例として酸化物半導体層を有するトランジスタを示す。
本実施の形態では、実施の形態1に示した半導体装置の酸化物半導体層等を形成する成膜装置の一例について、図4乃至図6を用いて説明する。なお、実施の形態1と同一部分または同様な機能を有する部分、および工程は、実施の形態1と同様に行うことができ、繰り返しの説明は省略する。また、同じ箇所の詳細な説明は省略する。
実施の形態1で例示したトランジスタを用いて表示機能を有する半導体装置(表示装置ともいう)を作製することができる。また、トランジスタを含む駆動回路の一部または全体を、画素部と同じ基板上に一体形成し、システムオンパネルを形成することができる。
実施の形態1で例示したトランジスタを用いて、対象物の情報を読み取るイメージセンサ機能を有する半導体装置を作製することができる。
実施の形態1で例示したトランジスタは、複数のトランジスタを積層する集積回路を有する半導体装置に好適に用いることができる。本実施の形態では、半導体装置の一例として、記憶媒体(メモリ素子)の例を示す。
本明細書に開示する半導体装置は、さまざまな電子機器(遊技機も含む)に適用することができる。電子機器としては、例えば、テレビジョン装置(テレビ、またはテレビジョン受信機ともいう)、コンピュータ用などのモニタ、デジタルカメラ、デジタルビデオカメラ等のカメラ、デジタルフォトフレーム、携帯電話機(携帯電話、携帯電話装置ともいう)、携帯型ゲーム機、携帯情報端末、音響再生装置、パチンコ機などの大型ゲーム機などが挙げられる。上記実施の形態で説明した半導体装置を具備する電子機器の例について説明する。
101 ロード室
102 アンロード室
106 素子分離絶縁膜
108 ゲート絶縁膜
110 ゲート電極層
111 成膜室
112 成膜室
113 成膜室
114 加熱室
115 加酸素化処理室
116 チャネル形成領域
120 不純物領域
124 金属化合物領域
128 絶縁膜
130 絶縁膜
140 トランジスタ
141 基板支持部
142a ソース電極層またはドレイン電極層
142b ソース電極層またはドレイン電極層
143 移動手段
148b 電極層
150 絶縁膜
151 ターゲット
152 絶縁膜
153 防着板
154 成膜室
155 基板加熱手段
157 圧力調整手段
159 ガス導入手段
161 ゲートバルブ
162 トランジスタ
164 容量素子
170 加熱室
171 ヒータ
173 保護板
185 基板
201 ロード室
202 アンロード室
211 成膜室
212 成膜室
213 加熱室
250 基板温度
301 ロード室
302 アンロード室
311 成膜室
312 成膜室
313 成膜室
314 加熱室
400 基板
401 ゲート電極層
401a ゲート電極層
402a 酸化アルミニウム膜
402b 酸化シリコン膜
403 酸化物半導体層
405a ソース電極層
405b ドレイン電極層
407a 酸化シリコン膜
407b 酸化アルミニウム膜
410 トランジスタ
420 トランジスタ
421 酸素
601 基板
602 フォトダイオード
606a 半導体膜
606b 半導体膜
606c 半導体膜
608 接着層
613 基板
631 絶縁膜
632 絶縁膜
633 層間絶縁膜
634 層間絶縁膜
640 トランジスタ
641a 電極層
641b 電極層
642 電極層
643 導電層
645 ゲート電極層
656 トランジスタ
658 フォトダイオードリセット信号線
659 ゲート信号線
671 フォトセンサ出力信号線
672 フォトセンサ基準信号線
2700 電子書籍
2701 筐体
2703 筐体
2705 表示部
2707 表示部
2711 軸部
2721 電源
2723 操作キー
2725 スピーカー
2800 筐体
2801 筐体
2802 表示パネル
2803 スピーカー
2804 マイクロフォン
2805 操作キー
2806 ポインティングデバイス
2807 カメラ用レンズ
2808 外部接続端子
2810 太陽電池セル
2811 外部メモリスロット
3001 本体
3002 筐体
3003 表示部
3004 キーボード
3021 本体
3022 スタイラス
3023 表示部
3024 操作ボタン
3025 外部インターフェイス
3051 本体
3053 接眼部
3054 操作スイッチ
3055 表示部(B)
3056 バッテリー
3057 表示部(A)
4001 基板
4002 画素部
4003 信号線駆動回路
4004 走査線駆動回路
4005 シール材
4006 基板
4008 液晶層
4010 トランジスタ
4011 トランジスタ
4013 液晶素子
4015 接続端子電極層
4016 端子電極層
4018 FPC
4018a FPC
4018b FPC
4019 異方性導電膜
4020 絶縁膜
4021 絶縁膜
4023 絶縁膜
4024 絶縁膜
4030 電極層
4031 電極層
4032 絶縁層
4033 絶縁層
4510 隔壁
4511 電界発光層
4513 発光素子
4514 充填材
4612 キャビティ
4613 球形粒子
4614 充填材
4615a 黒色領域
4615b 白色領域
9600 テレビジョン装置
9601 筐体
9603 表示部
9605 スタンド
Claims (4)
- ゲート電極を形成する工程と、
第1の酸化アルミニウム膜(AlOx1(x1>3/2))および前記第1の酸化アルミニウム膜上の酸化シリコン膜(SiOy(y>2))よりなるゲート絶縁膜を形成する工程と、
酸化物半導体膜を形成する工程と、
ソース電極層およびドレイン電極層を形成する工程と、
第2の酸化アルミニウム膜(AlOx2(x2>3/2))を前記酸化物半導体膜上に形成する工程を有し、
前記ゲート絶縁膜と前記酸化物半導体膜は、第1のインライン装置にて大気暴露させることなく連続的に形成後、前記第1のインライン装置にて第1の熱処理および加酸素化処理が行われ、
前記第2の酸化アルミニウム膜は第2のインライン装置にて大気暴露されることなく連続的に形成後、第2のインライン装置にて第2の熱処理が行われることを特徴とする半導体装置の作製方法。 - ゲート電極を形成する工程と、
第1の酸化アルミニウム膜(AlOx1(x1>3/2))と前記第1の酸化アルミニウム膜上の第1の酸化シリコン膜(SiOy1(y1>2))よりなるゲート絶縁膜を形成する工程と、
酸化物半導体膜を形成する工程と、
ソース電極層とドレイン電極層を形成する工程と、
第2の酸化シリコン膜(SiOy2(y2>2))と第2の酸化シリコン膜上の第2の酸化アルミニウム膜(AlOx2(x2>3/2))よりなる保護層を前記酸化物半導体膜上に形成する工程を有し、
前記ゲート絶縁膜と前記酸化物半導体膜は、第1のインライン装置にて大気暴露させることなく連続的に形成後、前記第1のインライン装置にて第1の熱処理および加酸素化処理が行われ、
前記保護層は第2のインライン装置にて大気暴露されることなく連続的に形成後、第2のインライン装置にて第2の熱処理が行われることを特徴とする半導体装置の作製方法。 - ゲート電極を形成する工程と、
第1の酸化アルミニウム膜(AlOx1(x1>3/2))と前記第1の酸化アルミニウム膜上の第1の酸化シリコン膜(SiOy1(y1>2))よりなるゲート絶縁膜を形成する工程と、
酸化物半導体膜を形成する工程と、
ソース電極層とドレイン電極層を形成する工程と、
第2の酸化シリコン膜(SiOy2(y2>2))と第2の酸化シリコン膜上の有機物と金属酸化物の混合膜または透明導電酸化膜または窒素を含む前記酸化物半導体膜である薄膜Xと、薄膜X上の第2の酸化アルミニウム膜(AlOx2(x2>3/2))よりなる保護層を前記酸化物半導体膜上に形成する工程を有し、
前記ゲート絶縁膜と前記酸化物半導体膜は、第1のインライン装置にて大気暴露させることなく連続的に形成後、前記第1のインライン装置にて第1の熱処理および加酸素化処理が行われ、
前記保護層は第2のインライン装置にて大気暴露されることなく連続的に形成後、第2のインライン装置にて第2の熱処理が行われることを特徴とする半導体装置の作製方法。 - 請求項1乃至請求項3に記載の第2の熱処理は、275℃以上325℃以下にて行われることを特徴とする半導体装置の作製方法。
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