JP2010080952A - 半導体装置及び半導体装置の作製方法 - Google Patents
半導体装置及び半導体装置の作製方法 Download PDFInfo
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- JP2010080952A JP2010080952A JP2009197350A JP2009197350A JP2010080952A JP 2010080952 A JP2010080952 A JP 2010080952A JP 2009197350 A JP2009197350 A JP 2009197350A JP 2009197350 A JP2009197350 A JP 2009197350A JP 2010080952 A JP2010080952 A JP 2010080952A
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Classifications
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- G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
- G09G2300/0809—Several active elements per pixel in active matrix panels
- G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
- G09G2300/0857—Static memory circuit, e.g. flip-flop
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/08—Details of timing specific for flat panels, other than clock recovery
Abstract
【解決手段】酸化物半導体膜とソース電極及びドレイン電極の間に1nm以上10nm以下のサイズの結晶粒を有し、チャネル形成領域となる酸化物半導体膜よりキャリア濃度が高い酸素欠乏酸化物半導体層を設ける。
【選択図】図4
Description
本実施の形態では、薄膜トランジスタ及びその作製工程について、図5乃至図8を用いて説明する。
本実施の形態は、マルチゲート構造の薄膜トランジスタの例である。従って、他は実施の形態1と同様に行うことができ、実施の形態1と同一部分又は同様な機能を有する部分、及び工程の繰り返しの説明は省略する。
本実施の形態は、薄膜トランジスタにおいてソース領域及びドレイン領域を多層とする例である。従って、他は実施の形態1又は実施の形態2と同様に行うことができ、実施の形態1又は実施の形態2と同一部分又は同様な機能を有する部分、及び工程の繰り返しの説明は省略する。
本実施の形態は、実施の形態1において、薄膜トランジスタの形状及び作製方法が一部異なる例である。従って、他は実施の形態1と同様に行うことができ、実施の形態1と同一部分又は同様な機能を有する部分、及び工程の繰り返しの説明は省略する。
本実施の形態では、半導体装置の一例である表示装置において、同一基板上に少なくとも駆動回路の一部と、画素部に配置する薄膜トランジスタを作製する例について以下に説明する。
線S1〜Sm(図示せず。)により信号線駆動回路5303と接続され、走査線駆動回路
5302から行方向に伸張して配置された複数の走査線G1〜Gn(図示せず。)により
走査線駆動回路5302と接続され、信号線S1〜Sm並びに走査線G1〜Gnに対応し
てマトリクス状に配置された複数の画素(図示せず。)を有する。そして、各画素は、信
号線Sj(信号線S1〜Smのうちいずれか一)、走査線Gi(走査線G1〜Gnのうち
いずれか一)と接続される。
ここでは、少なくともゲート絶縁層と酸素過剰酸化物半導体層の積層を大気に触れることなく、連続成膜を行う逆スタガ型の薄膜トランジスタの作製例を以下に示す。ここでは、連続成膜を行う工程までの工程を示し、その後の工程は、実施の形態1乃至実施の形態4のいずれか一に従って薄膜トランジスタを作製すればよい。
薄膜トランジスタを作製し、該薄膜トランジスタを画素部、さらには駆動回路に用いて表示機能を有する半導体装置(表示装置ともいう)を作製することができる。また、薄膜トランジスタを駆動回路の一部または全体を、画素部と同じ基板上に一体形成し、システムオンパネルを形成することができる。
本実施の形態では、半導体装置として発光表示装置の例を示す。表示装置の有する表示素子としては、ここではエレクトロルミネッセンスを利用する発光素子を用いて示す。エレクトロルミネッセンスを利用する発光素子は、発光材料が有機化合物であるか、無機化合物であるかによって区別され、一般的に、前者は有機EL素子、後者は無機EL素子と呼ばれている。
次に、半導体装置の一形態である表示パネルの構成について、以下に示す。本実施の形態では、表示素子として液晶素子を有する液晶表示装置の一形態である液晶表示パネル(液晶パネルともいう)、表示素子として発光素子を有する半導体装置の一形態である発光表示パネル(発光パネルともいう)について説明する。
本発明の一形態の半導体装置は、電子ペーパーとして適用することができる。電子ペーパーは、情報を表示するものであればあらゆる分野の電子機器に用いることが可能である。例えば、電子ペーパーを用いて、電子書籍(電子ブック)、ポスター、電車などの乗り物の車内広告、クレジットカード等の各種カードにおける表示等に適用することができる。電子機器の一例を図31、図32に示す。
本発明の一形態に係る半導体装置は、さまざまな電子機器(遊技機も含む)に適用することができる。電子機器としては、例えば、テレビジョン装置(テレビ、またはテレビジョン受信機ともいう)、コンピュータ用などのモニタ、デジタルカメラ、デジタルビデオカメラ、デジタルフォトフレーム、携帯電話機(携帯電話、携帯電話装置ともいう)、携帯型ゲーム機、携帯情報端末、音響再生装置、パチンコ機などの大型ゲーム機などが挙げられる。
本実施の形態は、薄膜トランジスタにおいてチャネル保護型の薄膜トランジスタの例である。従って、他は実施の形態1又は実施の形態2と同様に行うことができ、実施の形態1又は実施の形態2と同一部分又は同様な機能を有する部分、及び工程の繰り返しの説明は省略する。
本実施の形態は、本発明の一形態である薄膜トランジスタにおいてトップゲート型の薄膜トランジスタの例である。従って、他は実施の形態1又は実施の形態2と同様に行うことができ、実施の形態1又は実施の形態2と同一部分又は同様な機能を有する部分、及び工程の繰り返しの説明は省略する。
81 搬送ロボット
82 カセット室
83 ゲートバルブ
84 ゲートバルブ
85 ゲートバルブ
86 ゲートバルブ
87 ゲートバルブ
88 ゲートバルブ
89 処理室
90 処理室
91 処理室
92 処理室
93 処理室
94 基板
100 基板
101 ゲート電極層
102 ゲート絶縁層
103 半導体層
104a ソース領域又はドレイン領域
104b ソース領域又はドレイン領域
105a ソース電極層又はドレイン電極層
105b ソース電極層又はドレイン電極層
105a1 ソース電極層又はドレイン電極層
105a2 ソース電極層又はドレイン電極層
105b1 ソース電極層又はドレイン電極層
105b2 ソース電極層又はドレイン電極層
106a ソース領域又はドレイン領域
106b ソース領域又はドレイン領域
108 チャネル保護層
109a 絶縁膜
109b 絶縁膜
111 半導体膜
112 半導体層
113 マスク
114 半導体膜
115 半導体膜
116 マスク
117 導電膜
118 マスク
121 導電膜
122 マスク
131 半導体膜
132 半導体膜
133 導電膜
135 マスク
136 半導体膜
137 半導体膜
138 導電膜
139 マスク
150 基板
151a ゲート電極層
151b ゲート電極層
152 ゲート絶縁層
153 半導体層
153a 半導体層
153b 半導体層
154a ソース領域又はドレイン領域
154b ソース領域又はドレイン領域
154c ソース領域又はドレイン領域
155a ソース電極層又はドレイン電極層
155b ソース電極層又はドレイン電極層
156 配線層
170a 薄膜トランジスタ
170b 薄膜トランジスタ
170c 薄膜トランジスタ
170d 薄膜トランジスタ
171a 薄膜トランジスタ
171b 薄膜トランジスタ
171c 薄膜トランジスタ
173 薄膜トランジスタ
174 薄膜トランジスタ
175 薄膜トランジスタ
200 基板
201 薄膜トランジスタ
202 ソース配線層
203 ゲート配線層
204 容量配線層
211 絶縁層
212 絶縁層
213 絶縁層
255 電極層
260 液晶表示素子
261 絶縁層
262 液晶層
263 絶縁層
264 着色層
265 電極層
266 基板
267 偏光板
268 偏光板
301 薄膜トランジスタ
302 薄膜トランジスタ
303 発光素子
304 容量素子
305 ソース配線層
306 ゲート配線層
307 電源線
311 絶縁層
312 絶縁層
313 絶縁層
320 電極層
321 隔壁
322 電界発光層
323 電極層
581 薄膜トランジスタ
585 絶縁層
587 電極層
588 電極層
589 球形粒子
590a 黒色領域
590b 白色領域
594 キャビティ
595 充填材
1000 携帯電話機
1001 筐体
1002 表示部
1003 操作ボタン
1004 外部接続ポート
1005 スピーカ
1006 マイク
2600 TFT基板
2601 対向基板
2602 シール材
2603 画素部
2604 表示素子
2605 着色層
2606 偏光板
2607 偏光板
2608 配線回路部
2609 フレキシブル配線基板
2610 冷陰極管
2611 反射板
2612 回路基板
2613 拡散板
2631 ポスター
2632 車内広告
2700 電子書籍
2701 筐体
2703 筐体
2705 表示部
2707 表示部
2711 軸部
2721 電源
2723 操作キー
2725 スピーカ
4001 基板
4002 画素部
4003 信号線駆動回路
4004 走査線駆動回路
4005 シール材
4006 基板
4008 液晶層
4010 薄膜トランジスタ
4011 薄膜トランジスタ
4013 液晶素子
4015 接続端子
4016 配線
4018 FPC
4019 異方性導電膜
4030 画素電極層
4031 対向電極層
4032 絶縁層
4501 基板
4502 画素部
4503a 信号線駆動回路
4503b 信号線駆動回路
4504a 走査線駆動回路
4504b 走査線駆動回路
4505 シール材
4506 基板
4507 充填材
4509 薄膜トランジスタ
4510 薄膜トランジスタ
4511 発光素子
4512 電極層
4515 接続端子
4516 配線
4517 電極層
4518a FPC
4518b FPC
4519 異方性導電膜
5300 基板
5301 画素部
5302 走査線駆動回路
5303 信号線駆動回路
5400 基板
5401 画素部
5402 走査線駆動回路
5403 信号線駆動回路
5404 走査線駆動回路
5501 配線
5502 配線
5503 配線
5504 配線
5505 配線
5506 配線
5543 ノード
5544 ノード
5571 薄膜トランジスタ
5572 薄膜トランジスタ
5573 薄膜トランジスタ
5574 薄膜トランジスタ
5575 薄膜トランジスタ
5576 薄膜トランジスタ
5577 薄膜トランジスタ
5578 薄膜トランジスタ
5601 ドライバIC
5602 スイッチ群
5603a 薄膜トランジスタ
5603b 薄膜トランジスタ
5603c 薄膜トランジスタ
5703a タイミング
5703b タイミング
5703c タイミング
5803a タイミング
5803b タイミング
5611 配線
5612 配線
5613 配線
5621 配線
5711 配線
5712 配線
5713 配線
5714 配線
5715 配線
5716 配線
5717 配線
5721 信号
5821 信号
7001 TFT
7002 発光素子
7003 陰極
7004 発光層
7005 陽極
7011 駆動用TFT
7012 発光素子
7013 陰極
7014 発光層
7015 陽極
7016 遮蔽膜
7017 導電膜
7021 駆動用TFT
7022 発光素子
7023 陰極
7024 発光層
7025 陽極
7027 導電膜
9600 テレビジョン装置
9601 筐体
9603 表示部
9605 スタンド
9607 表示部
9609 操作キー
9610 リモコン操作機
9700 デジタルフォトフレーム
9701 筐体
9703 表示部
9881 筐体
9882 表示部
9883 表示部
9884 スピーカ部
9885 入力手段(操作キー)
9886 記録媒体挿入部
9887 接続端子
9888 センサ
9889 マイクロフォン
9890 LEDランプ
9891 筐体
9893 連結部
9900 スロットマシン
9901 筐体
9903 表示部
Claims (8)
- 絶縁表面上に、ゲート電極と、該ゲート電極上にゲート絶縁層と、該ゲート絶縁層上に半導体層と、該半導体層上にソース領域及びドレイン領域と、前記ソース領域及び前記ドレイン領域上に金属層とを有し、
前記半導体層は、インジウム、ガリウム、及び亜鉛を含む酸化物半導体層であり、
前記ソース領域及び前記ドレイン領域は、前記半導体層の酸素濃度よりも酸素濃度が低く、且つサイズが1nm以上10nm以下の結晶粒を含み、
前記金属層は、ソース電極層及びドレイン電極層であることを特徴とする半導体装置。 - 請求項1において、前記ソース領域及び前記ドレイン領域は、インジウム、ガリウム、及び亜鉛を含む酸化物層である半導体装置。
- 絶縁表面上に、ゲート電極と、該ゲート電極上にゲート絶縁層と、該ゲート絶縁層上に半導体層と、該半導体層上に第1のソース領域及び第1のドレイン領域と、前記第1のソース領域及び前記第1のドレイン領域上に第2のソース領域及び第2のドレイン領域と、前記第2のソース領域及び前記第2のドレイン領域上に金属層とを有し、
前記半導体層は、インジウム、ガリウム、及び亜鉛を含む酸化物半導体層であり、
前記第1のソース領域及び前記第1のドレイン領域は、前記半導体層の酸素濃度よりも酸素濃度が低く、且つサイズが1nm以上10nm以下の結晶粒を含み、
前記第2のソース領域及び前記第2のドレイン領域は、W、Mo、Ti、NiまたはAlを含み、且つ前記半導体層の酸素濃度よりも酸素濃度が低く、
前記金属層は、ソース電極層及びドレイン電極層であることを特徴とする半導体装置。 - 請求項3において、前記第1のソース領域及び前記第1のドレイン領域は、インジウム、ガリウム、及び亜鉛を含む酸化物層である半導体装置。
- 請求項3または請求項4において、前記第2のソース領域及び前記第2のドレイン領域は、インジウム、ガリウム、及び亜鉛を含む酸化物層である半導体装置。
- 絶縁表面上にゲート電極を形成し、
前記ゲート電極上にゲート絶縁層と、該ゲート絶縁層上に半導体層とをスパッタ法により大気に触れることなく積層し、
前記半導体層上にソース領域及びドレイン領域を形成し、
前記ソース領域及び前記ドレイン領域上に金属層を形成し、
前記半導体層は、インジウム、ガリウム、及び亜鉛を含む酸化物半導体層であり、
前記ソース領域及び前記ドレイン領域は、前記半導体層の酸素濃度よりも酸素濃度が低く、且つサイズが1nm以上10nm以下の結晶粒を含み、
前記金属層は、ソース電極層及びドレイン電極層であることを特徴とする半導体装置の作製方法。 - 請求項6において、前記ソース領域及び前記ドレイン領域は、インジウム、ガリウム、及び亜鉛を含む酸化物層であり、スパッタ法により大気に触れることなく前記半導体層と積層する半導体装置の作製方法。
- 請求項6または請求項7において、前記半導体層を形成する前に、前記ゲート絶縁層表面に酸素ラジカル処理を行う半導体装置の作製方法。
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