JP4375619B2 - 半導体装置の製造方法 - Google Patents
半導体装置の製造方法 Download PDFInfo
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- JP4375619B2 JP4375619B2 JP2005046573A JP2005046573A JP4375619B2 JP 4375619 B2 JP4375619 B2 JP 4375619B2 JP 2005046573 A JP2005046573 A JP 2005046573A JP 2005046573 A JP2005046573 A JP 2005046573A JP 4375619 B2 JP4375619 B2 JP 4375619B2
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- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 19
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- 229910018072 Al 2 O 3 Inorganic materials 0.000 description 1
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 1
- KZBUYRJDOAKODT-UHFFFAOYSA-N Chlorine Chemical compound ClCl KZBUYRJDOAKODT-UHFFFAOYSA-N 0.000 description 1
- ZAMOUSCENKQFHK-UHFFFAOYSA-N Chlorine atom Chemical compound [Cl] ZAMOUSCENKQFHK-UHFFFAOYSA-N 0.000 description 1
- KRHYYFGTRYWZRS-UHFFFAOYSA-M Fluoride anion Chemical compound [F-] KRHYYFGTRYWZRS-UHFFFAOYSA-M 0.000 description 1
- CPELXLSAUQHCOX-UHFFFAOYSA-N Hydrogen bromide Chemical compound Br CPELXLSAUQHCOX-UHFFFAOYSA-N 0.000 description 1
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Description
本発明の第1の実施の形態に係る半導体装置の製造方法について、図2乃至図17を用いて説明する。図2は、本発明の第1の実施の形態に係る半導体装置の製造方法により形成される半導体装置の断面図である。図3乃至図17は、第1の実施の形態に係る半導体装置の製造工程を示す図である。
本発明の第2の実施の形態に係る半導体装置の製造方法について、図18乃至図22を用いて説明する。図18乃至図22は、第2の実施の形態に係る半導体装置の製造工程を示す図である。図中、先に説明した部分に対応する部分には同一の参照符号を付し、説明を省略する。
本発明の第3の実施の形態に係る半導体装置の製造方法について、図23乃至図29を用いて説明する。図23乃至図29は、第3の実施の形態に係る半導体装置の製造工程を示す図である。図中、先に説明した部分に対応する部分には同一の参照符号を付し、説明を省略する。
本発明の第1の実施の形態に係る半導体装置の製造方法によりp−MOSトランジスタ13aとn−MOSトランジスタ13bを有する半導体装置(以下「実施例」という)を製造した。
以上本発明の好ましい実施の形態について詳述したが、本発明は係る特定の実施の形態に限定されるものではなく、特許請求の範囲に記載された本発明の範囲内において、種々の変形・変更が可能である。
(付記1)
半導体基板の第1の領域に形成されたp型トランジスタと、該半導体基板の第2の領域に形成されたn型トランジスタからなる半導体装置の製造方法であって、
前記半導体基板上にゲート絶縁膜およびゲート電極からなるゲート積層体を形成する工程と、
前記第1の領域において、前記ゲート積層体の両側面に第1の側壁絶縁膜および第2の側壁絶縁膜を形成する工程と、
前記第2の領域の半導体基板表面を耐エッチング膜により覆った状態で、前記第1の領域において第1の側壁絶縁膜および第2の側壁絶縁膜をマスクとして、該第2の側壁絶縁膜の外側の半導体基板に溝部を形成する工程と、
前記溝部に圧縮応力印加部を形成する工程と、
前記第1の領域において第1の側壁絶縁膜および第2の側壁絶縁膜を除去すると共に、前記第2の領域において耐エッチング膜を除去する工程と、
前記ゲート積層体をマスクとして、前記第1の領域および前記第2の領域に第1の接合領域を形成する工程と、
前記ゲート積層体の両側面に第3の側壁絶縁膜を形成し、前記ゲート積層体および第3の側壁絶縁膜をマスクとして、前記第1の領域および前記第2の領域に第2の接合領域を形成する工程と、
を備えることを特徴とする半導体装置の製造方法。
(付記2)
前記第1の側壁絶縁膜および第2の側壁絶縁膜を形成する工程は、
前記半導体基板の表面およびゲート積層体を覆う第1の絶縁膜および第2の絶縁膜を順次形成する工程と、
前記第1の領域において第1の絶縁膜および第2の絶縁膜を異方性エッチングする工程からなり、
前記溝部を形成する工程は、前記第2の領域の耐エッチング膜が第2の絶縁膜であることを特徴とする付記1記載の半導体装置の製造方法。
(付記3)
前記溝部を形成する工程は、前記第2の領域を覆うレジスト膜であることを特徴とする付記1記載の半導体装置の製造方法。
(付記4)
半導体基板の第1の領域に形成されたp型トランジスタと、該半導体基板の第2の領域に形成されたn型トランジスタからなる半導体装置の製造方法であって、
半導体基板上にゲート絶縁膜およびゲート電極からなるゲート積層体を形成する工程と、
前記ゲート積層体の両側面に第1の側壁絶縁膜および第2の側壁絶縁膜を形成すると共に、該第2の側壁絶縁膜の外側の半導体基板表面を露出する工程と、
前記第2の領域を覆うレジスト膜を形成する工程と、
CF4ガスおよびO2ガスを電離すると共に照射して前記第1の領域の半導体基板表面を改質する第1の表面処理工程と、
O2ガスを電離すると共に照射して第2の領域においてレジスト膜を除去すると共に、第2の側壁絶縁膜の外側に露出する半導体基板表面に酸化膜を形成する第2の表面処理工程と、
前記第1の領域の半導体基板表面を露出する工程と、
前記第1の領域の第1の側壁絶縁膜、第2の側壁絶縁膜、および第2の領域の酸化膜をマスクとして、第2の側壁絶縁膜の外側の半導体基板に溝部を形成する工程と、
前記溝部に圧縮応力印加部を形成する工程と、
前記第1の領域において第1の側壁絶縁膜および第2の側壁絶縁膜を除去すると共に、前記第2の領域において耐エッチング膜を除去する工程と、
前記ゲート積層体をマスクとして、前記第1の領域および前記第2の領域に第1の接合領域を形成する工程と、
前記ゲート積層体の両側面に第3の側壁絶縁膜を形成し、前記ゲート積層体および第3の側壁絶縁膜をマスクとして、前記第1の領域および前記第2の領域に第2の接合領域を形成する工程と、
を備えることを特徴とする半導体装置の製造方法。
(付記5)
第1の領域および第2の領域に第1の接合領域を形成する工程の後、第2の接合領域を形成する工程する前に、
前記ゲート積層体の両側面に前記第3の側壁絶縁膜より薄い第4の側壁絶縁膜を形成し、前記ゲート積層体および第4の側壁絶縁膜をマスクとして、前記第1の領域および前記第2の領域に前記第1の接合領域より深く前記第2の接合領域より浅い第3の接合領域を形成する工程を更に有し、
第1の領域および第2の領域に第2の接合領域を形成する工程は、
前記ゲート積層体および前記第4の側壁絶縁膜の両側面に前記第3の側壁絶縁膜を形成し、前記ゲート積層体、前記第4の側壁絶縁膜および前記第3の側壁絶縁膜をマスクとして、前記第1の領域および前記第2の領域に前記第2の接合領域を形成する
を備えることを特徴とする半導体装置の製造方法。
(付記6)
前記溝部を形成する工程は、
第2の側壁絶縁膜の外側の半導体基板を異方性エッチングを行う処理と、
等方性エッチングを行う処理からなる
ことを特徴とする付記1乃至5のいずれか1項に記載の半導体装置の製造方法。
(付記7)
前記等方性エッチングは、塩化水素ガスあるいは塩素ガスを用いたケミカルドライエッチングであることを特徴とする付記6記載の半導体装置の製造方法。
(付記8)
前記溝部は、その端部とゲート積層体の端部との距離を5nm〜80nmの範囲に設定することを特徴とする付記6記載の半導体装置の製造方法。
(付記9)
前記圧縮応力印加部を形成する工程は、前記溝部に半導体基板を構成する半導体の格子定数よりも大きな半導体材料をエピタキシャル成長させることを特徴とする付記1乃至8のいずれか1項に記載の半導体装置の製造方法。
(付記10)
前記ゲート積層体を形成する工程の後に、該ゲート積層体上にキャップ層を形成する工程をさらに備え、
前記溝部を形成する工程は、キャップ層をゲート積層体のマスクとすることを特徴とする付記1乃至9のいずれか1項に記載の半導体装置の製造方法。
(付記11)
前記圧縮応力印加部を形成する工程は、前記キャップ層をゲート積層体のマスクとすることを特徴とする付記10記載の半導体装置の製造方法。
(付記12)
前記半導体基板がシリコン基板であり、前記圧縮応力印加部がSiGe膜あるいはSiGeC膜からなることを特徴とする付記1乃至11のいずれか1項に記載の半導体装置の製造方法。
11…シリコン基板
11−1、11−2…溝部
12…素子分離領域
13a…p−MOSトランジスタ
13b…n−MOSトランジスタ
15、15−1…ゲート絶縁膜
16…ゲート電極
16−1…ゲート電極膜
18…ゲート積層体
19…第3側壁絶縁膜
20…圧縮応力印加部
21…圧縮歪み誘起部
22a,22b…浅い接合領域
23a,23b…ポケット領域
24a,24b…深い接合領域
26…シリサイド膜
28a,28b…ソース/ドレイン領域
30a…p−MOS領域
30b…n−MOS領域
31−1…トレンチ
32a…n型ウェル領域
32b…p型ウェル領域
33…キャップ層
33−1,35−1…シリコン窒化膜
34…第1側壁絶縁膜
34−1…シリコン酸化膜
35…第2側壁絶縁膜
36,38,39,41,51,51−1…レジスト膜
52,52−1…アッシング改質膜
53…シリコン酸化膜
60…第4側壁絶縁膜
61、63、65、66…レジスト膜
62a、62b…少し深い浅い接合領域
64…第5側壁絶縁膜
66a、66b…深い接合領域
Claims (9)
- 半導体基板の第1の領域に形成されたp型トランジスタと、前記半導体基板の第2の領域に形成されたn型トランジスタからなる半導体装置の製造方法であって、
前記半導体基板上の前記第1の領域にゲート絶縁膜およびゲート電極からなる第1のゲート積層体を形成し、前記半導体基板上の前記第2の領域にゲート絶縁膜およびゲート電極からなる第2のゲート積層体を形成する工程と、
前記第1のゲート積層体の両側面に第1の側壁絶縁膜を形成する工程と、
前記第2の領域の半導体基板表面を耐エッチング膜により覆った状態で、前記第1の領域において前記第1の側壁絶縁膜をマスクとして、前記第1の側壁絶縁膜の外側の半導体基板に溝部を形成する工程と、
前記溝部に圧縮応力印加部を形成する工程と、
前記第1の領域における前記第1の側壁絶縁膜を除去する工程と、
前記第1のゲート積層体及び前記第2のゲート積層体をマスクとして、前記第1の領域および前記第2の領域に第1の接合領域を形成する工程と、
前記第1のゲート積層体の両側面に第2の側壁絶縁膜を形成し、前記第2のゲート積層体の両側面に第3の側壁絶縁膜を形成する工程と、
前記第1のゲート積層体および前記第2の側壁絶縁膜ならびに前記第2のゲート積層体及び前記第3の側壁絶縁膜をマスクとして、前記第1の領域および前記第2の領域に第2の接合領域を形成する工程とをこの順番で行い、
前記第1の側壁絶縁膜を形成する工程では、
前記半導体基板の表面ならびに前記第1のゲート積層体および前記第2のゲート積層体を覆う第1の絶縁膜および第2の絶縁膜を順次形成する工程と、
前記第1の領域において前記第1の絶縁膜および前記第2の絶縁膜を異方性エッチングする工程とをこの順番で行い、
前記溝部を形成する工程では、
前記第2の領域の前記耐エッチング膜が前記第2の領域を覆う前記第2の絶縁膜である
ことを特徴とする半導体装置の製造方法。 - 半導体基板の第1の領域に形成されたp型トランジスタと、前記半導体基板の第2の領域に形成されたn型トランジスタからなる半導体装置の製造方法であって、
前記半導体基板上の前記第1の領域にゲート絶縁膜およびゲート電極からなる第1のゲート積層体を形成し、前記半導体基板上の前記第2の領域にゲート絶縁膜およびゲート電極からなる第2のゲート積層体を形成する工程と、
前記第1のゲート積層体の両側面に第1の側壁絶縁膜を形成する工程と、
前記第2の領域の半導体基板表面をレジスト膜により覆った状態で、CF4ガスおよびO2ガスを電離すると共に照射して、前記第1の領域の前記第1の側壁絶縁膜の外側の半導体基板表面を改質して第1の改質膜を形成する第1の表面処理工程と、
O2ガスを電離すると共に照射して、前記第2の領域において前記レジスト膜を除去すると共に、前記第1の領域において前記第1の側壁絶縁膜の外側に露出する半導体基板表面の前記第1の改質膜を更に改質して第2の改質膜を形成し、前記第2の領域において露出する前記半導体基板表面を酸化して酸化膜を形成する第2の表面処理工程と、
前記第1の領域の前記第1のゲート構造体および前記第1の側壁絶縁膜ならびに前記第2の領域の前記第2のゲート構造体および前記酸化膜をマスクとして、前記第1の領域の前記第1の側壁絶縁膜の外側の前記半導体基板に溝部を形成する工程と、
前記溝部に圧縮応力印加部を形成する工程と、
前記第1の領域において前記第1の側壁絶縁膜を除去する工程と、
前記第1のゲート積層体及び前記第2のゲート積層体をマスクとして、前記第1の領域および前記第2の領域に第1の接合領域を形成する工程と、
前記第1のゲート積層体の両側面に第2の側壁絶縁膜を形成し、前記第2のゲート積層体の両側面に第3の側壁絶縁膜を形成する工程と、
前記第1のゲート積層体および前記第2の側壁絶縁膜ならびに前記第2のゲート積層体及び前記第3の側壁絶縁膜をマスクとして、前記第1の領域および前記第2の領域に第2の接合領域を形成する工程と
をこの順番で行うことを特徴とする半導体装置の製造方法。 - 前記第1の領域および前記第2の領域に前記第1の接合領域を形成する工程の後、前記第2の側壁絶縁膜および前記第3の側壁絶縁膜を形成する工程の前に、
前記第1のゲート積層体の両側面に前記第2の側壁絶縁膜より薄い第4の側壁絶縁膜を形成し、前記第2のゲート積層体の両側面に前記第3の側壁絶縁膜より薄い第5の側壁絶縁膜を形成する工程と、
前記第1の領域においては、前記第1のゲート積層体および前記第4の側壁絶縁膜をマスクとして、前記第2の領域においては、前記第2のゲート積層体および前記第5の側壁絶縁膜をマスクとして、前記第1の領域および前記第2の領域に、前記第1の接合領域より深く前記第2の接合領域より浅い第3の接合領域を形成する工程とをこの順番で行う
ことを特徴とする請求項1又は2に記載の半導体装置の製造方法。 - 前記溝部を形成する工程は、
前記第1の側壁絶縁膜の外側の前記半導体基板を異方性エッチングする処理と、
前記第1の側壁絶縁膜の外側の前記半導体基板を等方性エッチングする処理からなる
ことを特徴とする請求項1乃至3のいずれか1項に記載の半導体装置の製造方法。 - 前記溝部は、その端部と前記第1のゲート積層体の端部との距離を5nm〜80nmの範囲に設定することを特徴とする請求項3記載の半導体装置の製造方法。
- 前記圧縮応力印加部を形成する工程は、
前記溝部に前記半導体基板を構成する半導体の格子定数よりも大きな半導体材料をエピタキシャル成長させる
ことを特徴とする請求項1乃至5のいずれか1項に記載の半導体装置の製造方法。 - 前記第1のゲート積層体および前記第2のゲート積層体を形成する工程の後に、前記第1のゲート積層体上にキャップ層を形成する工程をさらに行い、
前記溝部を形成する工程は、前記キャップ層を前記第1のゲート積層体のマスクとすることを特徴とする請求項1乃至6のいずれか1項に記載の半導体装置の製造方法。 - 前記圧縮応力印加部を形成する工程は、前記キャップ層を前記第1のゲート積層体のマスクとすることを特徴とする請求項7記載の半導体装置の製造方法。
- 前記半導体基板がシリコン基板であり、前記圧縮応力印加部がSiGe膜あるいはSiGeC膜からなることを特徴とする請求項1乃至8のいずれか1項に記載の半導体装置の製造方法。
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