JP5147471B2 - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
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- JP5147471B2 JP5147471B2 JP2008064435A JP2008064435A JP5147471B2 JP 5147471 B2 JP5147471 B2 JP 5147471B2 JP 2008064435 A JP2008064435 A JP 2008064435A JP 2008064435 A JP2008064435 A JP 2008064435A JP 5147471 B2 JP5147471 B2 JP 5147471B2
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- film
- insulating film
- gate electrode
- semiconductor device
- gate
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- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/665—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using self aligned silicidation, i.e. salicide
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66553—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using inside spacers, permanent or not
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/6656—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using multiple spacer layers, e.g. multiple sidewall spacers
Description
本発明は、半導体装置及びその製造方法に関し、特に金属材料からなるゲート電極を有するMISFET(Metal Insulator Semiconductor Field Effect Transistor)を備えた半導体装置及びその製造方法に関する。
Z.B.Zhang et al., "Integration of Dual Metal Gate CMOS withTaSiN(NMOS) and Ru(PMOS) Gate Electrodes on HfO2 Gate Dielectric", VLSI2005 S.C.Song et al., "Highly Manufacturable 45nm LSTP CMOSFETs Using Novel Dual High-k and Dual Metal Gate CMOS Integration", VLSI2006
本発明の第1の実施形態に係る半導体装置及びその製造方法について図面を参照しながら説明する。
本発明の第2の実施形態に係る半導体装置及びその製造方法について図面を参照しながら説明する。なお、第2の実施形態に係る半導体装置及びその製造方法について、前述の第1の実施形態に係る半導体装置及びその製造方法と相違する点を中心に説明し、共通する点については適宜省略して説明する。
以下に、本発明の第2の実施形態の変形例に係る半導体装置及びその製造方法について図面を参照しながら説明する。なお、第2の実施形態の変形例に係る半導体装置及びその製造方法について、前述の第2の実施形態に係る半導体装置及びその製造方法と相違する点を中心に説明し、共通する点については適宜省略して説明する。
10a 第1の活性領域
10b 第2の活性領域
11 素子分離領域
12a p型ウェル領域
12b n型ウェル領域
13 ゲート絶縁膜形成膜
13a 第1のゲート絶縁膜
13b 第2のゲート絶縁膜
14,14a,14b 第1の金属膜
15 シリコン膜
15a 第1のシリコン膜
15b 第2のシリコン膜
16 保護膜
16a 第1の保護膜
16b 第2の保護膜
17a 第1のオフセットスペーサ
17b 第2のオフセットスペーサ
18a 浅いn型ソースドレイン領域
18b 浅いp型ソースドレイン領域
19a 第1の内側サイドウォール
19b 第2の内側サイドウォール
20a 第1の外側サイドウォール
20b 第2の外側サイドウォール
20A 第1のサイドウォール
20B 第2のサイドウォール
21,21a 表面保護膜
22 レジストマスク
23 トレンチ
24 シリコン混晶層
25a 深いn型ソースドレイン領域
25b 深いp型ソースドレイン領域
26a 第1の金属シリサイド膜
26b 第2の金属シリサイド膜
27 絶縁膜
28 第1の層間絶縁膜
29 レジストマスク
30,30a,30b 第2の金属膜
30A 第1のゲート電極
30B 第2のゲート電極
31 第2の層間絶縁膜
32a 第1のコンタクトホール
32b 第2のコンタクトホール
33a 第1のコンタクトプラグ
33b 第2のコンタクトプラグ
34 金属シリサイド膜
35 ゲート絶縁膜形成膜
35a 第3のゲート絶縁膜
Wnp 素子分離領域のゲート幅方向の幅
Claims (12)
- 第1導電型の第1のMISトランジスタと第2導電型の第2のMISトランジスタとを備えた半導体装置において、
前記第1のMISトランジスタは、
半導体基板における第1の活性領域上に形成された第1のゲート絶縁膜と、
前記第1のゲート絶縁膜上に形成された第2の金属膜からなる第1のゲート電極と、
前記第1のゲート電極の側面上から前記第1の活性領域における前記第1のゲート電極の側方に位置する領域の上面上に跨って形成された絶縁膜とを備え、
前記第2のMISトランジスタは、
前記半導体基板における第2の活性領域上に形成された第2のゲート絶縁膜と、
前記第2のゲート絶縁膜上に形成され第1の金属膜と前記第1の金属膜上に形成された導電膜とからなる第2のゲート電極と、
前記第2のゲート電極の側面上から前記第2の活性領域における前記第2のゲート電極の側方に位置する領域の上面上に跨って形成された前記絶縁膜と、
前記第2の活性領域における前記第2のゲート電極の外側方下に形成された第2導電型のソースドレイン領域とを備え、
前記ソースドレイン領域は、前記第2の活性領域に設けられたトレンチ内に形成され、前記第2の活性領域におけるチャネル領域のゲート長方向に第1の応力を生じさせるシリコン混晶層を含み、
前記第1の金属膜と前記第2の金属膜とは、互いに異なる金属材料からなり、
前記絶縁膜は、前記第1の活性領域におけるチャネル領域のゲート長方向に第2の応力を生じさせる応力絶縁膜であり、
前記第1のゲート電極及び前記第2のゲート電極の各上面上には、前記絶縁膜が形成されていないことを特徴とする半導体装置。 - 請求項1に記載の半導体装置において、
前記第2のMISトランジスタは、p型MISトランジスタであり、
前記シリコン混晶層は、SiGe層からなり、
前記第1の応力は、圧縮応力であることを特徴とする半導体装置。 - 請求項1又は2に記載の半導体装置において、
前記第1の金属膜は、前記第2の金属膜に比べて膜厚が薄いことを特徴とする半導体装置。 - 請求項1〜3のうちいずれか1項に記載の半導体装置において、
前記第1の金属膜と前記第2の金属膜とは、互いに仕事関数が異なっていることを特徴とする半導体装置。 - 請求項1〜4のうちいずれか1項に記載の半導体装置において、
前記絶縁膜の膜厚は、前記第1のゲート電極の膜厚に比べて薄いことを特徴とする半導体装置。 - 請求項1〜5のうちいずれか1項に記載の半導体装置において、
前記導電膜は、前記第2の金属膜からなることを特徴とする半導体装置。 - 請求項1〜5のうちいずれか1項に記載の半導体装置において、
前記導電膜は、シリコン膜からなり、
前記シリコン膜上に形成された金属シリサイド膜をさらに備えていることを特徴とする半導体装置。 - 請求項1〜7のうちいずれか1項に記載の半導体装置において、
前記第1のゲート絶縁膜は、前記第2のゲート絶縁膜と同じ絶縁材料からなることを特徴とする半導体装置。 - 請求項1〜5、7のうちいずれか1項に記載の半導体装置において、
前記第1のゲート絶縁膜は、前記第2のゲート絶縁膜と異なる絶縁材料からなることを特徴とする半導体装置。 - 請求項1〜9のうちいずれか1項に記載の半導体装置において、
前記第1のゲート電極の側面上に形成された断面形状がL字状の第1の内側サイドウォールと、
前記第2のゲート電極の側面上に形成された断面形状がL字状の第2の内側サイドウォールとをさらに備え、
前記絶縁膜は、前記第1の内側サイドウォール及び前記第2の内側サイドウォールの上に接して形成されていることを特徴とする半導体装置。 - 請求項1に記載の半導体装置において、
前記第1のMISトランジスタは、n型MISトランジスタであり、
前記絶縁膜は、シリコン窒化膜からなり、
前記第2の応力は、引っ張り応力であることを特徴とする半導体装置。 - 請求項1〜11のうちいずれか1項に記載の半導体装置において、
前記第1のゲート絶縁膜及び前記第2のゲート絶縁膜は、比誘電率が10以上の金属酸化物からなる高誘電率膜を含むことを特徴とする半導体装置。
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