CN102487006B - 半导体器件及其形成方法 - Google Patents
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Abstract
本发明提供一种半导体器件的形成方法,包括:提供衬底,所述衬底上形成有栅极结构及位于所述栅极结构两侧的侧墙;以所述侧墙为掩膜,在位于所述栅极两侧的衬底内形成第一开口;对所述第一开口通入刻蚀气体,形成第二开口,所述第二开口与第一开口贯通,且所述第二开口位于侧墙下方,且与所述侧墙邻近;在所述第一开口和第二开口内形成外延层。本发明还提供一种半导体器件。本发明通过对第一开口通入刻蚀气体,对第一开口进行刻蚀,形成第二开口,所述第二开口与第一开口贯通,所述第二开口位于侧墙下方,且与所述侧墙邻近,减小后续形成的源区和漏区的间距,即减小了沟道区尺寸,提高了两侧外延层对沟道区的应力,提高所述晶体管的性能。
Description
技术领域
本发明涉及半导体技术领域,尤其涉及一种半导体器件及其形成方法。
背景技术
众所周知,机械应力可以改变硅材料的能隙和载流子迁移率,最近,机械应力在影响MOSFET性能方面扮演了越来越重要的角色。如果可以适当控制应力,提高了载流子(n-沟道晶体管中的电子,p-沟道晶体管中的空穴)迁移率,就提高了驱动电流,因而应力可以极大地提高晶体管的性能。
应力衬垫技术在NMOS晶体管上形成张应力衬垫层(tensile stress liner),在PMOS晶体管上形成压应力衬垫层(compressive stress liner),从而增大了PMOS晶体管和NMOS晶体管的驱动电流,提高了电路的响应速度。据研究,使用双应力衬垫技术的集成电路能够带来24%的速度提升。
具体地,以PMOS晶体管为例,首先在需要形成源区和漏区的区域形成外延层,如硅锗外延层,然后再进行掺杂形成PMOS晶体管的源区和漏区,形成硅锗是为了引入硅和硅锗(SiGe)之间晶格失配形成的压应力,进一步提高压应力,提高晶体管的性能。
公开号为CN1011700060A的中国专利申请中提供了一种在源漏区域采用硅锗(SiGe)的PMOS晶体管的形成方法,其具体包括:在硅衬底上形成栅极结构;在所述栅极结构的表面形成侧墙;以所述侧墙为掩膜,在栅极结构两侧的硅衬底内形成开口;在所述开口进行选择性外延生长形成硅锗外延层;对所述硅锗外延层进行掺杂,以形成源区和漏区。
但是,在所述半导体工艺制造过程中,常需要在一个衬底上同时形成PMOS晶体管和NMOS晶体管。具体地,首先提供衬底,包括有PMOS衬底和NMOS衬底,所述衬底上分别对应形成有栅极结构;在所述栅极结构表面上形成侧墙,位于PMOS栅极结构表面的侧墙是用于后续形成外延层的掩膜,位于NMOS栅极结构表面的侧墙是为了保护NMOS的栅极结构,避免所述NMOS栅极结构暴露在后续外延层的形成环境中。
现有技术在形成外延层时,常通过减小位于栅极结构上的侧墙宽度,使得以所述侧墙为掩模形成的PMOS外延层的间距减小,提高外延层对沟道区的压应力,但同时也会减小位于NMOS晶体管上的侧墙,变薄的侧墙对栅极结构将不能起到较佳的保护作用,甚至造成NMOS的栅极结构暴露在后续的PMOS外延层生长环境中,降低NMOS器件的可靠性。同样地,若形成NMOS的外延层时,也会同样发生上述问题。
发明内容
本发明解决的问题是提供一种半导体器件及其形成方法,提高了两侧外延层对沟道区的应力,提高晶体管性能。
为解决上述问题,本发明提供一种半导体器件的形成方法,包括:
提供衬底,所述衬底上形成有栅极结构及位于所述栅极结构两侧的侧墙;
以所述侧墙为掩膜,在位于所述栅极两侧的衬底内形成第一开口;
对所述第一开口通入刻蚀气体,形成第二开口,所述第二开口与第一开口贯通,且所述第二开口位于侧墙下方,且与所述侧墙邻近;
在所述第一开口和第二开口内形成外延层。
可选的,所述第二开口具有靠近侧墙的侧壁及靠近衬底的侧壁,其中,所述靠近衬底的侧壁与衬底表面所成角度范围为63~90度。
可选的,形成所述第一开口的方法为等离子体刻蚀。
可选的,形成所述第二开口的方法为各向异性刻蚀。
可选的,所述刻蚀气体为氯化氢、或者所述刻蚀气体为氯气和氢气的混合气体。
可选的,所述第二开口的刻蚀参数为:氯气的流量为50~300sccm,氢气的流量为5~50slm,腔室压力为1~760torr,刻蚀温度为550~850℃,所述刻蚀时间为15~150S。
可选的,所述刻蚀气体为溴化氢。
可选的,所述侧墙的宽度范围为15~20nm。
可选的,所述第二开口靠近侧墙一侧的侧壁的长度范围1~20nm。。
可选的,形成所述第二开口后,还包括对第一开口和第二开口进行退火工艺。
可选的,所述退火工艺参数为氢气的流量为20~50slm,退火时间为60~120S,退火温度800~850℃,腔室压强为1~700Torr。
本发明还提供一种半导体器件,包括:衬底,所述衬底上形成有栅极结构及位于所述栅极结构两侧的侧墙;位于所述侧墙两侧衬底内的第一开口,及位于所述侧墙下方,且邻近侧墙的第二开口,所述第一开口和第二开口贯通;填充第一开口和第二开口的外延层。
可选的,所述侧墙的宽度范围为15~20nm。
可选的,所述第二开口靠近侧墙一侧的侧壁的长度范围1~20nm。。
可选的,所述第二开口具有靠近侧墙的侧壁及靠近衬底的侧壁,其中,所述靠近衬底的侧壁与衬底表面所成角度范围为63~90度。
与现有技术相比,本发明具有以下优点:
通过对第一开口通入刻蚀气体,对第一开口进行刻蚀,形成第二开口,所述第二开口与第一开口贯通,所述第二开口位于侧墙下方,且与所述侧墙邻近,减小后续形成的源区和漏区的间距,即减小了沟道区尺寸,提高了两侧外延层对沟道区的应力,提高所述晶体管的性能,若为PMOS晶体管,则增加了外延层对沟道区的压应力;若为NMOS晶体管,则增加了外延层对沟道区的拉应力。
进一步地,仅仅只对第一开口内进行刻蚀形成第二开口,不需要减小侧墙的宽度,即可以减小沟道区的尺寸,不会对其他需要侧墙保护的器件造成影响。
附图说明
图1是本发明一个实施例的半导体器件的形成方法流程示意图;
图2~图5为本发明一个实施例的半导体器件的形成方法的剖面结构示意图。
具体实施方式
现有技术在形成外延层时,通过减小位于栅极结构上的侧墙宽度,使得以所述侧墙为掩模形成的外延层的间距减小,提高外延层对沟道区的应力,但同时也会减小位于其他不需形成外延层晶体管上的侧墙,变薄的侧墙对其他晶体管的栅极结构将不能起到较佳的保护作用,甚至造成所述栅极结构暴露在后续的外延层生长环境中,降低半导体器件的可靠性。
为解决上述问题,本发明提供一种半导体器件的形成方法,包括:提供衬底,所述衬底上形成有栅极结构及位于所述栅极结构两侧的侧墙;以所述侧墙为掩膜,在位于所述栅极两侧的衬底内形成第一开口;对所述第一开口通入刻蚀气体,形成第二开口,所述第二开口与第一开口贯通,且所述第二开口位于侧墙下方,且与所述侧墙邻近;在所述第一开口和第二开口内形成外延层。
图1为本发明一个实施例半导体器件的形成方法流程示意图,参考图1,包括:
步骤S1,提供衬底,所述衬底上形成有栅极结构及位于所述栅极结构两侧的侧墙;
步骤S2,以所述侧墙为掩膜,在位于所述栅极两侧的衬底内形成第一开口;
步骤S3,对所述第一开口通入刻蚀气体,形成第二开口,所述第二开口与第一开口贯通,所述第二开口位于侧墙下方,且与所述侧墙邻近;
步骤S4,对所述第一开口和第二开口进行退火工艺;
步骤S5,在所述第一开口和第二开口内形成外延层。
为了使本领域技术人员更好的理解本发明,下面结合附图以及具体实施例进行详细说明本发明一个实施例的半导体器件的形成方法。所述外延层可以为硅锗外延层、硅锗硼外延层、硅碳外延层或硅碳磷外延层之一。本实施例中,所述外延层为硅锗外延层。
如图2所示,首先提供衬底100,所述衬底100内形成有隔离区110。本实施例中所述衬底100为按晶面100排布的衬底,即所述衬底100的表面为100晶面,与所述衬底100表面垂直的晶面为110晶面。在所述衬底100表面上形成有栅极结构,所述栅极结构包括栅介质层210和位于所述栅介质层210上的栅极220。
所述衬底100可以是硅基底,隔离结构110可以是氧化硅浅沟槽隔离结构。栅介质层210的材料可以是氧化硅,栅极220的材料可以是掺杂多晶硅、金属、金属硅化物或其他导电材料。本实施例中,需要形成的外延层为PMOS晶体管的外延层,所述衬底100为N型衬底。
继续参考图2,所述栅极结构的表面还形成有侧墙230,所述侧墙230将作为掩膜,对栅极结构两侧的衬底100进行刻蚀,以形成第一开口。
进一步地,在半导体制造工艺中,所述侧墙还形成在NMOS器件区(未图示),用于对所述NMOS器件的栅极结构进行保护,避免所述栅极结构在后续外延生长环境下受到损伤。
其中,所述侧墙230的材料为氧化硅或者氮化硅,或者氧化硅和氮化硅的组合。所述侧墙230的宽度范围为15~20nm。本实施例中,所述侧墙230的宽度为20nm。对应的,本实施例中,所述侧墙宽度可以对NMOS上的栅极结构起到足够保护的作用。作为其他实施例,所述侧墙宽度可以根据实际的工艺要求而设定。
如图3所示,以所述侧墙230为掩膜,对位于所述栅极结构两侧的衬底进行刻蚀,以形成第一开口300a,用以在后续形成外延层,所述第一开口300a采用等离子刻蚀方法形成。
以所述侧墙230为掩膜的刻蚀,为具有较高能量的等离子仅沿所述侧墙230方向纵向进行的刻蚀,所述第一开口300a为矩形,位于所述侧墙230下方的衬底100未被刻蚀,或仅有少量被刻蚀。
进一步地,在进行外延工艺前,需要将上述结构在酸槽内进行清洗处理,以去除位于第一开口300a内的颗粒和有机物。
如图4所示,对所述衬底100进行各向异性或各向同性的气体刻蚀,形成第二开口300b。其中,所述第二开口300b位于侧墙230下方,邻近所述侧墙230,且所述第二开口300b与所述第一开口300a贯通。
进一步地,所述第二开口300b具有靠近侧墙230的侧壁及靠近衬底100的侧壁,其中,所述靠近衬底100的侧壁与衬底100表面所成角度范围为63~90度。所述第二开口300b靠近侧墙230一侧的侧壁的长度范围1~20nm。
具体地形成所述第二开口300b的刻蚀方法为气体刻蚀。优选地,所述刻蚀气体为未被电离化的刻蚀气体,主要通过刻蚀气体的热运动对第一开口300a内部的侧壁和底部进行刻蚀,以形成第二开口300b。
作为一个实施例,各向异性的刻蚀气体为未被电离的含氯气体,所述刻蚀气体可以为氯化氢、或者所述刻蚀气体还可以为氯气和氢气的混合气体。作为其他实施例,所述刻蚀气体可以为未被电离的含溴气体,如溴化氢。
本实施例中,所述刻蚀气体为氯气和氢气的混合气体,具体地所述刻蚀参数为:氯气的流量为50~300sccm,氢气的流量为5~50slm,腔室压力为1~760torr,刻蚀温度为550~850℃,所述刻蚀时间为15~150S。优选地,所述氯气流量为100sccm,所述氢气流量为30slm,腔室压力为500torr,刻蚀温度为800℃,刻蚀时间为100S。
作为其他实施例,若所述刻蚀气体为溴化氢,具体地刻蚀参数为,溴化氢的流量为50~300sccm,腔室压力为10~760torr,刻蚀温度为550~850℃,所述刻蚀时间为15~150S。优选地,所述溴化氢流量为100sccm,腔室压力为500torr,刻蚀温度为700℃,刻蚀时间为120S。
本发明中,所述第一开口300a的底部为材料的100晶面,与所述底部垂直的侧壁为110晶面,且通过刻蚀气体的热运动进行的刻蚀,对于110晶面的刻蚀速率高于100晶面的刻蚀速率,为各向异性的刻蚀过程。区别于定向刻蚀的等离子体刻蚀,本实施例中,因未被电离的刻蚀气体的热运动所进行的刻蚀具有较强的横向刻蚀效果,形成位于侧墙230下方且与所述侧墙230邻近的第二开口300b。
进一步地,通过通入所述刻蚀气体对第一开口300a进行刻蚀,所以刻蚀气体在第一开口300a内部具有浓度梯度分布,主要为由开口处向底部刻蚀气体浓度逐渐递减,所以对于第一开口300a的侧壁,所述刻蚀速率也表现为不同,具体地,对邻近侧墙230的侧壁的刻蚀速率高于邻近第一开口300a底部的侧壁的刻蚀速率,进而造成第二开口300a靠近衬底100的侧壁为倾斜状。
通过刻蚀气体对第一开口300a进行各向异性的刻蚀,形成有第二开口300b,所述第二开口300b主要是在第一开口300a的基础上有侧向尺寸的加大,在纵向上基本没有或只有少许的尺寸加大。进一步地,因为所述第一开口300a内的刻蚀气体浓度具有浓度梯度,所以所述第二开口300b的侧壁为倾斜状。即第二开口300b邻近侧墙230的侧壁开口大于邻近底部的侧壁开口。
作为其他实施例,还可以通过对所述第二开口300b进行修复刻蚀,使所述第二开口300b邻近侧墙230的侧壁开口等于邻近底部的侧壁开口,进而使得所述第二开口300a靠近衬底100的侧壁为垂直状。
后续将在所述第一开口300a和第二开口300b内形成外延层,而所述外延层将形成源区和漏区,在该步骤中,通过各向异性的气体刻蚀形成第二开口300b,且所述第二开口300b邻近侧墙230的尺寸大于邻近底部的尺寸,主要减小了后续形成的源区和漏区的间距,即减小了沟道区尺寸,提高了两侧外延层对沟道区的应力,本实施例中为外延层为PMOS晶体管中的外延层,则对应提高两侧外延层对沟道区的压应力。作为其他实施例,若所述外延层为NMOS晶体管的外延层,则对应提高两侧外延层对沟道区的拉应力。
进一步地,仅仅只对第一开口300a内进行各向异性刻蚀,形成第二开口300b,不需要减小侧墙230的宽度,不会对其他需要侧墙保护的器件,如NMOS器件造成影响。
接着,对所述第一开口300a和第二开口300b进行退火工艺,所述退火工艺可以进一步去除第一开口300a和第二开口300b内表面的氧化物,及其在无尘室空间带来的水分、碳氢有机物等杂质。所述退火工艺的参数包括:氢气的流量为20~50slm,退火时间为60~120S,退火温度800~850℃,腔室压强为1~700Torr。作为一个实施例,所述氢气流量为20slm,退火时间为80S,退火温度为800℃,腔室压强为500Torr。
进一步地,作为一个实施例,为使得所述退火工艺与前步骤的第二开口300b的刻蚀进行良好衔接,所述第二开口300b刻蚀采用氢气和氯化氢作为刻蚀气体,所述退火工艺采用氢气,且所述腔室压强和反应温度均可以选择性的接近,以进行良好的工艺流程的衔接,如气体刻蚀和退火工艺的腔室温度均为500Torr,气体刻蚀和退火工艺的反应温度均为800℃。
如图5所示,通过选择性外延生长工艺,在所述第一开口300a和第二开口300b内形成外延层,所述外延层的厚度范围为300~600埃;本实施例中,所述外延层厚度为300埃。
其中,所述选择性外延生长的腔室压强范围为1~20torr,温度范围为550~800℃。所述选择性外延生长的反应气体至少包含有含硅气体和含锗气体。优选地,所述腔室压强为10torr,温度为600℃。
上述含硅气体的总流量范围为30~300sccm。所述含锗气体的流量范围为5~500sccm。所述反应气体中的含硅气体为硅甲烷、硅乙烷或二氯硅甲烷,所述含锗气体包括锗烷。本实施例中,所述含硅气体的总流量为200sccm,所述含锗气体的流量为300sccm。
进一步地,所述反应气体还可以包含有氯化氢或氢气,或者同时含有氯化氢和氢气,所述氯化氢气体的流量范围为50~200sccm,所述氢气的流量范围为5~50slm。本实施例中,所述氯化氢气体的流量为100sccm,所述氢气的流量为30slm。
其中,所述反应气体中加入氯化氢用以保证外延的选择性。因为在外延锗化硅生长过程中,只需要在开口的硅表面外延生长,其他介电层中不需要形成锗化硅,所以通过加入氯化氢可以避免在介质层上形成锗化硅,以加强形成的外延层的均匀性。
现有技术相比,本发明具有以下优点:
通过对第一开口300a通入刻蚀气体,对第一开口300a进行刻蚀,形成第二开口300b,所述第二开口300b与第一开口300a贯通,且所述第二开口300b位于侧墙230下方,且与所述侧墙230邻近,减小后续形成的源区和漏区的间距,即减小了沟道区尺寸,提高了两侧外延层对沟道区的应力,提高所述PMOS晶体管的性能。若为PMOS晶体管,则增加了外延层对沟道区的压应力;若为NMOS晶体管,则增加了外延层对沟道区的拉应力。本实施例中,所述外延层为PMOS晶体管的外延层。
进一步地,仅仅只对第一开口300a内进行刻蚀形成第二开口300b,不需要减小侧墙230的宽度,即可以减小沟道区的尺寸,不会对其他需要侧墙保护的器件,如NMOS器件造成影响。
本发明还提供一种半导体器件,包括:衬底,所述衬底上形成有栅极结构及位于所述栅极结构两侧的侧墙;位于所述侧墙两侧衬底内的第一开口,及位于所述侧墙下方,且邻近侧墙的第二开口,所述第二开口与第一开口贯通;填充第一开口和第二开口的外延层。
具体地,如图5所示,本发明提供的半导体器件包括:衬底100,位于所述衬底100上的栅极结构及所述栅极结构两侧的侧墙230,所述栅极结构包括依次位于衬底100上的栅极氧化层210及栅极220;位于所述侧墙230两侧衬底100内的第一开口300a,及位于所述侧墙230下方,且邻近侧墙230的第二开口300b,所述第一开口300a和第二开口300b贯通;其中,所述侧墙230的宽度范围为15nm~20nm,所述第二开口300b邻近侧墙230的尺寸宽度范围1nm~20nm。所述第二开口300b具有靠近侧墙230的侧壁及靠近衬底100的侧壁,其中,所述靠近衬底100的侧壁与衬底100表面所成角度范围为63~90度。
所述半导体器件还包括填充所述第一开口300a和第二开口300b的外延层。所述外延层为硅锗外延层、硅锗硼外延层、硅碳外延层或硅碳磷外延层之一。
以上所述仅为本发明的具体实施例,为了使本领域技术人员更好的理解本发明的精神,然而本发明的保护范围并不以该具体实施例的具体描述为限定范围,任何本领域的技术人员在不脱离本发明精神的范围内,可以对本发明的具体实施例做修改,而不脱离本发明的保护范围。
Claims (9)
1.一种半导体器件的形成方法,其特征在于,包括:
提供衬底,所述衬底上形成有栅极结构及位于所述栅极结构两侧的侧墙;
以所述侧墙为掩膜,在位于所述栅极两侧的衬底内形成第一开口;
对所述第一开口通入刻蚀气体,通过刻蚀气体的热运动进行各向异性刻蚀形成第二开口,所述第二开口与第一开口贯通,且所述第二开口位于侧墙下方,且与所述侧墙邻近;
对第一开口和第二开口进行退火工艺;
在所述第一开口和第二开口内形成外延层。
2.如权利要求1所述的半导体器件的形成方法,其特征在于,所述第二开口具有靠近侧墙的侧壁及靠近衬底的侧壁,其中,所述靠近衬底的侧壁与衬底表面所成角度范围为63~90度。
3.如权利要求1所述的半导体器件的形成方法,其特征在于,形成所述第一开口的方法为等离子体刻蚀。
4.如权利要求1所述的半导体器件的形成方法,其特征在于,所述刻蚀气体为氯化氢、或者所述刻蚀气体为氯气和氢气的混和气体。
5.如权利要求1所述的半导体器件的形成方法,其特征在于,所述第二开口的刻蚀参数为:氯气的流量为50~300sccm,氢气的流量为5~50slm,腔室压力为1~760torr,刻蚀温度为550~850℃,所述刻蚀时间为15~150S。
6.如权利要求1所述的半导体器件的形成方法,其特征在于,所述刻蚀气体为溴化氢。
7.如权利要求1所述的半导体器件的形成方法,其特征在于,所述侧墙的宽度范围为15~20nm。
8.如权利要求7所述的半导体器件的形成方法,其特征在于,所述第二开口靠近侧墙一侧的侧壁的长度范围1~20nm。
9.如权利要求1所述的半导体器件的形成方法,其特征在于,所述退火工艺参数为氢气的流量为20~50slm,退火时间为60~120S,退火温度800~850℃,腔室压强为1~700Torr。
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JP4847152B2 (ja) * | 2006-02-22 | 2011-12-28 | 富士通セミコンダクター株式会社 | 半導体装置とその製造方法 |
KR100746232B1 (ko) * | 2006-08-25 | 2007-08-03 | 삼성전자주식회사 | 스트레인드 채널을 갖는 모스 트랜지스터 및 그 제조방법 |
US8138053B2 (en) * | 2007-01-09 | 2012-03-20 | International Business Machines Corporation | Method of forming source and drain of field-effect-transistor and structure thereof |
US8344447B2 (en) * | 2007-04-05 | 2013-01-01 | Taiwan Semiconductor Manufacturing Company, Ltd. | Silicon layer for stopping dislocation propagation |
JP2009152394A (ja) * | 2007-12-20 | 2009-07-09 | Toshiba Corp | 半導体装置及びその製造方法 |
US20110306170A1 (en) * | 2008-08-29 | 2011-12-15 | Texas Instruments Incorporated | Novel Method to Improve Performance by Enhancing Poly Gate Doping Concentration in an Embedded SiGe PMOS Process |
KR20120099863A (ko) * | 2011-03-02 | 2012-09-12 | 삼성전자주식회사 | 트랜지스터 및 그 제조 방법 |
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2010
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US20130320416A1 (en) | 2013-12-05 |
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US8581311B1 (en) | 2013-11-12 |
US8536001B2 (en) | 2013-09-17 |
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