TWI596708B - Ｃｍｏｓ結構其製備方法 - Google Patents

Ｃｍｏｓ結構其製備方法 Download PDF

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TWI596708B
TWI596708B TW105102266A TW105102266A TWI596708B TW I596708 B TWI596708 B TW I596708B TW 105102266 A TW105102266 A TW 105102266A TW 105102266 A TW105102266 A TW 105102266A TW I596708 B TWI596708 B TW I596708B
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肖德元
汝京 張
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上海新昇半導體科技有限公司
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Description

CMOS結構其製備方法
本發明涉及半導體製造領域，尤其涉及一種CMOS結構及其製備方法。
金屬氧化物半導體(MOS)電晶體是積體電路中最重要的主動元件之一，其中，以NMOS電晶體和PMOS電晶體互補形成的CMOS結構是深亞微米超大積體電路的組成單元。為了提高MOS電晶體的載子遷移率，現有技術通常在通道區引入應力，通過改變通道區半導體基底的晶格結構來提高載子的遷移率。現有的應變引入技術通常包括：源極/汲極外延矽鍺技術、應力蝕刻阻擋層技術、應變記憶技術和應力臨近技術等，由於一種應變技術形成產生的應力有限，為了提高通道區的應力，通常採用幾種應變引入技術同時對MOS電晶體的通道區產生應力。
在半導體元件的製備過程中，應力能夠改變矽材料的能帶隙和載子遷移率，從而提高MOS元件的性能，因此，增加應力提高MOS元件性能的技術已經成為越來越普遍的方法。載子的遷移率增加，能夠提高驅動電流，進而顯著的提高CMOS元件的性能。例如，嵌入的矽鍺技術能夠對PMOS電晶體的通道提供壓應力(Compressive stress)，從而增加電洞載子的遷移率，進而提高PMOS電晶體的性能。
然而，現有的CMOS元件中在不同薄膜的界面層，尤其是閘極介電層與通道處通常會存在較多的懸鍵，該懸鍵能夠去除電荷載體或者引入不必要的電荷載體。懸鍵主要發生在表面或元件的界面，同時其也 能夠發生在空缺、微孔隙等處，其也與雜質相關。通常懸鍵過多會造成基底的漏電流偏大，影響元件的整體性能。
本發明的目的在於提供一種CMOS結構及其製備方法，能夠減少懸鍵的數量，降低熱載子效應，提高CMOS的性能。
為了實現上述目的，本發明提出了一種CMOS的製備方法，包括以下步驟：提供基底，所述基底上包括PMOS元件區和NMOS元件區，所述PMOS元件區和NMOS元件區由淺溝槽隔離結構隔離開；在所述PMOS元件區和NMOS元件區上均形成有閘極、側壁、閘極介電層及源極/汲極凹槽，其中，所述閘極介電層形成在所述基底上，所述閘極形成在所述閘極介電層上，所述側壁形成在所述閘極的兩側，所述源極/汲極凹槽分別位於所述閘極兩側的基底中；分別在所述PMOS元件區的源極/汲極凹槽和NMOS元件區的源極/汲極凹槽中形成源極/汲極外延材料，在形成所述源極/汲極外延材料時，使用的載氣包括氘氣。
進一步的，在所述的CMOS的製備方法中，位於所述PMOS元件區的源極/汲極凹槽為Σ形。
進一步的，在所述的CMOS的製備方法中，所述PMOS元件區的源極/汲極凹槽採用乾式蝕刻形成。
進一步的，在所述的CMOS的製備方法中，所述PMOS元件區的源極/汲極凹槽採用濕式蝕刻形成。
進一步的，在所述的CMOS的製備方法中，所述濕式蝕刻採用的溶液為NH3和H2O的混合溶液、KOH溶液或TMAH(tetramethylazanium hydroxide)溶液。
進一步的，在所述的CMOS的製備方法中，所述濕式蝕刻的反應溫度範圍為20攝氏度~100攝氏度，反應時間為30s~400s。
進一步的，在所述的CMOS的製備方法中，形成在PMOS元件區的源極/汲極外延材料為矽鍺。
進一步的，在所述的CMOS的製備方法中，形成矽鍺所採用的反應氣體為GeH4與SiH4、Si2H6、SiH2Cl2、SiHCl3、SiCl4或Si(CH3)4中的一種或者多種混合。
進一步的，在所述的CMOS的製備方法中，所述GeH4的流量或者SiH4、Si2H6、SiH2Cl2、SiHCl3、SiCl4或Si(CH3)4中的一種氣體的流量均為10sccm~800sccm。
進一步的，在所述的CMOS的製備方法中，位於所述NMOS元件區的源極/汲極凹槽為U形。
進一步的，在所述的CMOS的製備方法中，所述NMOS元件區的源極/汲極凹槽採用乾式蝕刻形成。
進一步的，在所述的CMOS的製備方法中，所述乾式蝕刻採用的氣體為Cl2和Ar的混合氣體。
進一步的，在所述的CMOS的製備方法中，所述NMOS元件區的源極/汲極凹槽採用濕式蝕刻形成。
進一步的，在所述的CMOS的製備方法中，形成在NMOS元件區的源極/汲極外延材料為SiC。
進一步的，在所述的CMOS的製備方法中，形成SiC所採用的反應氣體為SiH4和H2與C3H8或CH4的混合氣體。
進一步的，在所述的CMOS的製備方法中，形成源極/汲極外延材料所採用的載氣為氘氣、氘氣和氫氣的混合氣體或氘氣、氫氣和氬氣的混合氣體。
進一步的，在所述的CMOS的製備方法中，形成源極/汲極外延材料所採用的選擇性蝕刻氣體為HCl或者Cl2。
進一步的，在所述的CMOS的製備方法中，所述選擇性蝕刻氣體的流量範圍為10sccm~800sccm。
進一步的，在所述的CMOS的製備方法中，形成源極/汲極外延材料時的溫度範圍是600攝氏度~1200攝氏度。
進一步的，在所述的CMOS的製備方法中，形成外延材料時的壓力範圍是1Torr~500Torr。
在本發明中，還提出了一種CMOS結構，採用如上文所述的CMOS的製備方法製備而成，所述CMOS結構包括：PMOS元件區和NMOS元件區，其中，在所述PMOS元件區和NMOS元件區上均形成有閘極、側壁、閘極介電層及源極/汲極外延材料，所述閘極介電層形成在所述基底上，所述閘極形成在所述閘極介電層上，所述側壁形成在所述閘極的兩側，形成在源極/汲極凹槽內的源極/汲極外延材料分別位於所述閘極兩側的基底中，所述閘極介電層與所述基底界面處存在氘原子。
與現有技術相比，本發明的有益效果主要體現在：在PMOS元件區和NMOS元件區中分別形成源極/汲極外延材料的同時，還使用氘氣作為載氣，從而能夠使氘原子儲存在源極/汲極外延材料的間隙中，作為雜質，由於形成的源極/汲極外延材料作為源極/汲極，其均十分靠近閘極，在閘極介電層形成的過程中，氘能夠擴散出，並與閘極介電層與基底之間界 面處的懸鍵進行結合，形成較為穩定的結構，從而避免載子的穿透，降低熱載子效應，提高元件的性能及可靠性。
S100~S300‧‧‧CMOS：結構製備方法步驟
100‧‧‧基底
110‧‧‧PMOS元件區
120‧‧‧NMOS元件區
200‧‧‧淺溝槽隔離結構
300‧‧‧閘極
400‧‧‧側壁
500‧‧‧閘極介電層
610‧‧‧矽鍺
620‧‧‧SiC
第1圖為本發明一實施例中CMOS的製備方法的流程圖。
第2圖為本發明一實施例中CMOS結構的剖面示意圖。
下面將結合示意圖對本發明的CMOS結構及其製備方法進行更詳細的描述，其中表示了本發明的較佳實施例，應該理解本領域技術人員可以修改在此描述的本發明，而仍然實現本發明的有利效果。因此，下列描述應當被理解為對於本領域技術人員的廣泛知道，而並不作為對本發明的限制。
為了清楚，不描述實際實施例的全部特徵。在下列描述中，不詳細描述公知的功能和結構，因為它們會使本發明由於不必要的細節而混亂。應當認為在任何實際實施例的開發中，必須做出大量實施細節以實現開發者的特定目標，例如按照有關系統或有關商業的限制，由一個實施例改變為另一個實施例。另外，應當認為這種開發工作可能是複雜和耗費時間的，但是對於本領域技術人員來說僅僅是常規工作。
在下列段落中參照附圖以舉例方式更具體地描述本發明。根據下面說明和申請專利範圍書，本發明的優點和特徵將更清楚。需說明的是，附圖均採用非常簡化的形式且均使用非精準的比例，僅用以方便、明晰地輔助說明本發明實施例的目的。
請參考第1圖，在本實施例中，提出了一種CMOS的製備方法，包括步驟：S100：提供基底，所述基底上包括PMOS元件區和NMOS元件區，所述PMOS元件區和NMOS元件區由淺溝槽隔離結構隔離開； S200：在所述PMOS元件區和NMOS元件區上均形成有閘極、側壁、閘極介電層及源極/汲極凹槽，其中，所述閘極介電層形成在所述基底上，所述閘極形成在所述閘極介電層上，所述側壁形成在所述閘極的兩側，所述源極/汲極凹槽分別位於所述閘極兩側的基底中；S300：分別在所述PMOS元件區的源極/汲極凹槽和NMOS元件區的源極/汲極凹槽中形成源極/汲極外延材料，在形成所述源極/汲極外延材料時，使用的載氣包括氘氣。
具體的，請參考第2圖，基底100上包括PMOS元件區110和NMOS元件區120，所述PMOS元件區110和NMOS元件區120由淺溝槽隔離結構200隔離開；其中，淺溝槽隔離結構200為二氧化矽。
在所述PMOS元件區110和NMOS元件區120上均形成有閘極300、側壁400、閘極介電層500及源極/汲極凹槽，其中，所述閘極介電層500形成在所述基底100上，所述閘極300形成在所述閘極介電層500上，所述側壁400形成在所述閘極300的兩側，所述源極/汲極凹槽分別位於所述閘極300兩側的基底100中。
其中，位於PMOS元件區110的源極/汲極凹槽為Σ形(Sigma)，其可以採用乾式蝕刻形成或者濕式蝕刻形成，例如，採用濕式蝕刻時，使用的溶液為NH3和H2O的混合溶液、KOH溶液或者是TMAH溶液(羥化四甲銨，tetramethylazanium hydroxide)，反應溫度範圍為20攝氏度~100攝氏度，例如是50攝氏度，反應時間為30s~400s，例如是200s。
位於所述NMOS元件區120的源極/汲極凹槽為U形，其同樣可以採用濕式蝕刻形成或者乾式蝕刻形成，例如採用乾式蝕刻時，採用的氣體為Cl2和Ar的混合氣體。
在所述PMOS元件區110的源極/汲極凹槽中形成矽鍺610作為源極/汲極外延材料，形成矽鍺610所採用的反應氣體為GeH4與SiH4、Si2H6、SiH2Cl2、SiHCl3、SiCl4或Si(CH3)4中的一種或者多種混合。所述GeH4 的流量或者SiH4、Si2H6、SiH2Cl2、SiHCl3、SiCl4或Si(CH3)4中的一種氣體的流量均為10sccm~800sccm，例如是400sccm；在所述NMOS元件區120的源極/汲極凹槽中形成SiC620作為源極/汲極外延材料，形成SiC620所採用的反應氣體為SiH4和H2與C3H8或CH4的混合氣體。
在所述PMOS元件區110處形成源極/汲極外延材料時，可以先在NMOS元件區120處形成硬遮罩(Hard Mask，HM)將NMOS元件區120遮擋住，避免矽鍺形成在NMOS元件區120，在PMOS元件區110處的矽鍺形成之後，去除NMOS元件區120處的硬遮罩，並在PMOS元件區110處形成硬遮罩作為遮擋，在NMOS元件區120處形成SiC。
此外，在形成所述源極/汲極外延材料時，使用的載氣包括氘氣，例如為純氘氣或者，氘氣和氫氣的混合氣體，或者，氘氣、氫氣和氬氣的混合氣體。
除了使用上述載氣，通常情況下，還可以使用選擇性蝕刻氣體，例如HCl或者Cl2。選擇性蝕刻氣體可以在反應的同時通入，也可以在反應進行一段時間後再通入，具體的可以根據製程要求來決定，選擇性蝕刻氣體可以蝕刻去除多餘的源極/汲極外延材料，有利於源極/汲極外延材料在凹槽中的填充。
形成源極/汲極外延材料時的溫度範圍是600攝氏度~1200攝氏度，例如是1000攝氏度。形成源極/汲極外延材料時的壓力範圍是1Torr~500Torr，例如是300Torr。具體的製程參數可以根據不同的製程環境等進行選擇，在此不作限定。
在本實施例的另一方面，還提出了一種CMOS結構，如第2圖所示，CMOS結構採用如上文所述的CMOS的製備方法製備而成，所述CMOS結構包括：基底100，基底100上包括PMOS元件區110和NMOS元件區120，其中，在所述PMOS元件區110和NMOS元件區120上均形成有閘極300、側壁400、閘極介電層500及源極/汲極凹槽，所述閘極介電 層500形成在所述基底100上，所述閘極300形成在所述閘極介電層500上，所述側壁400形成在所述閘極300的兩側，形成在源極/汲極凹槽內的源極/汲極外延材料分別位於所述閘極300兩側的基底中，所述閘極介電層與所述基底界面處存在氘原子。
綜上，在本發明實施例提供的CMOS結構及其製備方法中，在PMOS元件區和NMOS元件區中分別形成源極/汲極外延材料的同時，還使用氘氣作為載氣，從而能夠使氘原子儲存在源極/汲極外延材料的間隙中，作為雜質，由於形成的源極/汲極外延材料作為源極/汲極，其均十分靠近閘極，在閘極介電層形成的過程中，氘能夠擴散出，並與閘極介電層與基底之間界面處的懸鍵進行結合，形成較為穩定的結構，從而避免載子的穿透，降低熱載子效應，提高元件的性能及可靠性。
上述僅為本發明的較佳實施例而已，並不對本發明起到任何限制作用。任何所屬技術領域的技術人員，在不脫離本發明的技術方案的範圍內，對本發明揭露的技術方案和技術內容做任何形式的等同替換或修改等變動，均屬未脫離本發明的技術方案的內容，仍屬於本發明的保護範圍之內。
S100~S300‧‧‧CMOS結構製備方法步驟

Claims (21)

  1. 一種CMOS的製備方法，包括以下步驟：提供基底，該基底上包括PMOS元件區和NMOS元件區，該PMOS元件區和該NMOS元件區由淺溝槽隔離結構隔離開；在該PMOS元件區和該NMOS元件區上均形成有閘極、側壁、閘極介電層及源極/汲極凹槽，其中，該閘極介電層形成在該基底上，該閘極形成在該閘極介電層上，該側壁形成在該閘極的兩側，該源極/汲極凹槽分別位於靠近該閘極兩側的該基底中；分別在該PMOS元件區的該源極/汲極凹槽和該NMOS元件區的該源極/汲極凹槽中形成源極/汲極外延材料，在形成該源極/汲極外延材料時，使用的載氣包括氘氣。
  2. 如申請專利範圍第1項所述的CMOS的製備方法，其中，位於該PMOS元件區的該源極/汲極凹槽為Σ形。
  3. 如申請專利範圍第2項所述的CMOS的製備方法，其中，該PMOS元件區的該源極/汲極凹槽採用乾式蝕刻形成。
  4. 如申請專利範圍第2項所述的CMOS的製備方法，其中，該PMOS元件區的該源極/汲極凹槽採用濕式蝕刻形成。
  5. 如申請專利範圍第4項所述的CMOS的製備方法，其中，該濕式蝕刻採用的溶液為NH3和H2O的混合溶液、KOH溶液或TMAH溶液。
  6. 如申請專利範圍第4項所述的CMOS的製備方法，其中，該濕式蝕刻的反應溫度範圍為20攝氏度~100攝氏度，反應時間為30s~400s。
  7. 如申請專利範圍第1項所述的CMOS的製備方法，其中，形成在該PMOS元件區的該源極/汲極外延材料為矽鍺。
  8. 如申請專利範圍第7項所述的CMOS的製備方法，其中，形成該矽鍺所採用的反應氣體為GeH4與SiH4、Si2H6、SiH2Cl2、SiHCl3、SiCl4或Si(CH3)4中的一種或者多種混合。
  9. 如申請專利範圍第8項所述的CMOS的製備方法，其中，該GeH4的流量或者SiH4、Si2H6、SiH2Cl2、SiHCl3、SiCl4或Si(CH3)4中的一種氣體的流量均為10sccm~800sccm。
  10. 如申請專利範圍第1項所述的CMOS的製備方法，其中，位於該NMOS元件區的該源極/汲極凹槽為U形。
  11. 如申請專利範圍第10項所述的CMOS的製備方法，其中，該NMOS元件區的該源極/汲極凹槽採用乾式蝕刻形成。
  12. 如申請專利範圍第11項所述的CMOS的製備方法，其中，該乾式蝕刻採用的氣體為Cl2和Ar的混合氣體。
  13. 如申請專利範圍第1項所述的CMOS的製備方法，其中，該NMOS元件區的該源極/汲極凹槽採用濕式蝕刻形成。
  14. 如申請專利範圍第1項所述的CMOS的製備方法，其中，形成在該NMOS元件區的該源極/汲極外延材料為SiC。
  15. 如申請專利範圍第14項所述的CMOS的製備方法，其中，形成該SiC所採用的反應氣體為SiH4和H2與C3H8或CH4的混合氣體。
  16. 如申請專利範圍第1項所述的CMOS的製備方法，其中，形成該源極/汲極外延材料所採用的載氣為氘氣、氘氣和氫氣的混合氣體或氘氣、氫氣和氬氣的混合氣體。
  17. 如申請專利範圍第1項所述的CMOS的製備方法，其中，形成該源極/汲極外延材料所採用的選擇性蝕刻氣體為HCl或者Cl2。
  18. 如申請專利範圍第17項所述的CMOS的製備方法，其中，該選擇性蝕刻氣體的流量範圍為10sccm~800sccm。
  19. 如申請專利範圍第1項所述的CMOS的製備方法，其中，形成該源極/汲極外延材料時的溫度範圍是600攝氏度~1200攝氏度。
  20. 如申請專利範圍第1項所述的CMOS的製備方法，其中，形成該源極/汲極外延材料時的壓力範圍是1Torr~500Torr。
  21. 一種CMOS結構，其中，採用如申請專利範圍第1項至第20項中任一項該的CMOS的製備方法製備而成，該CMOS結構包括：PMOS元件區和NMOS元件區，其中，在該PMOS元件區和NMOS元件區上均形成有閘極、側壁、閘極介電層及源極/汲極凹槽，該閘極介電層形成在該基底上，該閘極形成在該閘極介電層上，該側壁形成在該閘極的兩側，形成在該源極/汲極凹槽內的源極/汲極外延材料分別位於該閘極兩側的該基底中，該閘極介電層與該基底界面處存在氘原子。
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