TWI545769B - 半導體裝置結構與其形成方法 - Google Patents

半導體裝置結構與其形成方法 Download PDF

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TWI545769B
TWI545769B TW103124694A TW103124694A TWI545769B TW I545769 B TWI545769 B TW I545769B TW 103124694 A TW103124694 A TW 103124694A TW 103124694 A TW103124694 A TW 103124694A TW I545769 B TWI545769 B TW I545769B
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layer
source
stress
semiconductor device
cap layer
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TW201526240A (zh
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黃信燁
張凱翔
江知諶
彭翊瑋
林冠宇
蔡明山
賴經綸
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台灣積體電路製造股份有限公司
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Description

半導體裝置結構與其形成方法
本揭露係有關於一種半導體裝置結構，且特別有關於一種半導體裝置結構與其形成方法。
半導體裝置使用於各種電子應用中，舉例而言，諸如個人電腦、手機、數位相機以及其他電子設備。半導體裝置的製造通常是藉由在半導體基板上依序沉積絕緣或介電層材料、導電層材料以及半導體層材料，接著使用微影製程圖案化所形成的各種材料層，以形成電路組件和零件於此半導體基板之上。通常許多積體電路製作於單一半導體晶圓中，且沿著切割線(scribe line)切割相鄰的積體電路，以切割位在晶圓上的各晶粒。舉例而言，通常各自的晶粒被分別封裝在多種晶片模組(multi-chip modules)或其他類似的封裝結構中。
在半導體業界，不斷降低最小特徵尺寸，如此一來可允許更多的裝置集積於一個特定的區域中，藉此持續改善各種電子裝置(例如電晶體、二極體、電阻、電容等等)的集積密度。在某些應用中，相較於過去的產品，這些尺寸更小的電子裝置需要利用較少區域及/或較低高度之更小的封裝。
具有應力區域的金屬氧化物半導體場效電晶體 (MOSFET)通常用於提高金屬氧化物半導體場效電晶體的性能表現。已經有各種技術關於源極與汲極結構特徵的形狀、構造與材料，用於增進電晶體元件的性能表現。雖然目前有各種方法應用於特定用途，然而，這些元件尚未能滿足所有要求。
本揭露提供一種半導體裝置結構，包括：一基板；一閘極堆疊結構形成於該基板之上；複數個閘極間隙壁形成於該閘極堆疊結構之側壁上；一隔離結構形成於該基板之中；以及一源極/汲極應力結構(source/drain stressor structure)相鄰於該隔離結構，其中該源極/汲極應力結構包括一蓋層，其中該蓋層沿著(311)及(111)之晶面方向(crystal orientations)成長。
本揭露亦提供一種半導體裝置結構，包括：一基板；一閘極堆疊結構形成於該基板之上；複數個閘極間隙壁形成於該閘極堆疊結構之側壁上；複數個摻雜區域形成於該基板中；一隔離結構形成於該基板之中；以及一源極/汲極應力結構(source/drain stressor structure)形成於該些摻雜區域與該隔離結構之間，其中該源極/汲極應力結構包括：一應力層形成於該基板中；以及一蓋層形成於該應力層之上，其中該蓋層從該摻雜區域朝下傾斜(slanted downward)到該隔離結構。
本揭露又提供一種半導體裝置結構之形成方法，包括以下步驟：提供一晶圓，其中該晶圓具有一中心區域與一邊緣區域；形成一半導體裝置結構於該中心區域與該邊緣區域之上，其中形成該半導體裝置結構包括：形成一隔離結構於該晶圓之該邊緣區域中；形成一閘極堆疊結構於該晶圓之邊緣區 域之上；形成複數個閘極間隙壁於該閘極堆疊結構之側壁上；在閘極間隙壁之下摻雜該晶圓，以形成複數個摻雜區域；以及成長一源極/汲極應力結構(source/drain stressor structure)介於該摻雜區域與該隔離結構之間，其中該源極/汲極應力結構包括一蓋層，其中該蓋層沿著(311)及(111)之晶面方向(crystal orientations)成長。
以下特舉出本揭露之實施例，並配合所附圖式作詳細說明。以下實施例的裝置和設計係為了簡化所揭露之發明，並非用以限定本揭露。本揭露於各個實施例中可能使用重複的參考符號及/或用字。這些重複符號或用字係為了簡化與清晰的目的，並非用以限定各個實施例及/或所述結構之間的關係。此外，說明書中提到在第二製程進行之前實施第一製程可包括第二製程於第一製程之後立即進行第二製程，也可包括有其他製程介於第一製程與第二製程之間的實施例。下述圖形並非依據尺寸繪製，該些圖式僅為了幫助說明。再者，說明書中提及形成第一特徵結構位於第二特徵結構之上，其包括第一特徵結構與第二特徵結構是直接接觸的實施例，另外也包括於 第一特徵結構與第二特徵結構之間另外有其他特徵結構的實施例，亦即，第一特徵結構與第二特徵結構並非直接接觸。
下文描述實施例的各種變化。藉由各種橫截面圖與顯示之實施例，類似的元件標號用於標示類似的元件。需注意的是，其他步驟可實施於方法之前、之間或之後，且一些步驟可以被其他實施例的方法所取代或刪除。
本揭露提供形成半導體裝置結構之各種實施例。依據本揭露之一些實施例，第1A圖至第1E圖顯示形成半導體裝置結構100之各個製程階段的剖面圖。
請參見第1A圖，提供基板102。基板102由矽或其他半導體材料所組成。另外，基板102可包括其他元素半導體，例如鍺。在一些實施例中，基板102由化合物半導體所組成，例如，碳化矽(silicon carbide)、砷化鎵(gallium arsenic)、砷化銦(indium arsenide)或磷化銦(indium phosphide)。在一些實施例中，基板102由合金半導體所組成，例如矽鍺(silicon germanium)、碳化矽鍺(silicon germanium carbide)、磷化鎵砷(gallium arsenic phosphide)或磷化鎵銦(gallium indium phosphide)。在一些實施例中，基板102包括磊晶層。舉例而言，基板102具有磊晶層位於塊狀半導體(bulk semiconductor)之上。
基板102可包括隔離結構104，例如淺溝隔離結構(shallow trench isolation,STI)或區域性矽氧化隔離結構(local oxidation of silicon,LOCOS)。隔離結構104可用於定義與隔離各種積體電路裝置。
在第1A圖中，在基板102之上形成閘極堆疊結構110，閘極堆疊結構110包括閘極介電層112與閘極電極層114。
閘極介電層112形成於半導體基板102之上。閘極介電層112由氧化矽、氮氧化矽或高介電常數(high-k)材料所組成。高介電常數材料可包括二氧化鉿(hafnium oxide,HfO2)、氧化矽鉿(hafnium silicon oxide,HfSiO)、氮氧化矽鉿(hafnium silicon oxynitride,HfSiON)、氧化鉭鉿(hafnium tantalum oxide,HfTaO)、氧化鈦鉿(hafnium titanium oxide,HfTiO)、氧化鋯鉿(hafnium zirconium oxide,HfZrO)或其它合適的高介電常數介電材料。高介電常數材料可更包括金屬氧化物(metal oxides)、金屬氮化物(metal nitrides)、金屬矽化物(metal silicates)、過渡金屬氧化物(transition metal-oxides)、過渡金屬氮化物(transition metal-nitrides)、過渡金屬矽化物(transition metal-silicates)、金屬氮氧化物(oxynitrides of metals)、金屬鋁酸鹽(metal aluminates)、矽酸鋯(zirconium silicate)、鋁酸鋯(zirconium aluminate)、氧化矽(silicon oxide)、氮化矽(silicon nitride)、氮氧化矽(silicon oxynitride)、氧化鋯(zirconium oxide)、氧化鈦(titanium oxide)、氧化鋁(aluminum oxide)、二氧化鉿-三氧化二鋁(hafnium dioxide-alumina,HfO2-Al2O3)合金或其它合適的材料。閘極介電層112藉由適合的方式形成，例如，原子層沉積法(atomic layer deposition,ALD)、化學氣相沉積法(chemical vapor deposition,CVD)、物理氣相沉積法(physical vapor deposition,PVD)、減壓化學氣相沉積法(reduced pressure CVD,RPCVD)、電漿輔助化學氣相沉積法 (plasma enhanced CVD,PECVD)、有機金屬化學氣相沉積法(metal organic CVD,MOCVD)、濺鍍(sputtering)、電鍍(plating)或其他適合的製程。
接著，閘極電極層114形成於半導體基板102之 上，閘極電極層114由下列材料所組成，例如多晶矽、金屬或金屬矽化物。在一些實施例中，閘極電極層114由多晶矽層所組成，其中此多晶矽層係當作虛擬閘極，且此虛擬閘極在後續的閘極置換製程中將被置換。在一些實施例中，利用化學氣相沉積法形成閘極電極層114。
閘極間隙壁116形成於閘極堆疊結構110相對兩側 的側壁上。在一些實施例中，在半導體基板102之上沉積介電層，並且實施蝕刻製程移除一部分的介電層，藉以形成閘極間隙壁116。閘極間隙壁116由氧化矽、氮化矽、氮氧化矽及/或介電材料所組成。閘極間隙壁116可包括單一層或多層。
此外，在半導體基板102之上可形成另一閘極堆疊 結構150，閘極堆疊結構150可包括閘極介電層152與閘極電極層154。閘極間隙壁156形成於閘極堆疊結構150的側壁上。
依據本揭露之一些實施例，形成閘極間隙壁116及 156之後，在基板102之中形成摻雜區域122及162，如第1A圖所示。摻雜區域122及162對準閘極間隙壁116及156之內側。在一些實施例中，摻雜區域122及162摻雜n型摻雜質，例如砷(arsenic,As)、磷(phosphorous,P)或銻(antimony,Sb)。在一些其他實施例中，對摻雜區域122及162摻雜p型摻雜質，例如硼(boron,B)或二氟化硼(boron fluorine,BF2)。在一些實施例中， 摻雜砷的摻雜區域122及162，其摻雜的砷之濃度介於1×1012至1×1015 atom/cm2的範圍之間。摻雜區域122及162具有梯度(gradient)的混摻濃度，且混摻濃度從摻雜區域122及162之內側到外側呈現下降的趨勢。
在一些實施例中，對摻雜區域122及162實施離子 佈植(ion implantation,IMP)製程(圖中未顯示)。在一些實施例中，在功率介於10keV至80keV的範圍之間進行離子佈植製程。
依據本揭露之一些實施例，接著，實施乾式蝕刻 製程(圖中未顯示)以移除一部分的基板102，並形成凹口(recess)130及130’，如第1A圖所示。在一些實施例中，乾式蝕刻製程包括電漿蝕刻製程。凹口130形成於閘極堆疊結構110及隔離結構104之間，凹口130’形成於閘極堆疊結構110及閘極堆疊結構150之間。
在一些實施例中，乾式蝕刻製程所使用的蝕刻氣 體包括氦氣(helium,He)、氬氣(argon,Ar)、氯氣(chlorine,C12)、氧氣(oxygen,O2)、溴化氫(HBr)、氮氣(N2)、四氟化碳(CF4)及氟甲烷(CH3F)。在一些實施例中，氯氣對氦氣的比率介於0.1至10的範圍之間。
如第1A圖所示，凹口130及130’為圓形。在一些實施例中，凹口130具有深度X1介於50nm至90nm的範圍之間。
在一些實施例中，在乾式蝕刻製程之後，實施濕式蝕刻製程(圖中未顯示)擴大凹口30，以形成一個擴大的凹口(圖中未顯示)。在一些實施例中，濕式蝕刻製程包括一蝕刻溶液，此蝕刻溶液包括四甲基氫氧化銨(tetramethyl ammonium hydroxide,TMAH)、氫氧化銨(ammonium hydroxide,NH4OH)、氫氧化鉀(potassium hydroxide,KOH)、氫氟酸(hydrofluoric acid,HF)或其它合適的蝕刻溶液。
依據本揭露之一些實施例，形成凹口130及130’之後，在凹口130之中形成應力層(stressor layer)142，如第1B圖所示。半導體裝置100的通道區域受到應力層142的應力調整。對n型金屬氧化物半導體(NMOS)裝置而言，應力層142對半導體裝置100的通道區域導入拉伸應變。對p型金屬氧化物半導體(PMOS)裝置而言，應力層142對半導體裝置100的通道區域導入壓縮應變。
如第1B圖所示，應力層142為五角形。在一些實施例中，應力層142具有第一晶面(facet)142A、第二晶面142B、第三晶面142C、第四晶面142D及第五晶面142E。此外，應力層172形成於凹口130’之中，並且同樣為五角形。
在一些實施例中，應力層142及172由矽鍺(SiGe)所組成。在一些實施例中，利用磊晶(epitaxy)製程形成應力層142。磊晶(epitaxy)製程可包括選擇性磊晶成長(selective epitaxial growth,SEG)製程、化學氣相沉積技術(例如，氣相磊晶(vapor-phase epitaxy,VPE)及/或超高真空化學氣相沉積法(ultra-high vacuum CVD,UHV-CVD))、分子束磊晶(molecular beam epitaxy,MBE)或其他合適的磊晶製程。磊晶製程可使用氣態及/或液態前驅物，這些氣態或液態前驅物能夠與基板102的組成成分交互作用。
應注意的是，由氧化物所組成之隔離結構104的表 面自由能(surface free energy)高於由矽所組成之半導體基板102的表面自由能。為了平衡隔離結構104的表面自由能，相鄰於隔離結構104的應力層142形成最密堆積(close-packed)結構。在一些實施例中，應力層142沿著(311)及(111)之晶面方向(crystal orientations)成長。舉例而言，第一晶面142A沿著(311)晶面方向成長，且第二晶面142B沿著(111)晶面方向成長。
在一些實施例中，應力層172形成於閘極堆疊結構 110及閘極堆疊結構150之間。相較於應力層142，應力層172較遠離隔離結構104，因此應力層172並未具有最密堆積(close-packed)結構。在一些實施例中，應力層172沿著(111)及(100)之晶面方向成長。
依據本揭露之一些實施例，形成應力層142之後， 在應力層142之上形成蓋層(capping layer)144，如第1C圖所示。蓋層144可降低應力層142的片電阻(sheet resistance)，以提供優異的接觸特性。蓋層144及應力層142構成源極/汲極應力結構(source/drain stressor structure)140。
蓋層144為含矽層。在一些實施例中，蓋層144由矽鍺(SiGe)、矽(Si)、碳化矽(SiC)或矽鍺錫(SiGeSn)所組成。覆蓋應力層142之蓋層144的一部分高於基板102的頂部表面。覆蓋應力層142之蓋層144的一部分低於基板102的頂部表面。蓋層144亦沿著(311)及(111)之晶面方向成長。舉例而言，蓋層144具有第一晶面144A及第二晶面144B。第一晶面144A沿著(311)之晶面方向成長，且第二晶面144B沿著(111)之晶面方向成長。在一些實施例中，利用選擇性磊晶成長(SEG)製程形成 蓋層144。
此外，相似於蓋層144，蓋層174形成於應力層172 之上。覆蓋應力層172之蓋層174高於基板102的頂部表面。蓋層174及應力層172構成源極/汲極應力結構170。在一些實施例中，蓋層174由矽鍺(SiGe)、矽(Si)、碳化矽(SiC)或矽鍺錫(SiGeSn)所組成。在一些實施例中，利用選擇性磊晶成長(SEG)製程形成蓋層174。
應注意的是，蓋層144形成於應力層142之上，因 此蓋層144是沿著應力層142的成長方向成長。介於蓋層144與應力層142之間的邊界是沿著(311)及(111)之晶面方向成長。由於應力層142具有最密堆積結構，蓋層144亦具有最密堆積結構。換句話說，蓋層144順應應力層142的形狀。此外，為了形成最密堆積結構，形成蓋層144的晶面成長速率小於形成蓋層174的晶面成長速率。因此，如第1C圖所示，從摻雜區域122到隔離結構104，蓋層144為朝下傾斜的，且蓋層144的一部分低於基板102的頂部表面。
此外，為了形成最密堆積結構，必須提供足夠數量，以形成蓋層144的原子，否則可能會形成太薄的蓋層144。舉例而言，若用以形成蓋層144的矽材料源不足，則蓋層144的厚度太薄而無法形成金屬矽化物層(後續將形成金屬矽化物層，如第1D圖所示)於其上。如此一來，將形成品質低劣的金屬矽化物層及接觸結構。因此，過高的接觸阻抗(contact resistance)將導致短路及漏電流等問題伴隨發生。
為了解決短路及漏電流等問題，在一些實施例 中，用以形成蓋層144的矽材料源在磊晶成長製程期間得到良好的控制，藉以獲得較厚的蓋層144。此控制方法將於第2圖詳細描述。在一些實施例中，蓋層144具有厚度T1介於10nm至30nm的範圍之間。
依據本揭露之一些實施例，形成蓋層144之後，在 蓋層144之上形成金屬矽化物層146，如第1D圖所示。舉例而言，在蓋層144之上設置金屬膜，以使金屬膜直接接觸蓋層144暴露的矽表面。可藉由實施任何合適的製程形成金屬膜，例如，物理氣相沉積法(PVD)、化學氣相沉積法(CVD)、電鍍(plating)、無電電鍍(electroless plating)或其他類似的製程。接著，進行快速高溫回火步驟，使所沉積的金屬膜與暴露的矽表面進行反應，藉以形成金屬矽化物層146。接著利用蝕刻製程移除所沉積之金屬膜未反應的部分。相較於未矽化的區域，金屬矽化物層146具有較低的阻抗，特別是在較小的幾何尺寸之下。
依據本揭露之一些實施例，形成金屬矽化物層146 之後，在基板102之上形成層間介電(inter-layer dielectric,ILD)層147，並且在層間介電層147之上形成接觸結構148，如第1E圖所示。舉例而言，在層間介電層147之中形成開口(圖中未顯示)，並將導電材料填入開口中以形成接觸結構148。接觸結構148直接接觸金屬矽化物層146。接觸結構148由導電材料所組成，例如，銅或銅合金。如此一來，半導體裝置結構100即已完成。
接著，基板102可繼續進行其他步驟以形成其他裝 置，例如金屬層間介電(inter-metal dielectric,IMD)層或內連線結構(interconnect structures)。本揭露之實施例的優點在於，在形成蓋層144的製程期間控制矽材料源，藉以使相鄰於隔離結構104的源極/汲極應力結構140具有較厚的蓋層144。因此，可藉由形成較厚的蓋層144改善金屬矽化物層146的品質。再者，亦可進一步改善接觸結構148的品質。此外，用以形成接觸結構148的製程容許範圍(process window)亦得以擴大。
依據本揭露之一些實施例，第2圖顯示晶圓在磊晶 製程期間的俯視圖。在一些實施例中，磊晶製程為選擇性磊晶成長(SEG)製程。
請參照第2圖，提供一晶圓10。晶圓10具有中心區 域10C及邊緣區域10E。在晶圓10的中心區域10C及邊緣區域10E上形成一些半導體裝置結構100(顯示於第1E圖)。
一些材料氣體源(source gas)包括矽材料氣體源或 鍺材料氣體源。在一些實施例中，用以形成蓋層144的矽材料氣體源包括矽甲烷(mono silane,SiH4)、矽乙烷(disilane,Si2H6)、二氯矽甲烷(dichloro silane,DCS,SiH2Cl2)、六氯矽乙烷(hexachloro disilane,HCD)、雙-乙甲胺基矽烷(bis(ethylmethylamino)silan,BEMAS)、雙-二乙胺基矽烷(bis(diethylamino)silane,BDEAS)、雙-二甲胺基矽烷(Bis(dimethylamino)silane,BDMAS)、三-二甲胺基矽烷(tris(dimethylamino)silane,Tris-DMAS)、四-二甲胺基矽烷(tetrakis(dimethylamino)silane,TDMAS)、三-乙甲胺基矽烷(tris(ethlymethylamino)silane,Tris-EMAS)、二乙胺基矽烷 (diethylamino silane,DEAS)、雙-第三丁基胺基矽烷(bis(tert-butylamino)silane,BTBAS)或二-異丙基胺基矽烷(di-isopropyl-amino-silane,DIPAS)。而鍺材料氣體源可以是，例如，鍺甲烷(germane,GeH4)。此外，在選擇性磊晶成長製程期間也使用了反應源氣體(reaction source gas)、蝕刻氣體(例如氯化氫)及載流氣體(例如氫氣)。
如第2圖所示，主要氣體供應器(main gas suppliers)22a、22b及22c主要提供至中心區域10C，且邊緣氣體供應器(edge gas suppliers)32a、32b及32c提供至邊緣區域10E。在一些實施例中，主要氣體供應器22a、22b及22c分別導入矽甲烷(mono silane,SiH4)、鍺甲烷(germane,GeH4)及氯化氫(HCl)，且邊緣氣體供應器32a、32b及32c分別導入矽甲烷(mono silane,SiH4)、鍺甲烷(germane,GeH4)及氯化氫(HCl)。
在一些實施例中，材料氣體源隨著載流氣體提 供。在中心區域10C的載流氣體流速高於在邊緣區域10E的載流氣體流速。在一些實施例中，在中心區域10C的載流氣體流速介於10slm至30slm的範圍之間。在一些實施例中，在邊緣區域10E的載流氣體流速介於200sccm至2000sccm的範圍之間。
在一些實施例中，以A1軸為中心旋轉晶圓10。由 於晶圓10藉由旋轉以進行反應，主要氣體供應器22a、22b及22c所供應的材料氣體源可能會從中心區域10C擴散至邊緣區域10E。因此，在邊緣區域10E的材料氣體源濃度小於在中心區域10C的材料氣體源濃度。材料氣體源的濃度不均勻性可能導致發生在邊緣區域10E的不足。為了彌補上述材料不足，邊緣氣 體供應器32a、32b及32c獨立供應至材料氣體源邊緣區域10E，如第2圖之箭頭標號50所示。
此外，由於供應至邊緣區域10E的材料氣體源不足，因此半導體裝置結構100的短路及漏電流等問題在邊緣區域10E比在中心區域10C更為嚴重。如上所述，用以形成蓋層144的矽材料源在選擇性磊晶成長製程期間得到良好的控制，可獲得較厚的蓋層144。因此，在邊緣區域10E所進行之用以形成蓋層144及/或應力層142的選擇性磊晶成長製程受到控制，而符合下列方程式(I)：邊緣區域-E/D=氯化氫(HCl source)的流速/矽源(Si source)與鍺源(Ge source)之流速總和---(I)
在一些實施例中，邊緣區域-E/D值介於0.2至0.8的範圍之間。若邊緣區域-E/D值太大，則沒有足夠的材料氣體源供應至晶圓10，因此將得到太薄的蓋層144。反之，若邊緣區域-E/D值太小，則會發生嚴重的選擇性損失(selectivity loss)，進而導致磊晶層的品質低劣。
在一些實施例中，在邊緣區域10E之用以形成蓋層144的材料氣體源介於100sccm至400sccm的範圍之間。在一些其他實施例中，在邊緣區域10E之用以形成蓋層144的材料氣體源介於50sccm至200sccm的範圍之間。
在一些實施例中，在溫度介於500℃至850℃的範圍之間實施用以形成蓋層144及/或應力層142的選擇性磊晶成長製程。在一些其他實施例中，在壓力介於1torr至760torr的範圍之間實施用以形成蓋層144及/或應力層142的選擇性磊晶 成長製程。
在邊緣區域10E之蓋層144的厚度藉由邊緣區域 -E/D值而受到良好的控制。充分地供應材料氣體源以符合蓋層144的晶面成長速率(facet growth rate)，特別是在邊緣區域10E。因此，蓋層144具有足夠的厚度以形成高品質的金屬矽化物層146及接觸結構148。
本揭露提供形成半導體裝置結構之實施例。一源 極/汲極應力結構(source/drain stressor structure)形成於一閘極堆疊結構與一隔離結構之間。源極/汲極應力結構具有應力層與蓋層。蓋層具有足夠的厚度，以形成高品質的金屬矽化物層與接觸結構。因此，解決短路及漏電流的問題。此外，用以形成接觸結構製程容許範圍(process window)亦得以擴大。
在一些實施例中，本揭露提供一種半導體裝置結 構，包括：一基板；一閘極堆疊結構形成於該基板之上；複數個閘極間隙壁形成於該閘極堆疊結構之側壁上；一隔離結構形成於該基板之中；以及一源極/汲極應力結構(source/drain stressor structure)相鄰於該隔離結構，其中該源極/汲極應力結構包括一蓋層，其中該蓋層沿著(311)及(111)之晶面方向(crystal orientations)成長。
在一些實施例中，本揭露另提供一種半導體裝置 結構，包括：一基板；一閘極堆疊結構形成於該基板之上；複數個閘極間隙壁形成於該閘極堆疊結構之側壁上；複數個摻雜區域形成於該基板中；一隔離結構形成於該基板之中；以及一源極/汲極應力結構(source/drain stressor structure)形成於該些 摻雜區域與該隔離結構之間，其中該源極/汲極應力結構包括：一應力層形成於該基板中；以及一蓋層形成於該應力層之上，其中該蓋層從該摻雜區域朝下傾斜(slanted downward)到該隔離結構。
在一些實施例中，本揭露亦提供一種半導體裝置 結構之形成方法，包括以下步驟：提供一晶圓，其中該晶圓具有一中心區域與一邊緣區域；形成一半導體裝置結構於該中心區域與該邊緣區域之上，其中形成該半導體裝置結構包括：形成一隔離結構於該晶圓之該邊緣區域中；形成一閘極堆疊結構於該晶圓之邊緣區域之上；形成複數個閘極間隙壁於該閘極堆疊結構之側壁上；在閘極間隙壁之下摻雜該晶圓，以形成複數個摻雜區域；以及成長一源極/汲極應力結構(source/drain stressor structure)介於該些摻雜區域與該隔離結構之間，其中該源極/汲極應力結構包括一蓋層，其中該蓋層沿著(311)及(111)之晶面方向(crystal orientations)成長。
雖然本揭露已以數個較佳實施例揭露如上，然其並非用以限定本揭露，任何所屬技術領域中具有通常知識者，在不脫離本揭露之精神和範圍內，當可作任意之更動與潤飾，因此本揭露之保護範圍當視後附之申請專利範圍所界定者為準。
10‧‧‧晶圓
10C‧‧‧中心區域
10E‧‧‧邊緣區域
A1‧‧‧軸
22a、22b及22c‧‧‧主要氣體供應器(main gas suppliers)
32a、32b及32c‧‧‧邊緣氣體供應器(edge gas suppliers)
50‧‧‧箭頭
100‧‧‧半導體裝置結構
102‧‧‧基板
104‧‧‧隔離結構
110‧‧‧閘極堆疊結構
112‧‧‧閘極介電層
114‧‧‧閘極電極層
116‧‧‧閘極間隙壁
122‧‧‧摻雜區域
130、130’‧‧‧凹口
140‧‧‧源極/汲極應力結構(source/drain stressor structure)
142‧‧‧應力層
142A‧‧‧第一晶面(facet)
142B‧‧‧第二晶面
142C‧‧‧第三晶面
142D‧‧‧第四晶面
142E‧‧‧第五晶面
144‧‧‧~蓋層
144A‧‧‧第一晶面(facet)
144B‧‧‧第二晶面
146‧‧‧金屬矽化物層
147‧‧‧層間介電層
148‧‧‧接觸結構
150‧‧‧閘極堆疊結構
152‧‧‧閘極介電層
154‧‧‧閘極電極層
156‧‧‧閘極間隙壁
162‧‧‧摻雜區域
170‧‧‧源極/汲極應力結構
172‧‧‧應力層
174‧‧‧蓋層
第1A圖~第1E圖顯示依據本揭露之實施例形成半導體結構之各個製程階段的剖面圖。
第2圖顯示依據本揭露之實施例之磊晶製程過程中晶圓之俯視圖。
100‧‧‧半導體裝置結構
102‧‧‧基板
104‧‧‧隔離結構
110‧‧‧閘極堆疊結構
142‧‧‧應力層
144‧‧‧蓋層
146‧‧‧金屬矽化物層
147‧‧‧層間介電層
148‧‧‧接觸結構
150‧‧‧閘極堆疊結構
172‧‧‧應力層
174‧‧‧蓋層

Claims (9)

  1. 一種半導體裝置結構，包括：一基板；一閘極堆疊結構形成於該基板之上；複數個閘極間隙壁形成於該閘極堆疊結構之側壁上；一隔離結構形成於該基板之中；以及一源極/汲極應力結構(source/drain stressor structure)相鄰於該隔離結構，其中該源極/汲極應力結構包括一蓋層及一應力層，其中該蓋層沿著(311)及(111)之晶面方向(crystal orientations)成長，該應力層形成於該基板與該蓋層之間，及其中該應力層的一部分沿著(311)及(111)之晶面方向成長。
  2. 如申請專利範圍第1項所述之半導體裝置結構，其中該半導體裝置結構位於一晶圓之邊緣區域。
  3. 如申請專利範圍第1項所述之半導體裝置結構，尚包括：一金屬矽化物層形成於該源極/汲極應力結構之上。
  4. 一種半導體裝置結構，包括：一基板；一閘極堆疊結構形成於該基板之上；複數個閘極間隙壁形成於該閘極堆疊結構之側壁上；複數個摻雜區域形成於該基板中；一隔離結構形成於該基板之中；以及一源極/汲極應力結構(source/drain stressor structure)形成於該些摻雜區域與該隔離結構之間，其中該源極/汲極應力 結構包括：一應力層形成於該基板中，其中該應力層的一部分沿著(311)及(111)之晶面方向成長；以及一蓋層形成於該應力層之上，其中該蓋層從該摻雜區域朝下傾斜(slanted downward)到該隔離結構。
  5. 如申請專利範圍第4項所述之半導體裝置結構，其中介於該應力層與該蓋層之間的界面沿著(311)及(111)之晶面方向(crystal orientations)成長。
  6. 一種半導體裝置結構之形成方法，包括以下步驟：提供一晶圓，其中該晶圓具有一中心區域與一邊緣區域；形成一半導體裝置結構於該中心區域與該邊緣區域之上，其中形成該半導體裝置結構包括：形成一隔離結構於該晶圓之該邊緣區域中；形成一閘極堆疊結構於該晶圓之邊緣區域之上；形成複數個閘極間隙壁於該閘極堆疊結構之側壁上；在閘極間隙壁之下摻雜該晶圓，以形成複數個摻雜區域；以及成長一源極/汲極應力結構(source/drain stressor structure)介於該些摻雜區域與該隔離結構之間，其中該源極/汲極應力結構包括一蓋層及一應力層，其中該蓋層沿著(311)及(111)之晶面方向(crystal orientations)成長，及其中該應力層的一部分沿著(311)及(111)之晶面方向成長。
  7. 如申請專利範圍第6項所述之半導體裝置結構之形成方法，其中成長該源極/汲極應力結構包括： 蝕刻該晶圓，以形成一凹口於該晶圓中；成長該應力層於該凹口中；以及成長該蓋層於該應力層之上。
  8. 如申請專利範圍第7項所述之半導體裝置結構之形成方法，其中成長該蓋層於該應力層之上包括：藉由一選擇性磊晶成長(selective epitaxial growth,SEG)製程成長一矽鍺(SiGe)應力層於該凹口中，其中控制該選擇性磊晶成長(selective epitaxial growth,SEG)製程，以符合方程式(I)：邊緣區域-E/D=氯化氫(HCl source)的流速/矽源(Si source)與鍺源(Ge source)之流速總和---(I)；其中該邊緣區域-E/D值之範圍為約0.2至約0.8。
  9. 如申請專利範圍第7項所述之半導體裝置結構之形成方法，其中成長該蓋層於該應力層之上包括：形成該蓋層於該應力層之上沿著(311)及(111)晶面方向(crystal orientations)成長。
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