CN103295964B - 基于混合晶向soi及沟道应力的器件系统结构及制备方法 - Google Patents

基于混合晶向soi及沟道应力的器件系统结构及制备方法 Download PDF

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CN103295964B
CN103295964B CN201210046230.2A CN201210046230A CN103295964B CN 103295964 B CN103295964 B CN 103295964B CN 201210046230 A CN201210046230 A CN 201210046230A CN 103295964 B CN103295964 B CN 103295964B
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voltage device
soi
mixed crystal
silicon layer
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CN103295964A (zh
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卞剑涛
狄增峰
张苗
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Shanghai Institute of Microsystem and Information Technology of CAS
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Abstract

本发明提供一种基于混合晶向SOI及沟道应力的器件系统结构及制备方法。根据本发明的制备方法，首先制备（100）/（110）全局混晶SOI结构；接着，在全局混晶SOI结构上依次外延弛豫的锗硅层和应变硅层后，再形成（110）外延图形窗口，并在（110）外延图形窗口处外延（110）硅层及非弛豫的锗硅层后，使图形化混晶SOI结构表面平坦化，接着再形成隔离器件的隔离结构，最后在（110）衬底部分制备P型高压器件结构、在（100）衬底部分制备N型高压器件结构和/或低压器件结构，由此可有效提高各器件的载流子迁移率，改善高压器件的Rdson，提高各器件性能，有利于进一步提高集成度、降低功耗。

Description

基于混合晶向SOI及沟道应力的器件系统结构及制备方法
技术领域
本发明涉及本导体领域，特别是涉及一种基于混合晶向SOI及沟道应力的器件系统结构及制备方法。
背景技术
高压器件与高压集成工艺在汽车电子、LED驱动电路、PDP驱动等领域有着广泛的应用和大量的需求。BCD工艺是最主要的高压集成工艺，其中横向扩散金属氧化物半导体(LDMOS)是常用的集成高压器件，这类技术通常采用体硅和SOI衬底材料，在100V以上工艺中为了解决隔离问题，则常采用SOI衬底材料。虽然人们更多关心N-LDMOS，然而，与MOS器件一样，P-LDMOS也是高压MOS器件中重要的组成部分，其在PDP驱动等领域中有着重要的应用。目前，与N-LDMOS相比，在相同击穿电压(BV)情况下，P-LDMOS的Rdson总要高出一倍甚至更多，最主要的原因是由于受空穴迁移率的限制，其Ion小于N-LDMOS，为此希望提供一种新的衬底材料、并通过引入沟道应力，来提高载流子迁移率，改善器件Rdson，提高器件性能，以便有利于进一步提高集成度、降低功耗。
发明内容
鉴于以上所述现有技术的缺点，本发明的目的在于提供一种基于混合晶向SOI及沟道应力的器件系统结构制备方法，以制备出N型高压器件和/或低压器件、以及P型高压器件结构。
本发明的目的在于提供一种基于混合晶向SOI及沟道应力的器件系统结构，以提高各器件的载流子迁移率及改善高压器件的Rdson。
为实现上述目的及其他相关目的，本发明提供一种基于混合晶向SOI及沟道应力的器件系统结构制备方法，其至少包括：
1)制备(100)/(110)全局混晶SOI结构；
2)在所述全局混晶SOI结构上依次外延弛豫的锗硅层和应变硅层；
3)在具有弛豫的锗硅层和应变硅层的结构上形成(110)外延图形窗口；
4)在所述(110)外延图形窗口处依次选择性外延生长(110)硅层及非弛豫的锗硅层，并使外延锗硅层后的图形化混晶SOI结构表面平坦化；
5)在外延锗硅层后的图形化混晶SOI结构上形成隔离器件的隔离结构；以及
6)在具有隔离结构的全局混晶SOI结构的(110)衬底部分制备P型高压器件结构、在(100)衬底部分制备N型高压器件结构和/或低压器件结构，并去除N型高压器件结构的漂移区和漏区的锗硅和应变硅及P型高压器件结构的漂移区和漏区的锗硅。
本发明还提供另一种基于混合晶向SOI及沟道应力的器件系统结构制备方法，其至少包括：
1)制备(110)/(100)全局混晶SOI结构；
2)在所述全局混晶SOI结构上外延非弛豫的锗硅层；
3)在具有非弛豫的锗硅层上形成(100)外延图形窗口；
4)在所述(100)外延图形窗口处依次选择性外延生长弛豫的锗硅层和应变硅层，并使外延应变硅层后的图形化混晶SOI结构表面平坦化；
5)在外延应变硅层的图形化混晶SOI结构上形成隔离器件的隔离结构；
6)在具有隔离结构的图形化混晶SOI结构的(110)衬底部分制备P型高压器件结构、在(100)衬底部分制备N型高压器件结构和/或低压器件结构，并去除N型高压器件结构的漂移区和漏区的锗硅和应变硅及P型高压器件结构的漂移区和漏区的锗硅。
本发明提供一种基于混合晶向SOI及沟道应力的器件系统结构，其至少包括：
形成于(100)/(110)混晶SOI结构的(110)衬底部分、且具有锗硅沟道的P型高压器件结构；
形成于(100)/(110)＞混晶SOI结构的(100)衬底部分、且具有应变硅沟道的N型高压器件结构和/或低压器件结构；以及
隔离各器件的隔离结构。
本发明还提供一种基于混合晶向SOI及沟道应力的器件系统结构，其至少包括：
形成于(110)/(100)混晶SOI结构的(110)衬底部分、且具有锗硅沟道的P型高压器件结构；
形成于(110)/(100)混晶SOI结构的(100)衬底部分、且具有应变硅沟道的N型高压器件结构和/或低压器件结构；以及
隔离各器件的隔离结构。
如上所述，本发明具有以下有益效果：能有效提高载流子迁移率，改善高压器件的Rdson，提高器件的性能，有利于进一步提高集成度、降低功耗。
附图说明
图1-图6显示为本发明的一种基于混合晶向SOI及沟道应力的器件系统结构制备方法的流程图。
图7-图12显示为本发明的另一种基于混合晶向SOI及沟道应力的器件系统结构制备方法的流程图。
图13显示为电子和空穴迁移率示意图。
图14a至14e显示为高压器件所包含的沟道结构的形状示意图。
具体实施方式
以下由特定的具体实施例说明本发明的实施方式，熟悉此技术的人士可由本说明书所揭露的内容轻易地了解本发明的其他优点及功效。
请参阅图1至图14e。须知，本说明书所附图式所绘示的结构、比例、大小等，均仅用以配合说明书所揭示的内容，以供熟悉此技术的人士了解与阅读，并非用以限定本发明可实施的限定条件，故不具技术上的实质意义，任何结构的修饰、比例关系的改变或大小的调整，在不影响本发明所能产生的功效及所能达成的目的下，均应仍落在本发明所揭示的技术内容得能涵盖的范围内。同时，本说明书中所引用的如“上”、“下”、“左”、“右”、“中间”及“一”等的用语，亦仅为便于叙述的明了，而非用以限定本发明可实施的范围，其相对关系的改变或调整，在无实质变更技术内容下，当亦视为本发明可实施的范畴。
实施例一：
如图所示，本发明提供一种基于混合晶向SOI及沟道应力的器件系统结构制备方法，其包括以下步骤：
第一步：制备(100)/(110)全局混晶SOI结构。例如，采用常规制程制备(100)/(110)全局混晶SOI结构，如图1所示，该(100)/(110)全局混晶SOI结构包括：(100)硅衬底、埋氧层及(110)顶层硅。
第二步：在所述全局混晶SOI结构上依次外延弛豫的锗硅层和应变硅层。例如，如图2所示，在图1所示的全局混晶SOI结构上依次外延弛豫的锗硅层和应变硅层。
第三步：在具有弛豫的锗硅层和应变硅层的结构上形成(110)外延图形窗口。例如，如图3所示，采用光刻、腐蚀等工艺在图2所示的全局混晶SOI结构上制备用于外延(110)硅的(110)外延图形窗口，并在图形侧壁形成氮化硅侧墙(SiN Spacer)保护结构。
第四步：在所述(110)外延图形窗口处依次选择性外延生长(110)硅层及非弛豫的锗硅层，并使外延锗硅层后的图形化混晶SOI结构表面平坦化。如图4所示，在所述(110)外延图形窗口处依次选择性选择性外延生长(110)硅和10％～20％的锗硅，控制锗硅厚度使其不弛豫，并采用化学机械抛光(CMP)来实现外延后的图形化混晶SOI结构表面的平坦化。
第五步：在外延锗硅层后的图形化混晶SOI结构上形成隔离器件的隔离结构。例如，如图5所示，在外延锗硅层后的结构上形成STI隔离沟槽，槽内用二氧化硅填充并CMP形成浅槽隔离(STI)结构。
第六步：在具有隔离结构的图形化混晶SOI结构的(110)衬底部分制备P型高压器件结构、在(100)衬底部分制备N型高压器件结构和/或低压器件结构，并去除N型高压器件结构的漂移区和漏区的锗硅和应变硅及P型高压器件结构的漂移区和漏区的锗硅。
例如，如图6所示，采用BCD工艺，在具有隔离结构的全局混晶SOI结构的(110)衬底部分制备P-LDMOS，在(100)衬底部分制备N-LDMOS以及低压NMOS和PMOS，并去除N-LDMOS的漂移区和漏区的锗硅和应变硅及P-LDMOS的漂移区和漏区的锗硅。
优选地，采用凹陷LOCOS(Recess LOCOS)工艺去除N-LDMOS的漂移区和漏区的锗硅和应变硅、以及P-LCMOS漂移区和漏区的锗硅。
需要说明的是，本领域技术人员应该理解，当制备的低压器件结构包括多个时，各低压器件结构之间的隔离结构可采用LOCOS隔离结构及STI隔离结构中的一种或两种，在此不再详述。
基于上述制备方法，制备出的基于混合晶向SOI及沟道应力的器件系统结构如图6所示，该基于混合晶向SOI及沟道应力的器件系统结构包括：形成于(100)/(110)混晶SOI结构的(110)衬底部分、且具有锗硅沟道的P型高压器件结构，例如，P-LDMOS；形成于(100)/(110)混晶SOI结构的(100)衬底部分、且具有应变硅沟道的N型高压器件结构，例如，N-LDMOS；形成于(100)/(110)混晶SOI结构的(100)衬底部分、且具有应变硅沟道的低压器件结构，例如，低压NMOS和PMOS；以及隔离各器件的隔离结构，例如，STI隔离沟槽。
优选地，制备的P型或N型高压器件各自所包含的沟道的结构可以呈圆环形(如图14a所示)、跑道形环状(如图14b所示)、矩形环状(如图14c所示)、或直条状(如图14d及14e所示)等；更为优选地，(110)硅衬底上的P型高压器件的直条状沟道和/或环状沟道的直道部分沿<110>晶向。
实施例二：
如图所示，本发明提供的另一种基于混合晶向SOI及沟道应力的器件系统结构制备方法，其包括以下步骤：
第一步：制备(110)/(100)混晶SOI结构。例如，采用常规制程制备(110)/(100)全局混晶SOI结构，如图7所示，该(110)/(100)全局混晶SOI结构包括：(100)硅衬底、埋氧层及(110)顶层硅。
第二步：在所述全局混晶SOI结构上外延非弛豫的锗硅层。例如，如图8所示，在图7所示的全局混晶SOI结构上外延非弛豫的锗硅层。
第三步：在具有非弛豫的锗硅层上形成(100)外延图形窗口。例如，如图9所示，采用光刻、腐蚀等工艺在图8所示的全局混晶SOI结构制备用于外延(100)硅的(100)外延图形窗口，并在图形侧壁形成氮化硅侧墙(SiN Spacer)保护结构。
第四步：在所述(100)外延图形窗口处依次选择性外延生长弛豫的锗硅层和应变硅层，并使外延应变硅层后的图形化混晶SOI结构表面平坦化。如图10所示，在所述(100)外延图形窗口处弛豫的锗硅层和应变硅层，并采用化学机械抛光(CMP)来实现外延后的图形化混晶SOI结构表面的平坦化。
第五步：在外延应变硅层的图形化混晶SOI结构上形成隔离器件的隔离结构。例如，如图11所示，在外延应变硅层后的结构上形成STI隔离沟槽，槽内用二氧化硅填充并CMP形成浅槽隔离(STI)结构。
第六步：在具有隔离结构的图形化混晶SOI结构的(110)衬底部分制备P型高压器件结构、在(100)衬底部分制备N型高压器件结构和/或低压器件结构，并去除N型高压器件结构的漂移区和漏区的锗硅和应变硅及P型高压器件结构的漂移区和漏区的锗硅。
例如，如图12所示，采用BCD工艺，在具有隔离结构的全局混晶SOI结构的(110)衬底部分制备P-LDMOS，在(100)衬底部分制备N-LDMOS以及低压NMOS和PMOS，并去除N-LDMOS的漂移区和漏区的锗硅和应变硅及P-LDMOS的漂移区和漏区的锗硅。
需要说明的是，本领域技术人员应该理解，当制备的低压器件结构包括多个时，各低压器件结构之间的隔离结构可采用LOCOS隔离结构及STI隔离结构中的一种或两种，在此不再详述。
基于上述制备方法，制备出的基于混合晶向SOI及沟道应力的器件系统结构如图12所示，该基于混合晶向SOI及沟道应力的器件系统结构包括：形成于(110)/(100)混晶SOI结构的(110)衬底部分、且具有锗硅沟道的P型高压器件结构，例如，P-LDMOS；形成于(110)/(100)全局混晶SOI结构的(100)衬底部分、且具有应变硅沟道的N型高压器件结构，例如，N-LDMOS；形成于(110)/(100)混晶SOI结构的(100)衬底部分、且具有应变硅沟道的低压器件结构，例如，低压NMOS和PMOS；以及隔离各器件的隔离结构，例如，STI隔离沟槽。
优选地，制备的P型或N型高压器件各自所包含的沟道的结构可以呈圆环形(如图14a所示)、跑道形环状(如图14b所示)、矩形环状(如图14c所示)、或直条状(如图14d及14e所示)等；更为优选地，(110)硅衬底上的P型高压器件的直条状沟道和/或环状沟道的直道部分沿<110>晶向。
由上可见，本发明的基于混合晶向SOI及沟道应力的器件系统结构制备方法基于(100)硅衬底在<110>晶向具有最大的电子迁移率；而(110)硅衬底在<110>晶向具有最大的空穴迁移率，且是(100)硅衬底在<110>晶向空穴迁移率的2倍以上，同时(110)硅衬底在<100>晶向空穴迁移率也有明显的提高，具体如图13所示；故，本发明将N型高压器件制备于(100)衬底上，P型高压器件制备于(110)衬底上，此外，将低压器件也制备在(100)衬底上，与现有BCD工艺兼容，这样后续就可以直接将现有BCD工艺的直接转移，易于达到产业化和实用化的目的。此外，通过采用锗硅和/或应变硅材料，对N-LDMOS、P-LDMOS的沟道及低压器件的沟道引入应力，在保证击穿电压不变的前提下，进一步提高载流子迁移率，可使N-LDMOS和P-LDMOS的Rdson进一步减小。与现有(100)衬底上制备的P-LDMOS相比，采用混晶SOI实现的该高压集成技术，P-LDMOS的Rdson将至少减小1倍；另外，由于实施例一的(100)衬底部分没有埋氧层的存在，可减小P-LDMOS的自热效应和背栅效应；实施例二的(110)衬底部分没有埋氧层的存在，可减小N-LDMOS的自热效应和背栅效应。
此外，需要说明的是，本领域技术人员应该理解，上述各实施例仅仅只是列示，而非对本发明的限制，事实上，所制备的器件系统结构可仅仅包含P型高压器件、N型高压器件、P型和N型低压器件等中的一种或几种，在此不再详述。
综上所述，本发明的基于混合晶向SOI及沟道应力的器件系统结构制备方法基于混晶SOI及沟道应力来制备P型、N型高压器件和/或低压器件，可有效提高各器件的载流子迁移率，改善高压器件的Rdson，提高各器件的性能，有利于进一步提高集成度、降低功耗。所以，本发明有效克服了现有技术中的种种缺点而具高度产业利用价值。
上述实施例仅例示性说明本发明的原理及其功效，而非用于限制本发明。任何熟悉此技术的人士皆可在不违背本发明的精神及范畴下，对上述实施例进行修饰或改变。因此，举凡所属技术领域中具有通常知识者在未脱离本发明所揭示的精神与技术思想下所完成的一切等效修饰或改变，仍应由本发明的权利要求所涵盖。

Claims (8)

1.一种基于混合晶向SOI及沟道应力的器件系统结构制备方法，其特征在于，所述基于混合晶向SOI及沟道应力的器件系统结构制备方法至少包括：
a)制备(100)/(110)全局混晶SOI结构；
b)在所述全局混晶SOI结构上依次外延弛豫的锗硅层和应变硅层；
c)在具有弛豫的锗硅层和应变硅层的结构上形成(110)外延图形窗口；
d)在所述(110)外延图形窗口处依次选择性外延生长(110)硅层及非弛豫的锗硅层，并使外延锗硅层后的图形化混晶SOI结构表面平坦化；
e)在外延锗硅层后的图形化混晶SOI结构上形成隔离器件的隔离结构；
f)在具有隔离结构的图形化混晶SOI结构的(110)衬底部分制备P型高压器件结构、在(100)衬底部分制备N型高压器件结构和/或低压器件结构，并去除N型高压器件结构的漂移区和漏区的锗硅和应变硅及P型高压器件结构的漂移区和漏区的锗硅。
2.根据权利要求1所述的基于混合晶向SOI及沟道应力的器件系统结构制备方法，其特征在于：采用硅局部氧化(LOCOS)工艺去除N型高压器件结构的漂移区和漏区的锗硅和应变硅及P型高压器件结构的漂移区和漏区的锗硅。
3.根据权利要求1所述的基于混合晶向SOI及沟道应力的器件系统结构制备方法，其特征在于：当所述低压器件结构包括多个时，各低压器件结构之间的隔离结构包括LOCOS隔离结构和/或STI隔离结构。
4.根据权利要求1所述的基于混合晶向SOI及沟道应力的器件系统结构制备方法，其特征在于：高压器件之间的隔离结构以及高压与低压器件之间的隔离结构均包括STI隔离结构。
5.一种基于混合晶向SOI及沟道应力的器件系统结构制备方法，其特征在于，所述基于混合晶向SOI及沟道应力的器件系统结构制备方法至少包括：
a)制备(110)/(100)全局混晶SOI结构；
b)在所述全局混晶SOI结构上外延非弛豫的锗硅层；
c)在具有非弛豫的锗硅层上形成(100)外延图形窗口；
d)在所述(100)外延图形窗口处依次选择性外延生长弛豫的锗硅层和应变硅层，并使外延应变硅层后的图形化混晶SOI结构表面平坦化；
e)在外延应变硅层的图形化混晶SOI结构上形成隔离器件的隔离结构；
f)在具有隔离结构的图形化混晶SOI结构的(110)衬底部分制备P型高压器件结构、在(100)衬底部分制备N型高压器件结构和/或低压器件结构，并去除N型高压器件结构的漂移区和漏区的锗硅和应变硅及P型高压器件结构的漂移区和漏区的锗硅。
6.根据权利要求5所述的基于混合晶向SOI及沟道应力的器件系统结构制备方法，其特征在于：采用硅局部氧化(LOCOS)工艺去除N型高压器件结构的漂移区和漏区的锗硅和应变硅及P型高压器件结构的漂移区和漏区的锗硅。
7.根据权利要求5所述的基于混合晶向SOI及沟道应力的器件系统结构制备方法，其特征在于：当所述低压器件结构包括多个时，各低压器件结构之间的隔离结构包括LOCOS隔离结构和/或STI隔离结构。
8.根据权利要求5所述的基于混合晶向SOI及沟道应力的器件系统结构制备方法，其特征在于：高压器件之间的隔离结构以及高压与低压器件之间的隔离结构均包括STI隔离结构。
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