CN104659077A - 非平面SiGe沟道PFET - Google Patents

非平面SiGe沟道PFET Download PDF

Info

Publication number
CN104659077A
CN104659077A CN201410674393.4A CN201410674393A CN104659077A CN 104659077 A CN104659077 A CN 104659077A CN 201410674393 A CN201410674393 A CN 201410674393A CN 104659077 A CN104659077 A CN 104659077A
Authority
CN
China
Prior art keywords
germanium concentration
channel layer
stress inducing
inducing moiety
simple stress
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN201410674393.4A
Other languages
English (en)
Other versions
CN104659077B (zh
Inventor
冯家馨
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Taiwan Semiconductor Manufacturing Co TSMC Ltd
Original Assignee
Taiwan Semiconductor Manufacturing Co TSMC Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Taiwan Semiconductor Manufacturing Co TSMC Ltd filed Critical Taiwan Semiconductor Manufacturing Co TSMC Ltd
Publication of CN104659077A publication Critical patent/CN104659077A/zh
Application granted granted Critical
Publication of CN104659077B publication Critical patent/CN104659077B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1025Channel region of field-effect devices
    • H01L29/1029Channel region of field-effect devices of field-effect transistors
    • H01L29/1033Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1025Channel region of field-effect devices
    • H01L29/1029Channel region of field-effect devices of field-effect transistors
    • H01L29/1033Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
    • H01L29/1054Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with a variation of the composition, e.g. channel with strained layer for increasing the mobility
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312Gate electrodes for field effect devices
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007Multistep manufacturing processes
    • H01L29/66075Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409Unipolar field-effect transistors
    • H01L29/66477Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007Multistep manufacturing processes
    • H01L29/66075Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409Unipolar field-effect transistors
    • H01L29/66477Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66787Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
    • H01L29/66795Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/7842Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
    • H01L29/7848Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate the means being located in the source/drain region, e.g. SiGe source and drain
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/785Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/786Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78696Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007Multistep manufacturing processes
    • H01L29/66075Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409Unipolar field-effect transistors
    • H01L29/66477Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568Lateral single gate silicon transistors
    • H01L29/66613Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation
    • H01L29/66628Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation recessing the gate by forming single crystalline semiconductor material at the source or drain location
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007Multistep manufacturing processes
    • H01L29/66075Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409Unipolar field-effect transistors
    • H01L29/66477Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568Lateral single gate silicon transistors
    • H01L29/66636Lateral single gate silicon transistors with source or drain recessed by etching or first recessed by etching and then refilled

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Manufacturing & Machinery (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Thin Film Transistor (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

本发明提供了用于制造半导体器件结构的系统和方法。示例性半导体器件结构包括由锗化合物形成的沟道层,沟道层具有锗浓度B且形成在具有锗浓度A的半导体衬底上,其中衬底的锗浓度A小于沟道层的锗浓度B。该结构还包括为使沟道层与金属栅极分隔而形成的覆盖层,该覆盖层具有锗浓度C,沟道层的锗浓度B大于覆盖层的锗浓度C。本发明还公开非平面SiGe沟道PFET。

Description

非平面SiGe沟道PFET
技术领域
本发明所描述的技术总体上与半导体器件结构相关,并且更具体地与多层结构相关。
背景技术
非平面晶体管结构提供一种在小占用面积中实现高器件性能的手段。这样的结构的制造经常被用于生成这些结构的物质的材料属性所限制。如本文所描述,在非平面晶体管结构(诸如三栅极、finFET和全环栅结构)中的沟道材料工程提供了实现高迁移率和提高晶体管性能的机会。
发明内容
根据本文描述的教导,提供了用于制造半导体器件结构的系统和方法。示例性半导体器件结构包括由锗化合物形成的沟道层,沟道层具有锗浓度B且形成在具有锗浓度A的半导体衬底上,其中衬底的锗浓度A小于沟道层的锗浓度B。该结构还包括使沟道层与金属栅极分隔而形成的覆盖层,该覆盖层具有锗浓度C,沟道层的锗浓度B大于覆盖层的锗浓度C。
优选地,半导体器件结构还包括:单轴应力诱导部分化合物,具有锗浓度D且在所述半导体衬底之上且邻近所述沟道层形成,所述单轴应力诱导部分的锗浓度D大于或等于所述沟道层的锗浓度B,并且所述单轴应力诱导部分的锗浓度D大于所述衬底的锗浓度A。
优选地,所述单轴应力诱导部分配置为用作场效应晶体管的源极或漏极,并且其中所述金属栅极配置为用作所述场效应晶体管的栅极。
优选地,所述场效应晶体管配置为使用VDD>0.6V运行。
优选地,半导体器件结构还包括第二单轴应力诱导部分,所述第二单轴应力诱导部分具有锗浓度E且在所述半导体衬底之上且邻近所述沟道层处形成,所述第二单轴应力诱导部分的锗浓度E大于或等于所述沟道层的锗浓度B,并且所述第二单轴应力诱导部分的锗浓度E大于所述衬底的锗浓度A。
优选地,所述单轴应力诱导部分配置为用作场效应晶体管的源极,并且其中所述第二单轴应力诱导部分配置为用作所述场效应晶体管的漏极。
优选地,所述单轴应力诱导部分的锗浓度D是渐变的,以使所述单轴应力诱导部分的顶部处的锗浓度D1大于所述单轴应力诱导部分的底部处的锗浓度D2
优选地,当以百分比表示时,所述单轴应力诱导部分的底部处的锗浓度D2减去所述衬底的锗浓度A小于50%。
优选地,所述衬底的锗浓度A为约30%,所述沟道层的锗浓度B为约60%,所述覆盖层的锗浓度C为约0%,以及所述单轴应力诱导部分的锗浓度大于或等于60%。
优选地,所述半导体衬底由硅形成,并具有基本上为零的锗浓度A。
优选地,所述覆盖层由硅形成,并具有基本上为零的锗浓度C。
优选地,半导体器件结构还包括:形成为使得所述覆盖层与所述金属栅极进一步分隔的氧化物介电层。
优选地,当以百分比表示时,所述沟道层的锗浓度B减去所述衬底的锗浓度A小于50%。
优选地,所述金属栅极包括底面并且所述沟道层包括底面,其中所述沟道层的底面从所述金属栅极的底面垂直地偏移。
优选地,所述沟道层的底面比所述金属栅极的底面离所述半导体器件结构的基底更远。
优选地,所述沟道层的底面离所述半导体器件结构的基底比所述金属栅极的底面远1nm至5nm。
在一个实施例中,提供了一种用于制造半导体器件结构的方法。在具有锗浓度A的半导体衬底上形成具有锗浓度B的锗化合物的沟道层,衬底的锗浓度A小于沟道层的锗浓度B。形成覆盖层以使沟道层与金属栅极分隔,覆盖层具有锗浓度C,沟道层的锗浓度B大于覆盖层的锗浓度C。
优选地,所述方法还包括:在所述半导体衬底之上且邻近所述沟道层形成具有锗浓度D的单轴应力诱导部分,所述单轴应力诱导部分的锗浓度D大于或等于所述沟道层的锗浓度B,并且所述单轴应力诱导部分的锗浓度D大于所述衬底的锗浓度A。
优选地,所述单轴应力诱导部分的锗浓度D是渐变的,以便所述单轴应力诱导部分的顶部处的锗浓度D1大于所述单轴应力诱导部分的底部处的锗浓度D2
优选地,当以百分比表示时,所述单轴应力诱导部分的底部处的锗浓度D2减去所述衬底的锗浓度A小于50%。
附图说明
图1是沿着沟道方向示出了包括含锗沟道层的多层半导体器件结构的图。
图2是沿着宽度方向示出了包括含锗沟道层的多层半导体器件结构的图。
图3是描述制造半导体器件结构的方法的流程图。
具体实施方式
图1图示了示出包括含锗沟道层的多层半导体器件结构的示例性图。由诸如Ge或SiGe的材料制成的含锗沟道层的利用通过引入比使用硅沟道的传统系统较高应力、改进的量子阱限制、以及较高的本征迁移率提供用于改进PFET驱动电流增强的机制。图1是具有含锗沟道层的这样的半导体器件结构100的沿着沟道的视图。半导体材料形成衬底102,相继的结构施加在衬底102上。在不同实施中,衬底102呈现各种形式,诸如硅衬底或诸如含有浓度为A的锗(例如,A%锗)的硅锗的含锗物质。第二半导体材料用以在衬底102顶部上形成沟道层104。沟道层104由锗化合物形成,并且锗浓度为B。在一个实施例中,衬底的锗浓度A小于沟道层的锗浓度B(即,B>A)。在另一个实施例中,衬底的锗浓度A等于沟道层的锗浓度B。
理想的是,在一个实施例中,衬底的锗浓度A小于但不是太小于沟道层B的锗浓度。已经发现A与B之间的显著差异增加了某些实施中某些晶体缺陷的可能性。为了有助于避免这些缺陷,选择衬底的锗浓度A与沟道层的锗浓度B,以使得当这些浓度以百分比表示时沟道层的锗浓度B减去衬底的锗浓度A小于50%(即,B-A<50%)。
图1还示出了所形成的覆盖层106将沟道层104与金属栅极108隔离。覆盖层由锗浓度为C的含锗物质形成。为了限制沟道层中空穴,在一个实施例中,覆盖层被形成为使得沟道层的锗浓度B大于覆盖层的锗浓度C(即,B>C)。覆盖层制造成锗含量低的薄层,包括将覆盖层制造成锗浓度基本为零(即,<5%)的基本硅层。在某些实施例中额外的层介于上述层之间,所述额外的层诸如由包括高k氧化物电介质的氧化物电介质形成的介电层110。
为了阐述诸如晶体管的半导体结构,将某些单轴应力诱导部分引入半导体器件结构中。例如,在特定的实施方式中,这些单轴应力诱导部分用作制造的晶体管的源极和漏极部分。图1以112、114示出了两个这样的部分。单轴应力诱导部分112、114形成在半导体衬底102之上并且邻近沟道层104。为了对沟道层104提供压缩应力,制造一个或两个单轴应力诱导部分112、114以便使其具有大于或等于沟道层的锗浓度B的锗浓度D(即,D≥B)。在特定的实施方式中,单轴应力诱导部分的锗浓度D也大于衬底的锗浓度A(即,D>A)。然而,为了避免单轴应力诱导部分112、114和衬底102之间的较大的晶格失配,单轴应力诱导部分的锗浓度D被选择为使得当表述为百分比时单轴应力诱导部分的锗浓度D减去衬底的锗浓度A小于50%(即,D–A<50%)。
图1示出了被构造成作为晶体管来工作的半导体器件结构100。因此,具有锗浓度D的第一单轴应力诱导部分112构造成以场效应晶体管的源极来工作,以及具有锗浓度E(在特定实施方式中等于D)的第二单轴应力诱导部分114构造成以场效应晶体管的漏极来工作。将金属栅极108配置为用作场效应晶体管的栅极,其中,场效应晶体管表现出所期望的特定特性,诸如在特定实施方式中使用VDD>0.6V正常运行。
在特定实施方式中,将单轴应力诱导部分112、114改变为其他方式。例如,在一个实施例中,单轴应力诱导部分112、114的锗浓度从顶部至底部渐变,从而使得单轴应力诱导部分在顶部处的锗浓度D1大于其在底部处的锗浓度D2。在这样的实施方式中,在顶部实施更高的锗浓度D1,同时限制在单轴应力诱导部分112、114与衬底102界面处的较大的晶体失配(例如,选择锗浓度从而使得D2–A<50%)。
大量半导体器件结构可以设计成实施本文描述的特定的设计标准。在一个实例中,将衬底102的锗浓度A选择为30%,将沟道层104的锗浓度B选择为60%,将覆盖层106的锗浓度C选择为0%,并且将单轴应力诱导部分112、114的锗浓度D、E选择为在60%和100%之间。可以改变这些浓度而仍然落在本发明的范围内,本发明的范围包括衬底102的锗浓度A是0%的实施方式。
图2是沿着宽度方向示出包括含锗沟道层的多层半导体器件结构的示意图。半导体器件结构100包括由锗化合物形成的具有锗浓度B的沟道层104,沟道层104在具有锗浓度A的衬底102上形成,其中,锗浓度A小于沟道层的锗浓度B。覆盖层106形成为将沟道层104与金属栅极108分隔开,覆盖层106具有锗浓度C,其中,沟道层的锗浓度B大于覆盖层的锗浓度C。在图2中示出的半导体器件结构包括在覆盖层106和金属栅极108之间具有高k/氧化物介电层110的额外的层(该额外的层包括高k/氧化物介电层110)以及制造于衬底102和金属栅极108之间的浅沟槽隔离(STI)氧化物层116。
在一个实施例中,制造半导体器件以使得金属栅极108的底面118不与沟道层104的底面120垂直对准。通过改变衬底缓冲区124的尺寸实施的偏移X可以被调整以改变特定的半导体器件结构参数。例如,如图2所示,当X为正时,沟道层的底面120相比于金属栅极108的底面118远离半导体器件结构100的基底122,由于有效宽度减小,ION降低,而当X为负时,观察到泄漏电流增加。在一个实施例中,沟道层104的底面120相比于金属栅极108的底面118远离半导体器件结构100的基底122且偏移1至5nm。根据系统需要改变这种偏移,诸如偏移在+5nm至-5nm的数值内。
图3是示出制造半导体器件结构的方法的流程图。在302中,在具有锗浓度A的半导体衬底上形成具有锗浓度B的锗化合物的沟道层,衬底的锗浓度A小于沟道层的锗浓度B。在304中,形成覆盖层以将沟道层与金属栅极分隔开,覆盖层具有锗浓度C,沟道层的锗浓度B大于覆盖层的锗浓度C。在306,在半导体衬底之上并且邻近沟道层形成具有锗浓度D的单轴应力诱导部分,单轴应力诱导部分的锗浓度D大于或等于沟道层的锗浓度B,并且单轴应力诱导部分的锗浓度D大于衬底的锗浓度A。
该撰写的说明书使用实例来公开本发明,包括最佳模式,并且还使得本领域普通技术人员能够制造和使用本发明。本发明的可专利范围可以包括本领域普通技术人员容易想到的其他实例。本领域普通技术人员将认识到需在不要一个或多个具体细节的情况下可以实践各个实施例,或利用其他替代形式和/或额外的方法、材料或部件来实践各个实施例。可以不具体示出或描述已知的结构、材料或操作以避免模糊本发明的各个实施例的各方面。在图中示出的各个实施例为说明性的实例代表并且不必按比例绘制。在一个或多个实施例中,可以以任何合适的方式对特定的部件、结构、材料或特征组合。在其他实施例中可以包括各个额外的层和/或结构和/或可以省略描述的部件。又可以以更有助于理解本发明的方式将各个操作描述为多个离散的操作。然而,描述的顺序不应当被解释为暗示这些操作必须为顺序依赖的。特别地,无需以示出的顺序实施这些操作。相比于描述的实施例,可以以不同的顺序、连续地或同时地实施本文描述的操作。可以实施和/或描述各个额外的操作。在额外的实施例中可以省略操作。
该撰写的说明书和权利要求可以包括诸如左、右、顶部、底部、在…上方、在……下方、上、下、第一、第二等的术语,这些术语仅用于描述的目的并且不被解释为限制意义。例如,代表相对垂直位置的术语可以表示其中衬底或集成电路的器件侧(或有源表面)是衬底的“顶”面;事实上,衬底可以处于任何方位,从而使得在标准陆地参考框架中,衬底的“顶”侧可以低于衬底的“底”侧并且仍然可落在术语“顶部”的含义内。如本文(包括权利要求中)中使用的术语“在…上”可以不指示在第二层上的第一层是直接位于第二层上并且立即与第二层接触,除非具体地陈述这种情形;在第一层和位于第一层上的第二层之间可以有第三层或其他结构。可以以多个位置和方位制造、使用或载运本文描述的器件或物品的实施例。本领域普通技术人员应该意识到图中示出的各个部件的各种等效组合和替代。

Claims (10)

1.一种半导体器件结构,包括:
沟道层,由锗化合物形成,所述沟道层具有锗浓度B且形成在具有锗浓度A的半导体衬底上,所述衬底的锗浓度A小于所述沟道层的锗浓度B;
覆盖层,形成为使得所述沟道层与金属栅极分隔,所述覆盖层具有锗浓度C,所述沟道层的锗浓度B大于所述覆盖层的锗浓度C。
2.根据权利要求1所述的半导体器件结构,还包括:
单轴应力诱导部分化合物,具有锗浓度D且在所述半导体衬底之上且邻近所述沟道层形成,所述单轴应力诱导部分的锗浓度D大于或等于所述沟道层的锗浓度B,并且所述单轴应力诱导部分的锗浓度D大于所述衬底的锗浓度A。
3.根据权利要求2所述的半导体器件结构,其中,所述单轴应力诱导部分配置为用作场效应晶体管的源极或漏极,并且其中所述金属栅极配置为用作所述场效应晶体管的栅极。
4.根据权利要求3所述的半导体器件结构,其中,所述场效应晶体管配置为使用VDD>0.6V运行。
5.根据权利要求3所述的半导体器件结构,还包括第二单轴应力诱导部分,所述第二单轴应力诱导部分具有锗浓度E且在所述半导体衬底之上且邻近所述沟道层处形成,所述第二单轴应力诱导部分的锗浓度E大于或等于所述沟道层的锗浓度B,并且所述第二单轴应力诱导部分的锗浓度E大于所述衬底的锗浓度A。
6.根据权利要求5所述的半导体器件结构,其中,所述单轴应力诱导部分配置为用作场效应晶体管的源极,并且其中所述第二单轴应力诱导部分配置为用作所述场效应晶体管的漏极。
7.根据权利要求2所述的半导体器件结构,其中,所述单轴应力诱导部分的锗浓度D是渐变的,以使所述单轴应力诱导部分的顶部处的锗浓度D1大于所述单轴应力诱导部分的底部处的锗浓度D2
8.根据权利要求7所述的半导体器件结构,其中,当以百分比表示时,所述单轴应力诱导部分的底部处的锗浓度D2减去所述衬底的锗浓度A小于50%。
9.根据权利要求2所述的半导体器件结构,其中,所述衬底的锗浓度A为约30%,所述沟道层的锗浓度B为约60%,所述覆盖层的锗浓度C为约0%,以及所述单轴应力诱导部分的锗浓度大于或等于60%。
10.一种制造半导体器件结构的方法,包括:
在具有锗浓度A的半导体衬底上形成具有锗浓度B的锗化合物的沟道层,所述衬底的锗浓度A小于所述沟道层的锗浓度B;
形成覆盖层以使所述沟道层与金属栅极分隔,所述覆盖层具有锗浓度C,所述沟道层的锗浓度B大于所述覆盖层的锗浓度C。
CN201410674393.4A 2013-11-20 2014-11-20 非平面SiGe沟道PFET Active CN104659077B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US14/084,925 2013-11-20
US14/084,925 US9425257B2 (en) 2013-11-20 2013-11-20 Non-planar SiGe channel PFET

Publications (2)

Publication Number Publication Date
CN104659077A true CN104659077A (zh) 2015-05-27
CN104659077B CN104659077B (zh) 2018-03-23

Family

ID=53172438

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201410674393.4A Active CN104659077B (zh) 2013-11-20 2014-11-20 非平面SiGe沟道PFET

Country Status (4)

Country Link
US (1) US9425257B2 (zh)
KR (1) KR101727368B1 (zh)
CN (1) CN104659077B (zh)
TW (1) TWI532183B (zh)

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR102395071B1 (ko) * 2015-05-14 2022-05-10 삼성전자주식회사 전계 효과 트랜지스터를 포함하는 반도체 소자
US10020317B2 (en) 2015-08-31 2018-07-10 Cypress Semiconductor Corporation Memory device with multi-layer channel and charge trapping layer
US9711648B1 (en) * 2016-08-09 2017-07-18 Globalfoundries Inc. Structure and method for CMP-free III-V isolation
US10141430B1 (en) * 2017-07-27 2018-11-27 Taiwan Semiconductor Manufacturing Co., Ltd. Fin structures with uniform threshold voltage distribution and method of making the same
US10431695B2 (en) 2017-12-20 2019-10-01 Micron Technology, Inc. Transistors comprising at lease one of GaP, GaN, and GaAs
US10818800B2 (en) * 2017-12-22 2020-10-27 Nanya Technology Corporation Semiconductor structure and method for preparing the same
US10825816B2 (en) 2017-12-28 2020-11-03 Micron Technology, Inc. Recessed access devices and DRAM constructions
US10734527B2 (en) 2018-02-06 2020-08-04 Micron Technology, Inc. Transistors comprising a pair of source/drain regions having a channel there-between
US10916633B2 (en) * 2018-10-23 2021-02-09 International Business Machines Corporation Silicon germanium FinFET with low gate induced drain leakage current
US11031291B2 (en) * 2018-11-28 2021-06-08 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor structure and method of forming the same
US11728383B2 (en) * 2020-09-25 2023-08-15 Applied Materials, Inc. Localized stressor formation by ion implantation

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1770470A (zh) * 2004-09-25 2006-05-10 三星电子株式会社 具有应变的硅沟道的场效应晶体管及其制造方法
US20070032009A1 (en) * 2002-06-07 2007-02-08 Amberwave Systems Corporation Semiconductor devices having strained dual channel layers
US20070164364A1 (en) * 2006-01-06 2007-07-19 Hirohisa Kawasaki Semiconductor device using sige for substrate and method for fabricating the same
CN101414632A (zh) * 2007-10-16 2009-04-22 台湾积体电路制造股份有限公司 鳍式场效应晶体管

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7045401B2 (en) 2003-06-23 2006-05-16 Sharp Laboratories Of America, Inc. Strained silicon finFET device
US7154118B2 (en) 2004-03-31 2006-12-26 Intel Corporation Bulk non-planar transistor having strained enhanced mobility and methods of fabrication
JP2007142408A (ja) 2005-11-14 2007-06-07 Samsung Electronics Co Ltd コンタクトタイプマスクパターンを用いたローカルダマシンFinFETSを製造する方法(METHODSOFFABRICATINGLOCALDAMASCENEFinFETSUSINGCONTACTTYPEMASKPATTERN)
US7679146B2 (en) 2006-05-30 2010-03-16 Semiconductor Components Industries, Llc Semiconductor device having sub-surface trench charge compensation regions
US8471244B2 (en) 2006-12-05 2013-06-25 Atmel Corporation Method and system for providing a metal oxide semiconductor device having a drift enhanced channel
US7759199B2 (en) * 2007-09-19 2010-07-20 Asm America, Inc. Stressor for engineered strain on channel
US7767560B2 (en) 2007-09-29 2010-08-03 Intel Corporation Three dimensional strained quantum wells and three dimensional strained surface channels by Ge confinement method
US8053299B2 (en) 2009-04-17 2011-11-08 Taiwan Semiconductor Manufacturing Company, Ltd. Method of fabrication of a FinFET element
US7993999B2 (en) 2009-11-09 2011-08-09 International Business Machines Corporation High-K/metal gate CMOS finFET with improved pFET threshold voltage
US8283653B2 (en) 2009-12-23 2012-10-09 Intel Corporation Non-planar germanium quantum well devices
DE102010064280B4 (de) * 2010-12-28 2012-08-30 GLOBALFOUNDRIES Dresden Module One Ltd. Liability Company & Co. KG Verfahren zur Verringerung der Defektraten in PFET-Transistoren, die ein Si/GE Halbleitermaterial aufweisen, durch Vorsehen einer graduellen Ge-Konzentration, und entsprechende PFET-Transistoren

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20070032009A1 (en) * 2002-06-07 2007-02-08 Amberwave Systems Corporation Semiconductor devices having strained dual channel layers
CN1770470A (zh) * 2004-09-25 2006-05-10 三星电子株式会社 具有应变的硅沟道的场效应晶体管及其制造方法
US20070164364A1 (en) * 2006-01-06 2007-07-19 Hirohisa Kawasaki Semiconductor device using sige for substrate and method for fabricating the same
CN101414632A (zh) * 2007-10-16 2009-04-22 台湾积体电路制造股份有限公司 鳍式场效应晶体管

Also Published As

Publication number Publication date
US9425257B2 (en) 2016-08-23
TW201521200A (zh) 2015-06-01
KR101727368B1 (ko) 2017-04-14
KR20150058089A (ko) 2015-05-28
TWI532183B (zh) 2016-05-01
CN104659077B (zh) 2018-03-23
US20150137268A1 (en) 2015-05-21

Similar Documents

Publication Publication Date Title
CN104659077A (zh) 非平面SiGe沟道PFET
US10115788B2 (en) Semiconductor devices with horizontal gate all around structure and methods of forming the same
CN104854703B (zh) 缩小尺寸的共振隧穿场效应晶体管
US20120193707A1 (en) High voltage multigate device and manufacturing method thereof
US20170005095A1 (en) Sandwich epi channel for device enhancement
DE112011105926T5 (de) Belastungskompensation in Transistoren
CN106784001A (zh) 一种场效应晶体管及其制作方法
CN103545372A (zh) 具有沟槽场板的FinFET
CN104835844B (zh) 鳍式场效应晶体管半导体装置及其制造方法
DE112013007050T5 (de) Tunnelfeldeffekttransistoren (TFET) mit undotierten Drainunterlappungs-Umwicklungsbereichen
KR20160099537A (ko) 완화된 기판이 없는 nmos 및 pmos 스트레인된 디바이스
CN103855009A (zh) 鳍结构制造方法
CN106062963A (zh) 晶体管中的应变补偿
CN103854981A (zh) 鳍结构制造方法
CN105679674A (zh) 使用重叠掩膜减少栅极高度变化的方法
US20140210009A1 (en) High voltage finfet structure
CN103811342A (zh) 鳍结构及其制造方法
CN103426756A (zh) 半导体器件及其制造方法
TWI591729B (zh) 雙閘極石墨烯場效電晶體及其製造方法
US20150001630A1 (en) Structure and methods of fabricating y-shaped dmos finfet
CN102956498B (zh) 半导体器件及其制造方法
JPWO2019107411A1 (ja) トンネル電界効果トランジスタおよび電子デバイス
CN103811315A (zh) 半导体器件及其制造方法
CN102214683B (zh) 具有悬空源漏的半导体结构及其形成方法
CN102214681B (zh) 半导体结构及其形成方法

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant