CN104854703B - 缩小尺寸的共振隧穿场效应晶体管 - Google Patents

缩小尺寸的共振隧穿场效应晶体管 Download PDF

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CN104854703B
CN104854703B CN201380061009.7A CN201380061009A CN104854703B CN 104854703 B CN104854703 B CN 104854703B CN 201380061009 A CN201380061009 A CN 201380061009A CN 104854703 B CN104854703 B CN 104854703B
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hetfet
source electrode
semiconductor device
conduction band
drain electrode
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CN104854703A (zh
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U·E·阿维奇
D·E·尼科诺夫
I·A·扬
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Abstract

实施例包括异质结隧穿场效应晶体管，所述异质结隧穿场效应晶体管包括源极、沟道和漏极；其中，(a)所述沟道包括与沟道长度相对应的长轴，以及与沟道宽度相对应并且与所述长轴正交的短轴；(b)所述沟道长度小于10nm长；(c)对所述源极进行掺杂使其具有第一极性，并且所述源极具有第一导带；(d)对所述漏极进行掺杂使其具有与所述第一极性相反的第二极性，并且所述漏极具有第二导带，所述第二导带比所述第一导带具有更高能量。本文描述了其它实施例。

Description

缩小尺寸的共振隧穿场效应晶体管
技术领域
本发明涉及半导体装置。
背景技术
隧穿场效应晶体管(TFET)结构与金属氧化物半导体场效应晶体管(MOSFET)的结构类似，并且包括源极、漏极和耦合至栅极的沟道。TFET以不同形式获得，诸如n型(nTFET)器件和p型(pTFET)器件。对于nTFET，漏极电流(Id)随着增加的栅极电压(Vg)而增加，而对于pTFET，漏极电流(Id)随着减小的Vg而增加。对于大于阈值电压的栅极/源极电压(Vg)，nTFET开启(“导通状态”)，而对于小于阈值电压的Vg，pTFET开启。nTFET中的源极为p掺杂的，而漏极为n掺杂的，并且pTFET中的源极为n掺杂的，而漏极为p掺杂的。就掺杂浓度而言，沟道为未掺杂的或者比源极或漏极掺杂少的。
发明内容
根据本发明的一个方面，提供一种半导体装置，其包括：n异质结隧穿场效应晶体管(n-heTFET)，所述n异质结隧穿场效应晶体管包括源极、沟道和漏极；其中，(a)所述沟道包括与沟道长度相对应的长轴，以及与沟道宽度相对应并且与所述长轴正交的短轴；(b)所述沟道长度小于10nm长；(c)所述源极是正掺杂的并且具有第一导带；(d)所述漏极是负掺杂的并且具有第二导带，所述第二导带比所述第一导带具有更高能量；以及(e)所述源极和所述漏极分别包括InAs和GaSb；Si和InAs；Si和SiGe；GaAsSb和InAsSb；以及InGaAs和InP中的一个。
根据本发明的另一个方面，提供另一种半导体装置，其包括：衬底；第一n异质结隧穿场效应晶体管(n-heTFET)，所述第一n异质结隧穿场效应晶体管包括正掺杂的第一源极、第一沟道和负掺杂的第一漏极；其中，所述第一沟道长度小于10nm长，所述第一漏极的导带比所述第一源极的导带具有更高能量，以及所述第一n-heTFET形成在所述衬底上；以及第二heTFET，所述第二heTFET包括第二源极、第二沟道和第二漏极；其中，所述第二漏极的导带比所述第二源极的导带具有更低能量，并且所述第二heTFET形成在所述衬底上；并且其中，所述第一源极和所述第一漏极分别包括InAs和GaSb；Si和InAs；Si和SiGe；GaAsSb和InAsSb；以及InGaAs和InP中的一个。
附图说明
根据所附权利要求、以下对一个或多个示例性实施例的详细描述以及相对应的附图，本发明的实施例的特征和优点将变得显而易见，在附图中：
图1-2涉及MOSFET、TFET和异质结TFET(heTEFT)的截止/导通状态特性；
图3涉及传统的heTFET结构；
图4涉及实施例中的反向heTFET结构；
图5-6涉及实施例中的MOSFET、heTFET及反向heTFET的截止/导通状态特性；
图7-8涉及实施例中的MOSFET、heTFET及反向heTFET的截止/导通状态特性；
图9涉及实施例中的反向heTFET能带图；
图10(a)-(d)涉及实施例的态密度(DOS)；
图11包括实施例的横截面示意图。
具体实施方式
在下面的描述中，阐述了许多具体细节，但是本发明的实施例可以在没有这些具体细节的情况下得以实施。没有详细示出公知的电路、结构和技术，以避免掩盖对此描述的理解。“实施例”、“各个实施例”等指示如此描述的实施例可以包括特定的特征、结构或特性，但不是每一个实施例必须包括特定的特征、结构或特性。一些实施例可以具有针对其它实施例所描述的特征中的一些或所有特征或不具有所述特征。“第一”、“第二”、“第三”等描述共同对象并且指示提及的类似对象的不同例子。这种形容词并不暗示如此描述的对象在时间上、空间上、排序上或以其它任何方式必须处于给定的顺序。“连接”可以指示元件彼此直接物理地或电气地接触，并且“耦合”可以指示元件彼此协作或彼此交互，但它们可以或可以不处于直接的物理或电气接触。另外，虽然类似或相同的附图标记可以用于表示不同附图中的相同或类似的部分，但是这样做并不意指包括类似或相同附图标记的所有附图组成单个或相同的实施例。
在室温下，MOSFET的反向“亚阈值斜率”dVg/dlog(Id)具有60mV/decade(“dec”)的理论下限。亚阈值斜率涉及器件的“截止状态”(即，其中Id很小，也被称为Ioff或“截止电流”)和器件的“导通状态”(即，其中存在大量的Id，也被称为Ion或“导通电流”)附近的电流-电压特性的斜率。对于给定的截止电流目标(其由包括MOSFET的设备的待机功率需求决定)，MOSFET的Id只能以此60mV/dec的最大比率增加。这限制了导通电流并且因此限制了电路性能(例如，晶体管进行开关的速度)。对于低有功功率设备，由于对电源电压上有功功率的强烈依赖(与电源电压的2次幂成比例)，在较低电源电压下工作是期望的。然而，由于MOSFET的受限的亚阈值斜率，当MOSFET在低电源电压下工作时，导通电流显著降低，因为MOSFET在其阈值电压附近工作(其需要从截止状态转变为导通状态)。
图1描绘了各种晶体管性能特性，其示出了例如TFET(迹线(trace)102)可比MOSFET(迹线101)具有更急剧的启动行为(turn on behavior)(即，更陡峭的亚阈值斜率)。图1的情形包括1nA/μm的Ioff，等同于0.8nm的氧化物厚度(EOT)以及栅极长度(Lg)＝15nm。TFET的此鲜明的优势在图1中从0.0至0.2V的Vg示出，在该相同范围内MOSFET 101具有74mV/dec的斜率并且TFET 102具有41mV/dec的斜率。换句话说，TFET具有更陡峭并且更期望的亚阈值斜率。这使得能够当在低电源电压下驱动器件时实现比在MOSFET的情况下具有的更高的导通电流。heTFET(迹线103)使用两种半导体材料的组合(一种用于源极，以及另一种用于沟道和漏极；因此为术语异质结)来使得能够实现更高的隧穿电流和更好的TFET特性。heTFET 103的亚阈值斜率大约为35mV/dec，比TFET 102或MOSFET 101更好(更陡峭)。
然而，TFET器件超过MOSFET的此优势在大幅缩小的(更短的)栅极长度时变得更小。当图1包括具有15nm的Lg的器件的数据时，图2包括与图1相同条件下的数据(除了只有9nm的Lg以外)。图2示出了对于0.0至0.1V的Vg，201、202、203的亚阈值斜率是类似的(与图1在该相同范围内示出了TFET对MOSFET的清晰的优势(更陡峭的斜率)对比)。三个器件之间的亚阈值斜率的差别随着栅极长度减小而减小。换句话说，在图1与图2之间，与MOSFET相比，迹线202和迹线203(其都是TFET)具有更小的斜率陡峭改善。
图3描绘了传统heTFET设计，其结合了在源极处的半导体材料(例如，锑化镓(GaSb))与在沟道和漏极处的更低导带的材料(例如砷化铟(InAs))。与之对比，图4描绘了包括其中切换了带材料顺序的反向heTFET的本发明的实施例。换句话说，图4的反向heTFET设计结合了在源极处的半导体材料(例如，InAs)与在沟道和漏极处的更高导带的材料(例如，GaSb)。然而，在图4中，来自不同材料的带不连续性对隧穿电流密度不利并造成更困难的隧穿路径。
本发明的实施例不限于诸如以上所描述的InAs/GaSb材料系统的源极/漏极组合。其它实施例包括产生显著的带不连续性的材料的组合。其它的示例包括诸如硅(Si)、锗(Ge)、磷(P)，并且包括但不限于诸如：Si/InAs、Si/SiGe、GaAsSb/InAsSb和InGaAs/InP的源极/漏极的组合。
这可以从在图5和图6中示出的各自具有Lg＝20nm的传统heTFET器件与反向heTFET器件之间的工作特性差异看出来。在图5和图6中，针对1nA/μm(图5，元素505)和10pA/μm(图6，元素605)的截止电流目标，绘出了MOSFET(迹线501、601)、传统heTFET(源极＝GaSb，漏极＝InAs)(迹线503、603)以及反向heTFET(源极＝InAs，漏极＝GaSb)(迹线504、604)。这些图示出了当器件具有Lg＝20nm时，对于各个截止电流目标和电源电压，传统heTFET比反向heTFET具有更高的导通电流。
然而，此行为随着具有受限的沟道尺寸的非常短的Lg而变化。对于短的Lg，反向heTFET具有非常陡峭的亚阈值斜率。这使得能够实现低电源电压和低截止电流目标的工作，其都能实现非常低的功率产品。例如，实施例包括具有在3nm宽和3nm高的纳米线(半导体纳米级结构)中包括的Lg＝9nm的沟道。如图7和图8中所见，此反向heTFET实施例具有非常陡峭的亚阈值斜率。针对1nA/μm(图7)和10pA/μm(图8)的Ioff目标，分别绘出了MOSFET(迹线701、801)、传统heTFET(源极＝GaSb，漏极＝InAs)(迹线703、803)和反向heTFET(源极＝InAs，漏极＝GaSb)(迹线704、804)。所有器件具有Lg＝9nm。在低电源电压下的两个Ioff目标处，反向heTFET示出了最佳的亚阈值斜率并且表现最佳。特别地，对于图8，反向heTFET迹线804示出了25mV/dec的亚阈值斜率(在0.0和0.1的Vg之间)，然而，异质结器件迹线803示出了47mV/dec的亚阈值斜率，并且MOSFET 801示出了63mV/dec的亚阈值斜率。因此，在低电源电压下，反向heTFET的此实施例实现了比MOSFET和传统heTFET更好的导通电流。
由于例如由反向heTFET沟道的三维局限产生的分立(discreet)的谐振状态，实施例已经提高了晶体管的特性。例如，实施例包括具有小于10nm的Lg的沟道，通过使用3nm的纳米线宽度和高度来局限两个维度，并且第三个维度由于实施例的源极与沟道之间带不连续性的分布而被局限。由于紧密的态密度(DOS)特性，这些谐振状态使得能够实现从Ioff到Ion的快速变化。
当观察经典的电势分布图时，从Ioff到Ion的此快速变化是不明显的。例如，在包括反向heTFET的实施例中，能带未精确地解释实际的器件工作。图9示出了反向heTFET在Ioff和在Ion的经典带边缘(迹线910和迹线911)。迹线910与在0.0ev下的导带和价带相对应，以及迹线911与在0.3ev下的导带和价带相对应。隧穿距离920是大的，但即使如此，隧穿距离921保持大的(指示在导通状态下的非常低的(不期望的)沟道电流)。
然而，图10(a)-(d)更好地示出了器件的实施例的工作以及为何高度限制的沟道形状比起非反向heTFET和MOSFET更偏爱反向heTFET。由于强烈的沟道限制，允许的电子能量在异质结界面区周围具有峰值。特别地，图10(a)-(d)示出了态密度(DOS)特性。DOS等于薛定谔方程的解的数量的每单位体积和能量的密度。图10(a)和(b)与传统heTFET(Lg＝9nm)的截止状态和导通状态相对应。图10(c)和(d)与反向heTFET(Lg＝9nm)的截止状态和导通状态相对应。直到分立能态与源极侧的价带(图10(a)-(d)的每一个中的区域1021)对齐，由于对于传导电子所必要的区域中的低DOS，隧道电流是低的。因此，图10(a)示出了在截止状态下的具有大的隧穿距离1020的传统heTFET。图10(c)示出了在截止状态下的具有大的隧穿距离1030的反向heTFET的实施例。
在图10(c)中，对于传统heTFET，一旦Vg增加，源极/沟道结1023处就仍然存在低的DOS(如根据阴影等值标记理解的)。然而，在图10(d)中，一旦使分立水平的能量降低至源极侧1021的价带的水平(由于增加的Vg)，隧穿电流就会存在急剧的增加，其产生陡峭的亚阈值斜率行为。换句话说，源极/沟道结1033包括高DOS投影1034(像水平的“针”指向图的左边)。在Ioff中，高DOS投影1031与源极价带1021未对齐(图10(c))；但是在图10(d)中，投影1034与源极价带1021对齐。更普遍地，图10(d)示出了沿着在源极/沟道结附近(在X轴上10nm标记附近)的器件的高DOS(较暗的部分为较高的DOS)随能量变化的函数。因此，反向heTFET在小的Lg时优于传统heTFET，在更低的Vg提供更佳的导通电流。
利用与传统heTFET(仅仅利用如图4中所示的在源极和沟道/漏极区域中的切换的半导体材料)相同或类似的方法来实施实施例。这使得能够实现两个器件的异质集成，其中，例如，高性能要求电路使用传统的异质结器件而低功率要求电路在相同的衬底上使用反向heTFET。
用于产生适合于反向heTFET的窄沟道的多个方法是可用的。这种方法在例如归属于英特尔公司(美国，加利福尼亚，圣塔克拉拉)的美国专利号No.6,897,098并且名称为“Method of fabricating an ultra-narrow channel semiconductor device”中描述。如美国专利号No.6,897,098中详述的，如下地产生适合在本发明的各个实施例中使用的小尺寸沟道。在形成于衬底1102上的(见图11)第一电介质层1104上沉积纳米线1106。纳米线具有第一维度。纳米线提供第一区域1108、第二区域1107以及第三区域1109。在纳米线的第一区域1108上方沉积具有牺牲电介质层和牺牲栅极电极层的牺牲栅极叠置体，留下纳米线中暴露的第二区域和第三区域。在牺牲栅极叠置体的每一侧附近沉积第一间隔体。在第一电介质层上方沉积第二电介质层，以覆盖第二区域和第三区域。在沉积第一间隔体后去除牺牲栅极电极和牺牲电介质层。去除牺牲栅极电极和牺牲电介质层暴露了纳米线的第一区域。通过至少一次热氧化和氧化物去除工艺来减薄纳米线的第一区域。在减薄之后，第一区域具有比第一维度更小的第二维度。减薄纳米线的第一区域提供了纳米线的具有横截面维度的第一区域，该第一区域的横截面维度基本上小于(例如十倍或至少两倍小于)第二区域和第三区域的横截面维度。第一区域可以是纳米线的中间区域108，并且第二区域和第三区域1107、1109可以是纳米线的侧部区域。可以添加电介质层1125和栅极电极层1123。
在一个实施例中，纳米线具有在纳米级数量级的第一横截面尺寸。纳米线具有约2nm、3nm、4nm、5nm、6nm、7nm、8nm、9nm、10nm、11nm、12nm、13nm、14nm或15nm的长度1130，约2nm、3nm、4nm、5nm、6nm、7nm、8nm、9nm、10nm、11nm、12nm、13nm、14nm或15nm的高度132以及约2nm、3nm、4nm、5nm、6nm、7nm、8nm、9nm、10nm、11nm、12nm、13nm、14nm或15nm的宽度134。高度、宽度和长度取决于用于形成纳米线的方法而不同。如上文所示出的，一些实施例包括10nm、3nm和3nm的长度、宽度、高度的组合。但其它实施例包括例如且非限制的8nm、3nm和3nm；12nm、3nm和3nm；8nm、2nm和2nm等的长度、宽度、高度的组合。
在一个实施例中，在减薄之前，中间区域具有与纳米线的剩余部分相同的初始厚度或横截面维度。在减薄后，中间区域将具有小于或基本上小于纳米线1106的其它部分的横截面维度。在一个实施例中，减薄的中间部分具有小于约5nm或小于约2-3nm的宽度和/或高度。在一些实施例中，没有对中间部分1108进行减薄，其具有与部分1107、1109相同的高度和宽度。
在一个实施例中，使用诸如离子注入的传统方法来注入第二区域和第三区域，以形成半导体器件的源极/漏极区域。例如，对于n heTFET，区域1107可以是p掺杂的源极，沟道区域1108可以是本征的，以及区域1109可以是n掺杂的漏极。在另一个实施例中，对于pheTFET，区域1107可以是p掺杂的漏极，沟道区域1108可以是本征的，以及区域1109可以是n掺杂的源极。源极和漏极在掺杂浓度、材料浓度(例如，InxGa1-xAs和InyGa1-yAs，其中x不等于y)以及材料(例如，InAs和GaSb)方面可以为不同材料。
可以在注入后在第二区域和第三区域中的每一个上形成硅化物层，以促进至源极/漏极区域的接触。硅化物层提供至在第二区域和第三区域中形成的源极/漏极区域的低接触电阻。硅化物层可以由诸如钴、镍等的金属形成。可以使用在第二区域和第三区域上方沉积金属的传统方法来形成硅化物层。在沉积金属之后，向这些区域施加热量，以允许这些区域中的硅与金属反应来形成硅化物。
因此，如以上所指示的，实施例包括heTFET，所述heTFET包括源极、沟道和漏极；其中，沟道包括与沟道长度相对应的长轴以及与沟道宽度相对应并且与长轴正交的短轴。在实施例中，沟道长度小于10nm长；但在其它实施例中，长度更长(例如，10nm或15nm)或更短(例如3或nm)。在一个实施例中，沟道宽度小于5nm宽，但在其它实施例中，宽度更宽(例如7nm或9nm)或更窄(例如2或3)。在一个实施例中，沟道高度小于5nm宽，但在其它实施例中，高度更高(例如，7nm或9nm)或更矮(例如，2或3)。对于p heTFET，对源极进行掺杂使其具有第一极性(n)，并且所述源极具有第一导带；以及对漏极进行掺杂使其具有第二极性(p)，并且所述漏极具有第二导带，所述第二导带比第一导带更高。对于n heTFET，掺杂极性相反。在一个实施例中，截止电流小于3nA并且可以向下延伸至例如1pA，但在其它实施例中，截止电流可以是1nA或2nA或4nA、5nA、6nA、7nA、8nA、9nA或更多nA。在一个实施例中，在从截止状态到导通状态的转变之间发生的阈值栅极电压与漏极电流的对数的比率(阈值电压斜率)小于30mV/dec，但是在其它实施例中，该斜率为15mV/dec、20mV/dec、25mV/dec、35mV/dec或40mV/dec。
实施例包括装置，所述装置包括：异质结隧穿场效应晶体管，所述异质结隧穿场效应晶体管包括源极、沟道和漏极；其中，(a)沟道包括与沟道长度相对应的长轴，以及沟道宽度相对应并且与长轴正交的短轴；(b)沟道长度小于10nm长；(c)对源极进行掺杂使其具有第一极性，并且所述源极具有第一导带；(d)对漏极进行掺杂使其具有与第一极性相反的第二极性，并且漏极具有第二导带，所述第二导带比第一导带具有更高能量。在实施例中，第一极性为正。在实施例中，源极包括InAs。在实施例中，漏极包括GaSb。在实施例中，沟道宽度小于4nm宽。在实施例中，沟道包括纳米线。在实施例中，截止电流小于3nA。在实施例中，在从截止状态到导通状态的转变之间发生的亚阈值栅极电压与漏极电流的比率小于30mV/dec。在实施例中，源极与沟道之间的结处的DOS包括在“截止状态”中与源极的价带未对齐而在“导通状态”中与价带对齐的三角投影。在实施例中，在导通状态下，允许的电子能态在源极与沟道之间的结处具有峰值。在实施例中，heTFET为反向异质结TFET，在衬底中包括非反向异质结TFET(即，异质结TFET)的装置还包括反向异质结TFET。
实施例包括装置，所述装置包括：异质结隧穿场效应晶体管，所述异质结隧穿场效应晶体管包括源极、沟道和漏极；其中，沟道长度小于10nm长；漏极导带，所述导带比源极的导带具有更高能量；以及晶体管包括在从“截止状态”到“导通状态”的转变之间发生的小于30mV/dec的亚阈值栅极电压与漏极电流的比率。在实施例中，源极与沟道之间的结处的DOS包括在“截止状态”中与源极的价带未对齐而在“导通状态”中与价带对齐的三角投影。在实施例中，在导通状态下，允许的电子能态在源极与沟道之间的结处具有峰值。
实施例包括装置，所述装置包括：衬底；第一heTFET，所述第一heTFET包括第一源极、第一沟道和第一漏极；其中，第一沟道长度小于10nm长，第一漏极具有导带，所述导带比第一源极的导带具有更高能量，以及heTFET在形成衬底上；以及第二heTFET，所述第二heTFET包括第二源极、第二沟道和第二漏极；其中，第二漏极具有导带，所述导带比第二源极的导带具有更低能量，以及第二heTFET形成在衬底上。在实施例中，第一heTFET包括在从“截止状态”到“导通状态”的转变之间发生的小于30mV/dec的亚阈值栅极电压与漏极电流的斜率。在实施例中，第一沟道宽度小于4nm宽。在实施例中，第一heTFET的截止电流小于3nA。
虽然已经针对有限数量的实施例描述了本发明，但是本领域技术人员将意识到由此产生的许多修改和变型。旨在所附权利要求覆盖落入本发明的真实精神和范围之内的所有这种修改和变型。

Claims (14)

1.一种半导体装置，包括：
n异质结隧穿场效应晶体管(n-heTFET)，所述n异质结隧穿场效应晶体管包括源极、沟道和漏极；
其中，(a)所述沟道包括与沟道长度相对应的长轴，以及与沟道宽度相对应并且与所述长轴正交的短轴；(b)所述沟道长度小于10nm长；(c)所述源极是正掺杂的并且具有第一导带；(d)所述漏极是负掺杂的并且具有第二导带，所述第二导带比所述第一导带具有更高能量；以及(e)所述源极和所述漏极分别包括InAs和GaSb；Si和InAs；Si和SiGe；GaAsSb和InAsSb；以及InGaAs和InP中的一个。
2.如权利要求1所述的半导体装置，其中，所述源极包括InAs。
3.如权利要求2所述的半导体装置，其中，所述漏极包括GaSb。
4.如权利要求1所述的半导体装置，其中，所述沟道宽度小于4nm宽。
5.如权利要求1所述的半导体装置，其中，所述沟道包括纳米线。
6.如权利要求1所述的半导体装置，其中，所述n-heTFET的截止电流小于3nA。
7.如权利要求1所述的半导体装置，其中，所述n-heTFET包括在从截止状态到导通状态的转变之间发生的小于30mV/dec的亚阈值栅极电压与漏极电流的比率。
8.如权利要求1所述的半导体装置，其中，在所述源极与沟道之间的结处的态密度(DOS)包括在截止状态下与所述源极的价带未对齐而在导通状态下与所述价带对齐的三角投影。
9.如权利要求1所述的半导体装置，其中，在导通状态下，允许的电子能态在所述源极与所述沟道之间的结处具有峰值。
10.如权利要求1所述的半导体装置，所述装置在衬底上包括heTFET，所述heTFET还包括所述n-heTFET，其中，所述heTFET包括附加源极和附加漏极，并且所述附加源极的导带比所述附加漏极的导带具有更高能量。
11.一种半导体装置，包括：
衬底；
第一n异质结隧穿场效应晶体管(n-heTFET)，所述第一n异质结隧穿场效应晶体管包括正掺杂的第一源极、第一沟道和负掺杂的第一漏极；其中，所述第一沟道长度小于10nm长，所述第一漏极的导带比所述第一源极的导带具有更高能量，以及所述第一n-heTFET形成在所述衬底上；以及
第二heTFET，所述第二heTFET包括第二源极、第二沟道和第二漏极；其中，所述第二漏极的导带比所述第二源极的导带具有更低能量，并且所述第二heTFET形成在所述衬底上；并且其中，所述第一源极和所述第一漏极分别包括InAs和GaSb；Si和InAs；Si和SiGe；GaAsSb和InAsSb；以及InGaAs和InP中的一个。
12.如权利要求11所述的半导体装置，其中，所述第一n-heTFET包括在从截止状态到导通状态的转变之间发生的小于30mV/dec的亚阈值栅极电压与漏极电流的比率。
13.如权利要求11所述的半导体装置，其中，所述第一沟道宽度小于4nm宽。
14.如权利要求13所述的半导体装置，其中，所述第一n-heTFET的截止电流小于3nA。
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