TW201521200A - 半導體裝置結構及其製作方法 - Google Patents

半導體裝置結構及其製作方法 Download PDF

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TW201521200A
TW201521200A TW103115924A TW103115924A TW201521200A TW 201521200 A TW201521200 A TW 201521200A TW 103115924 A TW103115924 A TW 103115924A TW 103115924 A TW103115924 A TW 103115924A TW 201521200 A TW201521200 A TW 201521200A
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germanium concentration
concentration
channel layer
germanium
uniaxial stress
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TWI532183B (zh
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Ka-Hing Fung
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Taiwan Semiconductor Mfg Co Ltd
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Abstract

一種半導體裝置結構，包括：一通道層，包括具有鍺濃度B之鍺化合物，形成於一半導體基底上，其中半導體基底具有鍺濃度A，且基底之鍺濃度A小於通道層之鍺濃度B；及一蓋層，將通道層與一金屬閘極分隔，蓋層具有鍺濃度C，通道層之鍺濃度B大於蓋層之鍺濃度C。

Description

半導體裝置結構及其製作方法
本發明係有關於一種半導體裝置，特別有關於一種多層結構。
非平面電晶體結構使得裝置在小面積區域可達成高效能。此結構的製作通常限制於製作此結構之材料的特性。在此例如三閘(tri-gate)、鰭式場效電晶體(fin field effect transistor，FinFET)、環繞式閘極(gate-all-around)結構之非平面電晶體之通道材料工程可達成高移動率，且改進電晶體之效能。
本發明提供一種半導體裝置結構，包括：一通道層，包括具有鍺濃度B之鍺化合物，形成於一半導體基底上，其中半導體基底具有鍺濃度A，且基底之鍺濃度A小於通道層之鍺濃度B；及一蓋層，將通道層與一金屬閘極分隔，蓋層具有鍺濃度C，通道層之鍺濃度B大於蓋層之鍺濃度C。
本發明提供一種半導體裝置結構之製作方法，包括：形成一鍺化合物之通道層於一半導體基底上，其中通道層具有鍺濃度B，半導體基底具有鍺濃度A，半導體基底之鍺濃度A小於通道層之鍺濃度B；及形成一蓋層以將通道層與金屬 閘極分隔，蓋層具有鍺濃度C，通道層之鍺濃度B大於蓋層之鍺濃度C。
100‧‧‧半導體裝置結構
102‧‧‧基底
104‧‧‧通道層
106‧‧‧蓋層
108‧‧‧金屬閘極
110‧‧‧高介電常數/氧化物介電層
112‧‧‧單軸應力導引部分
114‧‧‧單軸應力導引部分
116‧‧‧淺溝槽隔離氧化層
118‧‧‧底部表面
120‧‧‧底部表面
122‧‧‧底面
124‧‧‧緩衝區
302‧‧‧步驟
304‧‧‧步驟
306‧‧‧步驟
第1圖是一示意圖，顯示沿通道方向包括含鍺通道層之多層半導體裝置結構。
第2圖為是一多層半導體結構之示意圖，包括沿寬度方向的含鍺通道層。
第3圖是一流程圖，顯示一製作半導體裝置結構之方法。
第1圖顯示一範例示意圖，揭示一包括含鍺通道層之多層半導體裝置結構。使用Ge或SiGe材料之含鍺通道層經由導入高應力、改進的量子井限制和較高的本質移動率，提供改善傳統矽通道系統P型場效電晶體驅動電流的機制。第1圖顯示此包括含鍺通道層半導體結構100沿著通道的剖面圖。提供一半導體材料形成之基底102，且於其上形成後續的結構。基底102可以為各種的型態，例如矽基底或含鍺物質之基底，其含鍺物質例如為鍺濃度為A之矽鍺(亦即A%鍺)。使用一第二半導體材料形成通道層104於基底102的頂部。通道層104包括鍺濃度為B之化合物。在一實施例中，基底之鍺濃度A小於通道層之鍺濃度B(亦即B>A)。在另一實施例中，基底之鍺濃度A等於通道層之鍺濃度B。
在本揭示之較佳實施例中，基底之鍺濃度A小於通道層之鍺濃度B，但基底之鍺濃度A沒有小於通道層之鍺濃度B 太多。A和B之間顯著的不同已被發現在特定的操作時會增加特定的晶格缺陷。為了避免此缺陷，本實施例選擇基底之鍺濃度A和通道層之鍺濃度B，使得通道層之鍺濃度B減去基底之鍺濃度A的值小於50%(當濃度以百分比表示)，亦即B-A<50%。
第1圖另揭示形成一蓋層106將通道層104和金屬閘極108分隔。蓋層106包括具有鍺濃度C之含鍺物質。在一實施例中，為了將電洞限制於通道層中，形成蓋層，使得通道層的鍺濃度B大於蓋層的鍺濃度(亦即B>C)。蓋層形成為具有低鍺濃度的薄層，其包括鍺濃度將近為零(亦即<5%)的矽層。在一些特定的實施例中，上述的數個層可插入額外的層，例如介電層110，其可以為包括高介電常數氧化介電物之氧化介電層。
為製作例如電晶體之半導體結構。特定單軸應力導引部分(uni-axial stress inducing portion)係整合入半導體裝置結構中。例如，在特定操作中，這種單軸應力導引部分作為製作電晶體的源極和汲極部分。第1圖揭示這兩個部分112、114。形成單軸應力導引部分112、114於半導體基底102上，且鄰接通道層104。為提供壓應力至通道層104，單軸應力導引部分112、114之一或兩者係形成為具有鍺濃度D大於或等於通道層的鍺濃度(亦即D≧B)。在特定的操作中，單軸應力導引部分112、114之鍺濃度D亦大於基底102之鍺濃度(亦即D>A)。然而，為了避免單軸應力導引部分112、114和基底102間晶格不匹配過大，本實施例可選擇單軸應力導引部分之鍺濃度D，使得單軸應力導引部分之鍺濃度D減去基底之鍺濃度小於50%的值(亦即D-A<50%)(當以百分比表示時)。
第1圖揭示作為一電晶體之半導體裝置結構100。因此，具有鍺濃度D之第一單軸應力導引部分112作為場效電晶體之源極，具有鍺濃度E之第二單軸應力導引部分114作為場效電晶體之汲極，且在特定的操作中，D等於E。金屬閘極108配置為場效電晶體之閘極，使得場效電晶體在特定操作展現特定希望的特性，例如適當的函數VDD>0.6V。
在特定的操作中，單軸應力導引部分112、114以其他的方式變化。例如，在一實施例中，單軸應力導引部分112、114的鍺濃度從頂部部分至底部部分逐漸變化，使得單軸應力導引部分之頂部部分的鍺濃度D1高於底部部分的鍺濃度D2。在此操作中，當限制單軸應力導引部分112、114和基底102界面間大的晶格不匹配時，頂部部分具有較高的鍺濃度(亦即選擇鍺濃度使得D2-A<50%)。
本實施例可設計多種的半導體裝置結構以實行在此所描述的設計標準。在一範例中，基底102的鍺濃度A選擇為30%，通道層104的鍺濃度B選擇為60%，蓋層106的鍺濃度C選擇為0%，且單軸應力導引部分112、114的鍺濃度D、E選擇為60%至100%之間。上述濃度可在本發明範疇之內進行變動，其包括基底102的鍺濃度A為0%之操作。
第2圖為一描述多層半導體結構之示意圖，其包括沿著寬度方向的含鍺通道層。半導體裝置結構100包括形成有具有鍺濃度B之鍺化合物的通道層104，形成於一半導體基底102上，其中半導體基底具有鍺濃度A，而鍺濃度A小於通道層之鍺濃度B。形成一蓋層106以將通道層104和金屬閘極108分 隔，蓋層106具有鍺濃度C，其中通道層之鍺濃度B大於蓋層之鍺濃度C。第2圖之半導體結構包括額外的層：包括一高介電常數/氧化物介電層110，位於蓋層106和金屬閘極108間，及淺溝槽隔離氧化層116，位於基底102和金屬閘極108間。
在一實施例中，製作半導體裝置，使得金屬閘極108的底部表面118未垂直對準通道層104之底部表面120。本實施例此調整此偏移量X可藉由改變基底緩衝區124的尺寸實現，以改變特定的半導體裝置的參數。例如，當X為正，如第2圖所示，通道層104之底部表面120相較於金屬閘極108之底部表面118係與半導體裝置結構100之底面122偏移，ION因為有效寬度減少而降低。當X為負，可觀察到漏電流增加。在一實施例中，通道層104之底部表面120從半導體裝置結構100之底面122相較於金屬閘極108之底部表面118偏移1nm~5nm。此偏移量可根據系統的需要改變，例如在+5nm至-5nm之數值範圍間。
第3圖為一流程圖，描述一製作半導體裝置結構之方法。在步驟302，形成一具有鍺濃度B之鍺化合物之通道層於一半導體基底上，其中半導體基底具有鍺濃度A，且鍺濃度A小於鍺濃度B。在步驟304，形成一蓋層以將通道層和金屬閘極分隔，蓋層具有鍺濃度C，通道層之鍺濃度B大於蓋層之鍺濃度C。在步驟306，形成一具有鍺濃度D之單軸應力導引部分於半導體基底上，且鄰接通道層。單軸應力導引部分之鍺濃度D大於或等於通道層之鍺濃度B，且單軸應力導引部分之鍺濃度D大於基底之鍺濃度A。
本描述使用範例來公開本發明，包括最佳模式， 並且使本領域技術人員在本領域中能夠製造和使用本發明。本發明的可專利範圍可包括於本領域技術人員可想到的其他範例。相關領域技術人員將認識到，各種實施例可以在沒有一或多個具體細節的情況下實行，或用其它替代及/或附加方法，材料或組件。眾所周知的結構，材料或作動，可以不顯示出或詳細描述，以避免模糊本公開的各個實施例的方面。在圖中所示的各種實施例是說明性的範例表示，並且不一定按比例繪製。特定特徵、結構、材料或特性在一個或多個實施例可以任何合適的方式被組合。各種附加層及/或結構可被包括，且所描述的特徵可以在其他實施例中可以省略。各種作動可以被描述為多個分立的作動，其方式是最有助於理解本發明。然而，描述的順序不應被解釋為暗示這些作動一定是順序相關的。特別地，這些作動不必按照說明書的順序來執行。本文所描述的作動可以不同的順序來執行。各種額外的作動可被執行及/或說明。作動可以在另外的實施例可以省略。
本描述和下面的申請專利範圍可以包括術語，例如左、右、頂部、底部、上方、下方、上、下、第一、第二等，其被用於描述的目的，並且不被解釋為限制。例如，術語指示相對的垂直位置可以是指以下一種情況：在基底或積體電路的裝置側(或主動表面)是該基底的“頂”表面上；基底可實際上處於任何方向，使得基底的”頂“側可比的標準地面”底“側低，但仍可落在術語所指的”頂“。“上”，如本文使用的(包括在申請專利範圍中)的術語可能不表示第一層直接位於第二層上並與所述第二層直接接觸，除非有這樣明確的說明；有可能是一第三 層或其它結構，位於所述第一層和第二層之間。一個裝置或物品在本文所描述的實施例可以被製造，使用或傳遞在多個位置和方向。本領域的技術人員將認識在附圖中示出的各種組件之各種組合和替換。
100‧‧‧半導體裝置結構
102‧‧‧基底
104‧‧‧通道層
106‧‧‧蓋層
108‧‧‧金屬閘極
110‧‧‧高介電常數/氧化物介電層
112‧‧‧單軸應力導引部分
114‧‧‧單軸應力導引部分

Claims (11)

  1. 一種半導體裝置結構，包括：一通道層，包括具有鍺濃度B之鍺化合物，形成於一半導體基底上，其中該半導體基底具有鍺濃度A，且該半導體基底之鍺濃度A小於該通道層之鍺濃度B；及一蓋層，將該通道層與一金屬閘極分隔，該蓋層具有鍺濃度C，該通道層之鍺濃度B大於該蓋層之鍺濃度C。
  2. 如申請專利範圍第1項所述之半導體裝置結構，更包括：一具有鍺濃度D之單軸應力導引部分，形成於該半導體基底上，且鄰接該通道層，該單軸應力導引部分之鍺濃度D大於或等於該通道層之鍺濃度B，且該單軸應力導引部分之鍺濃度D大於該半導體基底之鍺濃度A。
  3. 如申請專利範圍第1項所述之半導體裝置結構，更包括一具有鍺濃度E之第二單軸應力導引部分，形成於該半導體基底上且鄰接該通道層，該第二單軸應力導引部分之鍺濃度E大於或等於該通道層之鍺濃度B，且該第二單軸應力導引部分之鍺濃度E大於該半導體基底之鍺濃度A。
  4. 如申請專利範圍第2項所述之半導體裝置結構，其中該單軸應力導引部分之鍺濃度D係漸變，使得該單軸應力導引部分之頂部的鍺濃度D1大於該單軸應力導引部分之底部的鍺濃度D2。
  5. 如申請專利範圍第4項所述之半導體裝置結構，其中當鍺濃度以百分比表示，該單軸應力導引部分之底部的鍺濃度D2減去該半導體基底之鍺濃度A的值小於50%。
  6. 如申請專利範圍第1項所述之半導體裝置結構，其中當鍺濃度以百分比表示，該通道層的鍺濃度B減去該半導體基底之鍺濃度A的值小於50%。
  7. 如申請專利範圍第1項所述之半導體裝置結構，其中該金屬閘極包括一底部表面且該通道層包括一底部表面，其中該通道層之底部表面與該金屬閘極之底部表面垂直偏移。
  8. 一種半導體裝置結構之製作方法，包括：形成一鍺化合物之通道層於一半導體基底上，其中該通道層具有鍺濃度B，該半導體基底具有鍺濃度A，該半導體基底之鍺濃度A該小於該通道層之鍺濃度B；及形成一蓋層以將該通道層與一金屬閘極分隔，該蓋層具有鍺濃度C，該通道層之鍺濃度B大於該蓋層之鍺濃度C。
  9. 如申請專利範圍第8項所述之半導體裝置結構之製作方法，更包括：形成一具有鍺濃度D之單軸應力導引部分於該半導體基底上且鄰接該通道層，該單軸應力導引部分之鍺濃度D大於或等於該通道層之鍺濃度B，且該單軸應力導引部分之鍺濃度D大於該半導體基底之鍺濃度A。
  10. 如申請專利範圍第8項所述之半導體裝置結構之製作方法，其中該單軸應力導引部分之鍺濃度D係漸變，使得該單軸應力導引部分之頂部的鍺濃度D1大於該單軸應力導引部分之底部的鍺濃度D2。
  11. 如申請專利範圍第8項所述之半導體裝置結構之製作方法，當鍺濃度以百分比表示，該單軸應力導引部分之底部 的鍺濃度D2減去該半導體基底之鍺濃度A的值小於50%。
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