CN114639732A - 半导体元件及其制作方法 - Google Patents

半导体元件及其制作方法 Download PDF

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Publication number
CN114639732A
CN114639732A CN202011478662.1A CN202011478662A CN114639732A CN 114639732 A CN114639732 A CN 114639732A CN 202011478662 A CN202011478662 A CN 202011478662A CN 114639732 A CN114639732 A CN 114639732A
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layer
substrate
cap layer
epitaxial
semiconductor device
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唐启轩
黄仲廷
陈柏勋
陈俊仁
林钰书
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United Microelectronics Corp
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United Microelectronics Corp
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Priority to CN202011478662.1A priority Critical patent/CN114639732A/zh
Priority to US17/147,468 priority patent/US11495686B2/en
Publication of CN114639732A publication Critical patent/CN114639732A/zh
Priority to US17/956,840 priority patent/US11769833B2/en
Priority to US18/234,889 priority patent/US20230395719A1/en
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Abstract

本发明公开一种半导体元件及其制作方法，其中该制作半导体元件的方法为，首先形成一栅极结构于一基底上，然后形成一第一间隙壁于该栅极结构旁，形成一第二间隙壁于该第一间隙壁旁，形成一外延层于第二间隙壁旁，形成第二遮盖层于外延层上，再形成第一遮盖层于第二遮盖层上，其中第一遮盖层上表面包含V形，且第一遮盖层及第二遮盖层包含不同材料。

Description

半导体元件及其制作方法
技术领域
本发明涉及一种制作半导体元件的方法，尤其是涉及一种制作具有V形遮盖层的方法。
背景技术
为了能增加半导体结构的载流子迁移率，可以选择对于栅极通道施加压缩应力或是伸张应力。举例来说，若需要施加的是压缩应力，现有技术常利用选择性外延成长(selective epitaxial growth,SEG)技术于一硅基底内形成晶格排列与该硅基底相同的外延结构，例如硅锗(silicon germanium,SiGe)外延结构。利用硅锗外延结构的晶格常数(lattice constant)大于该硅基底晶格的特点，对P型金属氧化物半导体晶体管的通道区产生应力，增加通道区的载流子迁移率(carrier mobility)，并用于增加金属氧化物半导体晶体管的速度。反之，若是N型半导体晶体管则可选择于硅基底内形成硅碳(siliconcarbide,SiC)外延结构，对栅极通道区产生伸张应力。
现今以外延成长方式形成外延层的晶体管过程中通常会先于栅极结构两侧形成凹槽，再利用外延成长制作工艺形成外延层于凹槽内。然而以外延成长方式所形成的外延层通常无法得到平整的表面轮廓并影响元件运作。因此，如何改良现有制作工艺技术以解决现有瓶颈即为现今一重要课题。
发明内容
本发明一实施例揭露一种制作半导体元件的方法。首先形成一栅极结构于一基底上，然后形成一第一间隙壁于该栅极结构旁，形成一第二间隙壁于该第一间隙壁旁，形成一外延层于第二间隙壁旁，形成第二遮盖层于外延层上，再形成第一遮盖层于第二遮盖层上，其中第一遮盖层上表面包含V形，且第一遮盖层及第二遮盖层包含不同材料。
本发明另一实施例揭露一种半导体元件，其主要包含一栅极结构设于基底上，
外延层设于该栅极结构旁以及一第一遮盖层设于该外延层上，其中第一遮盖层顶表面包含V形。
附图说明
图1至图5为本发明一实施例制作一半导体元件的方法示意图；
图6为本发明一实施例的一半导体元件的结构示意图；
图7为本发明一实施例的一半导体元件的结构示意图；
图8为本发明一实施例的一半导体元件的结构示意图。
主要元件符号说明
12:基底
14:栅极结构
16:栅极结构
18:栅极介电层
20:栅极材料层
22:硬掩模
24:间隙壁
26:轻掺杂漏极
28:凹槽
30:外延层
32:缓冲层
34:第一线性主体层
36:第二线性主体层
38:主体层
40:遮盖层
42:源极/漏极区域
44:接触洞蚀刻停止层
46:层间介电层
48:介质层
50:高介电常数介电层
52:功函数金属层
54:低阻抗金属层
56:硬掩模
58:接触插塞
60遮盖层
62:V形
64:平坦表面
66:曲面
具体实施方式
请参照图1至图5，图1至图5为本发明一实施例制作一半导体元件的方法示意图。如图1所示，首先提供一基底12，然后于基底12上形成至少一栅极结构14、16。在本实施例中，形成栅极结构14、16的方式较佳依序形成一栅极介电层、一栅极材料层以及一硬掩模于基底12上，并利用一图案化光致抗蚀剂(图未示)当作掩模进行一图案转移制作工艺，以单次蚀刻或逐次蚀刻步骤，去除部分硬掩模、部分栅极材料层以及部分栅极介电层，然后剥除图案化光致抗蚀剂，以于基底12上形成至少一由图案化的栅极介电层18、图案化的栅极材料层20以及图案化的硬掩模22所构成的栅极结构14、16。在本实施例中，栅极结构14、16的数量以两颗为例，但不局限于此，且为了凸显后续于两个栅极结构14、16之间所形成的缓冲层与外延层，本实施例仅显示部分栅极结构14、16，例如仅显示栅极结构14的右半部分与栅极结构16的左半部分。
在本实施例中，基底12例如是硅基底、外延硅基底、碳化硅基底或硅覆绝缘(silicon-on-insulator,SOI)基底等的半导体基底，但不以此为限。栅极介电层18可包含二氧化硅(SiO2)、氮化硅(SiN)或高介电常数(high dielectric constant,high-k)材料；栅极材料层20可包含金属材料、多晶硅或金属硅化物(silicide)等导电材料；硬掩模22可选自由氧化硅、氮化硅、碳化硅(SiC)以及氮氧化硅(SiON)所构成的群组，但不局限于此。
此外，在一实施例中，还可选择预先在基底12中形成多个掺杂阱(未绘示)或多个作为电性隔离之用的浅沟槽隔离(shallow trench isolation,STI)。并且，本实施例虽以平面型晶体管为例，但在其他变化实施例中，本发明的半导体制作工艺也可应用于非平面晶体管，例如是鳍状晶体管(Fin-FET)，此时，图1所标示的基底12即相对应代表为形成于一基底12上的鳍状结构。
然后分别在栅极结构14、16侧壁形成至少一间隙壁24，并选择性进行一轻掺杂离子注入，利用约930℃温度进行一快速升温退火制作工艺活化注入基底12的掺质，以于间隙壁24两侧的基底12中分别形成一轻掺杂漏极26。在本实施例中，间隙壁24可为单一间隙壁或复合式间隙壁，例如可细部包含一偏位间隙壁(图未示)以及一主间隙壁(图未示)，偏位间隙壁与主间隙壁较佳包含不同材料，且两者均可选自由氧化硅、氮化硅、氮氧化硅以及氮碳化硅所构成的群组，但不局限于此。
随后进行一干蚀刻及/或湿蚀刻制作工艺，利用栅极结构14、16与间隙壁24为蚀刻掩模沿着间隙壁24向下单次或多次蚀刻基底12，以于栅极结构14、16两侧的基底12中形成凹槽28。举例来说，该蚀刻制作工艺可包含先进行一干蚀刻步骤以在栅极结构14、16两侧的基底12中预先形成一初始沟槽(未绘示)，再接着进行一湿蚀刻制作工艺，各向同性地加大初始沟槽以形成凹槽28。在本发明一实施例中，湿蚀刻制作工艺可选择使用例如氢氧化铵(ammonium hydroxide,NH4OH)或氢氧化四甲基铵(tetramethylammonium hydroxide,TMAH)等蚀刻液体。值得注意的是，形成凹槽28的方式不限于前述干蚀刻搭配湿蚀刻的方式，也可以通过单次或多次的干蚀刻及/或湿蚀刻的方式来形成。例如在一实施例中，凹槽28可具有不同的截面形状，例如是圆弧、六边形(hexagon；又称sigmaΣ)或八边形(octagon)等截面形状，本实施例是以圆弧的截面形状为实施样态说明，但并不以此为限。
随后如图2所示，进行一选择性外延成长(selective epitaxial growth,SEG)制作工艺，利用例如二氯硅甲烷(dichlorosilane,DCS)等气体以于各凹槽28中形成一外延层30，其中外延层30细部包含一缓冲层32设于凹槽28表面、第一线性主体层(first linearbulk layer)34设于缓冲层上32、第二线性主体层(second linear bulk layer)36设于第一线性主体层34上、主体层(bulk layer)38设于第二线性主体层上以及遮盖层40设于主体层38上。
在本实施例中，外延层30的一顶表面较佳与基底12一顶表面齐平，且较佳与凹槽28具有相同的截面形状，如圆弧、六边形(hexagon；又称sigmaΣ)或八边形(octagon)的截面形状，但也可以是其他截面形状。于本发明优选实施例中，外延层30根据不同的金属氧化物半导体(MOS)晶体管类型而可以具有不同的材质，举例来说，若该金属氧化物半导体晶体管为一P型晶体管(PMOS)时，外延层30可选择包含硅化锗(SiGe)、硅化锗硼(SiGeB)或硅化锗锡(SiGeSn)。而于本发明另一实施例中，若该金属氧化物半导体晶体管为一N型晶体管(NMOS)时，外延层30可选择包含碳化硅(SiC)、碳磷化硅(SiCP)或磷化硅(SiP)。此外，选择性外延制作工艺可以用单层或多层的方式来形成，且其异质原子(例如锗原子或碳原子)也可以渐层的方式改变，但较佳是使外延层30的表面较淡或者无锗原子，以利后续金属硅化物层的形成。另一方面，本实施例虽是以顶表面与基底12顶表面齐平的外延层30为实施样态说明，但在本发明的其他实施例中，也可选择使外延层30进一步向上延伸至高于基底12顶表面。
后续进行一离子注入制作工艺，以在外延层30的一部分或全部形成一源极/漏极区域42。在另一实施例中，源极/漏极区域42的形成也可同步(in-situ)于选择性外延成长制作工艺进行，例如金属氧化物半导体是PMOS时，形成硅化锗外延层、硅化锗硼外延层或硅化锗锡外延层，可以伴随着注入P型掺质；或是当金属氧化物半导体是NMOS时，形成硅化碳外延层、硅化碳磷外延层或硅化磷外延层，可以伴随着注入N型掺质。由此可省略后续利用额外离子注入步骤形成P型/N型晶体管的源极/漏极区域。此外在另一实施例中，源极/漏极区域42的掺质也可以渐层的方式形成。
值得注意的是，本实施例所揭露的外延层30较佳包含硅化锗(SiGe)，且外延层30中的缓冲层32、第一线性主体层34、第二线性主体层36、主体层38以及遮盖层40分别具有不同浓度分布以及分布曲线。举例来说，本实施例中缓冲层32的锗浓度较佳小于第一线性主体层34的锗浓度，第一线性主体层34的锗浓度小于第二线性主体层36的锗浓度，第二线性主体层36的锗浓度小于主体层38的锗浓度，且遮盖层40的锗浓度小于主体层38的的锗浓度，其中第一线性主体层34的锗浓度斜率较佳小于第二线性主体层36的锗浓度斜率，且第二线性主体层36厚度也小于第一线性主体层34厚度。
依据本发明的优选实施例，缓冲层32的锗浓度较佳介于30％至33％，第一线性主体层34的锗浓度较佳小于39％，第二线性主体层36的锗浓度较佳介于39％至47％，主体层38的锗浓度较佳介于47％至60％，遮盖层40的锗浓度较佳介于28％至30％。另外在厚度方面缓冲层32的厚度较佳约100埃，第一线性主体层34的厚度较佳约100埃，第二线性主体层36的厚度较佳介于30-50埃，主体层38的厚度较佳介于200～300埃。
接着如图3所示，利用甲硅烷(SiH4)以及二氯硅甲烷(DCS)为前驱物并搭配其他气体以形成一由硅所构成的遮盖层60于遮盖层40表面。值得注意的是，本阶段形成遮盖层60的步骤较佳在不通入含锗气体例如甲锗烷(GeH4)的情况下通入上述前驱物以及其他反应气体例如氯化氢(HCl)及/或乙硼烷(B2H2)来形成遮盖层60，其中甲硅烷的流量较佳介于180～300每分钟标准毫升(standard cubic centimeter per minute,sccm)，二氯硅甲烷的流量介于60～100每分钟标准毫升，氯化氢的流量介于40～100每分钟标准毫升，而乙硼烷的流量则介于200～300每分钟标准毫升。另外沉积遮盖层的时间较佳介于120～170秒，制作工艺温度较佳介于摄氏740～770度，且压力较佳介于5～20托。
依据本发明的优选实施例，经由上述配方可于外延层30的遮盖层40表面形成一约略碗状的遮盖层60，其中遮盖层60顶表面较佳包含一V形62轮廓以及二平坦表面64分别连接V形62两侧，而此特殊轮廓的遮盖层60即可用来可保护间隙壁中特别是偏位间隙壁在后续一系列制作工艺中不致受到蚀刻制作工艺侵蚀而耗损形成孔洞(void)，进而降低半导体元件产生缺陷(defect)的机率。
如图4所示，然后可选择性形成一由氮化硅所构成的接触洞蚀刻停止层(contactetch stop layer,CESL)44于基底12上并覆盖栅极结构14、16与遮盖层60，再形成一层间介电层46于接触洞蚀刻停止层44上。接着进行一平坦化制作工艺，例如利用化学机械研磨(chemical mechanical polishing,CMP)去除部分层间介电层46及部分接触洞蚀刻停止层36使硬掩模22上表面与层间介电层46上表面齐平。
随后进行一金属栅极置换制作工艺将栅极结构14、16转换为金属栅极。例如可先进行一选择性的干蚀刻或湿蚀刻制作工艺，例如利用氨水(ammonium hydroxide,NH4OH)或氢氧化四甲铵(Tetramethylammonium Hydroxide,TMAH)等蚀刻溶液来去除栅极结构14、16中的硬掩模22、栅极材料层20甚至栅极介电层18以于层间介电层46中形成凹槽(图未示)。之后依序形成一介质层48、高介电常数介电层50以及至少包含功函数金属层52与低阻抗金属层54的导电层于凹槽内，并再搭配进行一平坦化制作工艺使U型高介电常数介电层50、U型功函数金属层52与低阻抗金属层54的表面与层间介电层46表面齐平。
在本实施例中，高介电常数介电层50包含介电常数大于4的介电材料，例如选自氧化铪(hafnium oxide,HfO2)、硅酸铪氧化合物(hafnium silicon oxide,HfSiO4)、硅酸铪氮氧化合物(hafnium silicon oxynitride,HfSiON)、氧化铝(aluminum oxide,Al2O3)、氧化镧(lanthanum oxide,La2O3)、氧化钽(tantalum oxide,Ta2O5)、氧化钇(yttrium oxide,Y2O3)、氧化锆(zirconium oxide,ZrO2)、钛酸锶(strontium titanate oxide,SrTiO3)、硅酸锆氧化合物(zirconium silicon oxide,ZrSiO4)、锆酸铪(hafnium zirconium oxide,HfZrO4)、锶铋钽氧化物(strontium bismuth tantalate,SrBi2Ta2O9,SBT)、锆钛酸铅(leadzirconate titanate,PbZrxTi1-xO3,PZT)、钛酸钡锶(barium strontium titanate,BaxSr1- xTiO3,BST)、或其组合所组成的群组。
功函数金属层52较佳用以调整形成金属栅极的功函数，使其适用于N型晶体管(NMOS)或P型晶体管(PMOS)。若晶体管为N型晶体管，功函数金属层52可选用功函数为3.9电子伏特(eV)～4.3eV的金属材料，如铝化钛(TiAl)、铝化锆(ZrAl)、铝化钨(WAl)、铝化钽(TaAl)、铝化铪(HfAl)或TiAlC(碳化钛铝)等，但不以此为限；若晶体管为P型晶体管，功函数金属层52可选用功函数为4.8eV～5.2eV的金属材料，如氮化钛(TiN)、氮化钽(TaN)或碳化钽(TaC)等，但不以此为限。功函数金属层52与低阻抗金属层54之间可包含另一阻障层(图未示)，其中阻障层的材料可包含钛(Ti)、氮化钛(TiN)、钽(Ta)、氮化钽(TaN)等材料。低阻抗金属层54则可选自铜(Cu)、铝(Al)、钨(W)、钛铝合金(TiAl)、钴钨磷化物(cobalttungsten phosphide，CoWP)等低电阻材料或其组合。由于依据金属栅极置换制作工艺将虚置栅极转换为金属栅极乃此领域者所熟知技术，在此不另加赘述。接着可去除部分高介电常数介电层50、部分功函数金属层52与部分低阻抗金属层54形成凹槽(图未示)，然后再填入一硬掩模56于凹槽内并使硬掩模56与层间介电层46表面齐平，其中硬掩模56可选自由氧化硅、氮化硅、氮氧化硅以及氮碳化硅所构成的群组。
如图5所示，之后可进行一图案转移制作工艺，例如可利用一图案化掩模去除栅极结构14、16旁的部分的层间介电层46以及部分接触洞蚀刻停止层44以形成多个接触洞(图未示)并暴露出下面的遮盖层60。然后再于各接触洞中填入所需的金属材料，例如包含钛(Ti)、氮化钛(TiN)、钽(Ta)、氮化钽(TaN)等的阻障层材料以及选自钨(W)、铜(Cu)、铝(Al)、钛铝合金(TiAl)、钴钨磷化物(cobalt tungsten phosphide，CoWP)等低电阻材料或其组合的低阻抗金属层。之后进行一平坦化制作工艺，例如以化学机械研磨去除部分金属材料以分别形成接触插塞58于各接触洞内电连接源极/漏极区域42。至此即完成本发明优选实施例一半导体元件的制作。
请再参照的图5，图5另揭露本发明一实施例的一半导体元件结构。如图5所示，半导体元件包含至少一栅极结构14设于基底12上，间隙壁24设于栅极结构14侧壁，以及外延层30设于间隙壁24两侧的基底12内，以及遮盖层60设于外延层30上，其中外延层30包含缓冲层32、第一线性主体层34、第二线性主体层36、主体层38以及遮盖层40。
在本实施例中，遮盖层40上表面高于基底12上表面，遮盖层40下表面切齐基底12上表面，外延层30中的缓冲层32、第一线性主体层34、第二线性主体层36、主体层38以及遮盖层40较佳包含相同材料例如均由硅化锗(SiGe)所构成但如前所述可包含不同浓度曲线，遮盖层40与遮盖层60较佳包含不同材料例如遮盖层60较佳由硅所构成，遮盖层60下表面高于基底12上表面，且遮盖层60上表面可选择略低于栅极结构14的一半高度或略高于栅极结构14的一半高度。
从形状来看遮盖层60整体较佳呈现约略碗状，其中遮盖层60上表面可包含一V形62以及二与基底12表面平行的平坦表面64连接V形62两侧。但不局限于此，如图6所示，依据本发明另一实施例图5中V形62的所在位置除了遮盖层60中央顶表面整体呈现V形外V形底部又可由一上凹曲面66所取代并连接两侧的平坦表面64，此变化形也属本发明所涵盖的范围。
请再参照图7至图8，图7至图8分别为本发明不同实施例的一半导体元件的结构示意图。如图7所示，相较于图5中的接触插塞58底部仅具有V形轮廓或接触插塞58底部仅接触遮盖层60的V形顶部轮廓，本发明又可调整接触插塞58的宽度使接触插塞58底部同时跨在遮盖层60的V形62轮廓及平坦表面64上或接触插塞58底部本身具有V形62轮廓及平坦表面64位于V形62轮廓两侧，此变化型也属本发明所涵盖的范围。
另外如图8所示，本发明又可如图7般再次扩大接触插塞58的宽度并省略层间介电层46的设置，使接触插塞58底部具有V形62轮廓及平坦表面64位于V形62轮廓两侧的外接触插塞58的左右侧壁又直接接触接触洞蚀刻停止层44而非层间介电层46，此变化型也属本发明所涵盖的范围。
综上所述，本发明主要在形成外延层(包括由锗化硅所构成缓冲层、主体层以及遮盖层)后形成一由硅所构成且具有V形顶部轮廓及二平坦表面的遮盖层于外延层上。依据本发明的优选实施例，经由特定制作工艺配方所形成的碗状遮盖层60可用来可保护间隙壁中特别是偏位间隙壁在后续一系列制作工艺中不致受到蚀刻制作工艺侵蚀而耗损形成孔洞(void)，进而降低半导体元件产生缺陷(defect)的机率。
以上所述仅为本发明的优选实施例，凡依本发明权利要求所做的均等变化与修饰，都应属本发明的涵盖范围。

Claims (18)

1.一种制作半导体元件的方法，其特征在于，包含：
形成栅极结构于基底上；
形成外延层于该栅极结构旁；以及
形成第一遮盖层于该外延层上，其中该第一遮盖层上表面包含V形。
2.如权利要求1所述的方法，另包含：
形成间隙壁于该栅极结构旁；以及
形成该外延层于该间隙壁旁。
3.如权利要求1所述的方法，其中该外延层包含第二遮盖层，且该第一遮盖层设于该第二遮盖层上。
4.如权利要求3所述的方法，其中该第二遮盖层上表面高于该基底上表面。
5.如权利要求3所述的方法，其中该第二遮盖层下表面切齐该基底上表面。
6.如权利要求3所述的方法，其中该第一遮盖层以及该第二遮盖层包含不同材料。
7.如权利要求1所述的方法，其中该外延层以及该第一遮盖层包含不同材料。
8.如权利要求1所述的方法，其中该第一遮盖层下表面高于该基底上表面。
9.如权利要求1所述的方法，其中该第一遮盖层上表面高于该栅极结构的一半高度。
10.一种半导体元件，其特征在于，包含：
栅极结构，设于基底上；
外延层，设于该栅极结构旁；以及
第一遮盖层，设于该外延层上，其中该第一遮盖层顶表面包含V形。
11.如权利要求10所述的半导体元件，另包含：
间隙壁，设于该栅极结构旁；以及
该外延层设于该间隙壁旁。
12.如权利要求10所述的半导体元件，其中该外延层包含第二遮盖层，且该第一遮盖层设于该第二遮盖层上。
13.如权利要求12所述的半导体元件，其中该第二遮盖层上表面高于该基底上表面。
14.如权利要求12所述的半导体元件，其中该第二遮盖层下表面切齐该基底上表面。
15.如权利要求12所述的半导体元件，其中该第一遮盖层以及该第二遮盖层包含不同材料。
16.如权利要求10所述的半导体元件，其中该外延层以及该第一遮盖层包含不同材料。
17.如权利要求10所述的半导体元件，其中该第一遮盖层下表面高于该基底上表面。
18.如权利要求10所述的半导体元件，其中该第一遮盖层上表面高于该栅极结构的一半高度。
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