CN103107091B - 一种半导体结构及其制造方法 - Google Patents
一种半导体结构及其制造方法 Download PDFInfo
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- CN103107091B CN103107091B CN201110362350.9A CN201110362350A CN103107091B CN 103107091 B CN103107091 B CN 103107091B CN 201110362350 A CN201110362350 A CN 201110362350A CN 103107091 B CN103107091 B CN 103107091B
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Classifications
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- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
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- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28158—Making the insulator
- H01L21/28167—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation
- H01L21/28185—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation with a treatment, e.g. annealing, after the formation of the gate insulator and before the formation of the definitive gate conductor
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- H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
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- H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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- H01L29/7834—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's with a non-planar structure, e.g. the gate or the source or the drain being non-planar
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
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- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Physics & Mathematics (AREA)
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Abstract
本发明提供一种半导体结构的制造方法和相应的半导体器件。在替代栅工艺中通过在源漏区上方形成掺杂多晶硅层,形成贯穿层间介质层(300)和所述非晶硅层(251)的接触孔(310),所述接触孔(310)至少部分暴露所述源/漏区(110),并在所述源/漏区的暴露区域和接触孔在非晶硅层中的侧壁表面形成接触层,降低了所述源/漏区的接触电阻。由于接触层在对高K介质层进行退火后形成,所以避免了金属硅化物层在高温下被破坏。
Description
技术领域
本发明涉及半导体制造技术,尤其涉及一种半导体结构及其制造方法。
背景技术
金属氧化物半导体场效应晶体管(Metal-Oxide-SemiconductorField-EffectTransistor,MOSFET)是一种可以广泛应用在数字电路和模拟电路中的晶体管。当MOSFET的栅介质层由高K介质材料构成时,可以有效地减小栅极漏电流,但是在最初形成高K栅介质层时,高K栅介质层的分子结构可能会稍有缺陷。为了修复该缺陷,需要在较高的温度(600℃-800℃)下对其进行退火。此外,对高K栅介质层进行退火还可以提高晶体管的可靠性。在替代栅工艺中,沉积高K栅介质层通常在去除伪栅之后进行,例如已经沉积了层间介质层之后。如果此时已经形成源漏区的金属硅化物,由于对高K介质层进行退火需要高温,则金属硅化物层在高温下结构会发生变化,从而导致金属硅化物层电阻率的增加,进而降低晶体管的性能。
在现有技术美国专利申请US2007/0141798A1中提出一种在替代栅工艺中可以对高K栅介质层进行退火但又不破坏金属硅化物层的方法,该方法步骤如下:
在衬底上形成具有牺牲栅极的晶体管;在衬底上沉积第一层间介质层;移除所述牺牲栅极形成栅沟槽;在所述栅沟槽中沉积形成高K介电层;对所述高K介电层进行退火;在所述栅沟槽中沉积金属层;在所述第一层间介质层和所述晶体管上沉积第二层间介质层;刻蚀所述第一层间介质层和所述第二层间介质层至源极和漏极分别形成第一接触沟槽和第二接触沟槽;在所述第一接触沟槽和所述第二接触沟槽中沉积第二金属层;对所述第二金属层进行退火,在所述源极和漏极形成金属硅化物层;以及沉积第三金属层填充所述第一接触沟槽和所述第二接触沟槽。
由于在对高K介质层进行退火后形成接触层(如金属硅化物层),所以避免了金属硅化物层在高温下被破坏。
但是,上述方法虽然能在对高K栅介质层进行退火时不破坏金属硅化物层,但是该方法的限制是只能在接触沟槽与源/漏区之间形成金属硅化物层,在源/漏区表面覆盖金属硅化物的区域面积有限,由此不能充分地降低该晶体管的金属硅化物层的接触电阻。因此,如何降低接触层(如金属硅化物层)的接触电阻,就成了亟待解决的问题。
发明内容
本发明的目的之一是提供一种半导体结构及其制造方法,利于减小源/漏区接触层(如金属硅化物层)的接触电阻。
根据本发明的一个方面,提供一种半导体结构的制造方法,该方法包括以下步骤:
a)提供衬底;
b)在所述衬底上形成伪栅堆叠、附着于所述伪栅堆叠侧壁的侧墙、以及位于所述伪栅堆叠两侧的源/漏区,其中所述伪栅堆叠至少包括第一栅极介质层和伪栅极;
c)在所述源/漏区表面形成与所述源/漏区同型掺杂的非晶硅层;
d)形成覆盖所述掺杂非晶硅层以及伪栅堆叠的层间介质层;
e)去除所述层间介质层的一部分以暴露所述伪栅堆叠;
f)去除所述伪栅堆叠以形成开口,在所述开口内填充第二栅介质层和所述第一导电材料,或者去除所述伪栅堆叠在第一栅极介质层以上的部分以形成开口,在所述开口内填充所述第一导电材料,以形成栅堆叠结构;
g)形成贯穿层间介质层和所述非晶硅层的接触孔,所述接触孔至少部分暴露所述源/漏区;
h)在所述源/漏区的暴露区域和接触孔在非晶硅层中的侧壁表面形成接触层;
i)在所述接触孔中填充第二导电材料,形成接触塞。
本发明另一方面还提出一种半导体结构,该半导体结构包括:
衬底;
形成于所述衬底之上的栅堆叠结构;
形成于所述衬底之中,且位于所述栅堆叠结构两侧的源/漏区;
覆盖所述源/漏区的非晶硅层;
覆盖所述非晶硅层和所述栅堆叠结构的层间介质层;以及
贯穿层间介质层以及所述非晶硅层并与所述源/漏区电连接的,由第二导电材料构成的接触塞,其中:
在所述接触塞与所述源/漏区以及所述非晶硅层之间存在接触层。
本发明在源/漏区和非晶硅层表面形成接触层,接触层的金属硅化物不需要经受对高K栅介质层的高温处理,所以生成时可以控制其厚度比需要经受高温处理时的高,从而降低了源/漏区金属硅化物层的接触电阻;同时可增加在源/漏区表面覆盖接触层的面积,也利于减小源/漏区接触电阻。同时由于非晶硅层的存在,使得源/漏区与接触层的接触面积增大,可以进一步降低接触电阻。与现有技术相比,有明显的进步和提高。
附图说明
通过阅读参照以下附图所作的对非限制性实施例所作的详细描述,本发明的其它特征、目的和优点将会变得更明显:
图1为根据本发明的半导体结构制造方法的流程图;
图2至图13为根据本发明的一个优选实施例按照图1所示流程制造半导体结构的各个阶段的剖面示意图。
附图中相同或相似的附图标记代表相同或相似的部件。
具体实施方式
下面详细描述本发明的实施例,所述实施例的示例在附图中示出。下面通过参考附图描述的实施例是示例性的,仅用于解释本发明,而不能解释为对本发明的限制。
下文的公开提供了许多不同的实施例或例子用来实现本发明的不同结构。为了简化本发明的公开,下文中对特定例子的部件和设置进行描述。当然,它们仅仅为示例,并且目的不在于限制本发明。此外,本发明可以在不同例子中重复参考数字和/或字母。这种重复是为了简化和清楚的目的,其本身不指示所讨论各种实施例和/或设置之间的关系。此外,本发明提供了各种特定的工艺和材料的例子,但是本领域技术人员可以意识到其他工艺的可应用性和/或其他材料的使用。应当注意,在附图中所图示的部件不一定按比例绘制。本发明省略了对公知组件和处理技术及工艺的描述以避免不必要地限制本发明。
下面,将结合图2至图13对图1中形成半导体结构的方法进行具体地描述。
参考图1和图2,在步骤S101中,提供衬底100。
在本实施例中,衬底100包括硅衬底(例如硅晶片)。根据现有技术公知的设计要求(例如P型衬底或者N型衬底),衬底100可以包括各种掺杂配置。其他实施例中衬底100还可以包括其他基本半导体,例如锗。或者,衬底100可以包括化合物半导体(如III-V族材料),例如碳化硅、砷化镓、砷化铟。典型地,衬底100可以具有但不限于约几百微米的厚度,例如可以在400um-800um的厚度范围内。
特别地,可以在衬底100中形成隔离区,例如浅沟槽隔离(STI)结构120,以便电隔离相邻的场效应晶体管器件。
参考图1和图2,在步骤S102中,在衬底100上形成伪栅堆叠、在所述伪栅堆叠侧壁形成侧墙240、以及位于所述伪栅堆叠两侧的源/漏区110,其中所述伪栅堆叠包括第一栅介质层210、伪栅极220和覆盖层230。
在本实施例中,在形成伪栅堆叠时,首先在衬底100上形成第一栅介质层210,在本实施例中,所述第一栅介质层210的材料可以是氧化硅、氮化硅或其组合形成,在其他实施例中,也可以是高K介质,例如,HfO2、HfSiO、HfSiON、HfTaO、HfTiO、HfZrO、Al2O3、La2O3、ZrO2、LaAlO中的一种或其组合,其厚度可以为2-10nm。而后,在所述第一栅介质层210上通过沉积例如Poly-Si、Poly-SiGe、非晶硅,和/或,掺杂或未掺杂的氧化硅及氮化硅、氮氧化硅、碳化硅,甚至金属形成伪栅极220,其厚度可以为10-80nm。最后,在伪栅极220上形成覆盖层230,例如通过沉积氮化硅、氧化硅、氮氧化硅、碳化硅及其组合形成,用以保护伪栅极220的顶部区域,防止伪栅极220的顶部区域在后续形成接触层的工艺中与沉积的金属层发生反应。在其他实施例中,也可以不形成覆盖层230。通过光刻工艺构图,并利用刻蚀工艺刻蚀上述沉积的多层结构后,形成伪栅堆叠。在另一个实施例中,伪栅堆叠也可以没有第一栅介质层210,而是在后续的替代栅工艺中除去伪栅堆叠后形成栅介质层。
形成所述伪栅堆叠后,在所述伪栅堆叠的侧壁上形成侧墙240,用于将栅极隔离。侧墙240可以由氮化硅、氧化硅、氮氧化硅、碳化硅及其组合,和/或其他合适的材料形成。侧墙240可以具有多层结构,且对于相邻的两层,其材料可以不同。侧墙240可以通过包括沉积刻蚀工艺形成,其厚度范围可以是10nm-100nm,如30nm、50nm或80nm。
源/漏区110位于伪栅堆叠两侧,可以通过向衬底100中注入P型或N型掺杂物或杂质而形成,例如,对于PMOS来说,源/漏区110可以是P型掺杂的SiGe;对于NMOS来说,源/漏区110可以是N型掺杂的Si。源/漏区110可以由包括光刻、离子注入、扩散和/或其他合适工艺的方法形成,利用通常的半导体加工工艺和步骤,对所述半导体结构进行退火,以激活源/漏区110中的掺杂,退火可以采用包括快速退火、尖峰退火等其他合适的方法形成。在本实施例中,源/漏区110在衬底100内部,在其他一些实施例中,源/漏区110可以是通过选择性外延生长所形成的提升的源漏极结构,其外延部分的顶部高于伪栅堆叠底部(本说明书中所指的伪栅堆叠底部意指伪栅堆叠与衬底100的交界面)。
参考图1、图3和图4,在步骤S103中,在所述源/漏区110表面形成与所述源/漏区同型掺杂的非晶硅层251。具体地,如图3所示,首先沉积一层非晶硅层250均匀覆盖所述衬底100表面,如图所示覆盖了伪栅堆叠、侧墙240以及源/漏区110。非晶硅层250可以通过化学气相沉积(Chemicalvapordeposition,CVD)、等离子体增强CVD、高密度等离子体CVD、ALD(原子层淀积)、等离子体增强原子层淀积(PEALD)、脉冲激光沉积(PLD)或其他合适的方法形成。非晶硅层250的厚度可以是几纳米到几十纳米。之后对非晶硅层250进行掺杂,如果源/漏区是P型掺杂,那么非晶硅层250也进行P型掺杂,如果源/漏区是N型掺杂,那么非晶硅层250也进行N型掺杂,保持非晶硅层250与源/漏区掺杂类型的一致。最后在非晶硅层250上覆盖光刻胶,光刻构图后刻蚀去除源/漏区110上方以外的非晶硅层250,得到如图4所示的仅存在于源/漏区110上方的掺杂非晶硅层251。
需强调的是,此时,在覆盖非晶硅层250之前,还可以去除至少部分所述侧墙240。如图13所示,在后续步骤中制作接触塞时,可以增大接触孔的可选择范围。接触孔越大,源/漏区与接触层111的接触面积就越大,相应可以减小源/漏区与接触层111的接触电阻。
参考图1和图4,在步骤S104中,形成覆盖所述掺杂非晶硅层(251)以及伪栅堆叠的层间介质层300。所述层间介质层300可以通过化学气相沉淀(CVD)、等离子体增强CVD、高密度等离子体CVD、旋涂和/或其他合适的工艺等方法形成。所述层间介质层300的材料可以包括氧化硅(USG)、掺杂的氧化硅(如氟硅玻璃、硼硅玻璃、磷硅玻璃、硼磷硅玻璃)、低k电介质材料(如黑钻石、coral等)中的一种或其组合。所述层间介质层300的厚度范围可以是40nm-150nm,如80nm、100nm或120nm,且可以具有多层结构(相邻两层间,材料可以不同)。
参考图1和图5,在步骤S105中,去除所述层间介质层300的一部分以暴露所述伪栅堆叠。
在本实施例中,执行替代栅工艺。参考图5,对层间介质层300和伪栅堆叠进行平坦化处理以暴露伪栅极220的上表面。例如,可以通过化学机械抛光(CMP)的方法去除层间介质层300,并使伪栅极220和层间介质层300的上表面齐平(本文件内,术语“齐平”意指两者之间的高度差在工艺误差允许的范围内)。
参考图1,图6至图9,在步骤S106中,去除所述伪栅堆叠以形成开口260,在所述开口260内填充第二栅介质层和所述第一导电材料,或者去除所述伪栅堆叠在第一栅极介质层以上的部分以形成开口,在所述开口内填充所述第一导电材料,以形成栅堆叠结构。
在本实施例中,一并去除伪栅极220和第一栅介质层210,暴露栅衬底100以形成开口260,参考图6(b)。可以使用湿法刻蚀和/或干法刻蚀的方式去除伪栅极220和第一栅介质层210。湿法刻蚀工艺包括四甲基氢氧化铵(TMAH)、氢氧化钾(KOH)或者其他合适刻蚀的溶液;干法刻蚀工艺包括六氟化硫(SF6)、溴化氢(HBr)、碘化氢(HI)、氯、氩、氦、甲烷(及氯代甲烷)、乙炔、乙烯等碳的氢化物及其组合,和/或其他合适的材料。
沉积栅介质层270,覆盖开口260的底部以及侧墙240的内壁,参考图7。所述栅介质层270的材料可以是高K介质,例如,HfO2、HfSiO、HfSiON、HfTaO、HfTiO、HfZrO、Al2O3、La2O3、ZrO2、LaAlO中的一种或其组合,其厚度可以为2nm-10nm,如5nm或8nm。所述栅介质层270可以通过CVD或者原子层沉积(ALD)的工艺来形成。所述栅介质层270还可以具有多层结构,包括具有上述材料的两个以上的层。
形成所述栅介质层270后,进一步进行退火,以提高半导体结构的性能,退火的温度范围为600℃至800℃。退火后,在所述栅介质层270上通过沉积第一导电材料的方式形成金属栅极280,参考图8。对于NMOS,所述第一导电材料可以是TaC、TiN、TaTbN、TaErN、TaYbN、TaSiN、HfSiN、MoSiN、RuTax、NiTax中的一种或其组合,对于PMOS,所述第一导电材料可以是MoNx,TiSiN,TiCN,TaAlC,TiAlN,TaN,PtSix,Ni3Si,Pt,Ru,Ir,Mo,HfRu,RuOx;其厚度可以为10nm-80nm,如30nm或50nm。其中,金属栅极280也可以具有多层结构,包括具有上述材料的两个以上的层。
在其他实施例中,当所述第一栅介质层210的材料为高K介质时,例如,HfO2、HfSiO、HfSiON、HfTaO、HfTiO、HfZrO、Al2O3、La2O3、ZrO2、LaAlO中的一种或其组合,也可以只去除所述伪栅极220以形成开口260,参考图6(a)。接着,对所述第一栅介质层210进行高温退火,以修整在形成第一导电材料之前已形成的结构,然后再形成金属栅极280,其中,高温退火与形成金属栅极的工艺与上述形成所述栅介质层270后所执行的工艺相同,在此不再赘述。
最后,执行CMP平坦化处理,使所述金属栅极280与层间介质层300的上表面齐平,形成栅堆叠结构,参考图9。
参考图1和图11,在步骤S107中,形成贯穿层间介质层300和所述非晶硅层251的接触孔310,所述接触孔310至少部分暴露所述源/漏区110;在本实施例中,先刻蚀层间介质层300,再蚀刻掺杂非晶硅层251,直至暴露源/漏区110,形成接触孔310。
刻蚀之前先在层间介质层300和金属栅极280上覆盖一层光刻胶层,对所述光刻胶层进行曝光构图,形成小孔,对应要形成接触孔310的位置。在本实施例中,使用刻蚀的方法对层间介质层300和掺杂非晶硅层251分别进行刻蚀并停止于源/漏区110与掺杂非晶硅层251的接触面上,以形成接触孔310。其中可以使用不同的刻蚀工艺和/或不同的刻蚀剂来刻蚀层间介质层300和掺杂非晶硅层251。例如,在非晶硅层较薄的情况下,可以使用干法刻蚀层间介质层300并使用湿法刻蚀掺杂非晶硅层251。光刻胶层的材料可以是烯类单体材料、含有叠氮醌类化合物的材料或聚乙烯月桂酸酯材料,当然也可以根据具体的制造需要选择合适的材料。刻蚀后形成的接触孔310可以具有上大下小的锥形结构。
在本发明的实施例中,可以对刻蚀的深度进行控制。具体地,在刻蚀掺杂非晶硅层251时,可以减少或者加大刻蚀时间;减少刻蚀时间使得接触孔310的底部仅仅到达非晶硅层内部,加大刻蚀时间使得接触孔310的底部进入所述源/漏区的内部,从而进一步增大了源/漏区的暴露面积,使得后续操作能够进一步减小源/漏区与金属硅化物层之间的接触电阻。
可选地,在形成接触孔310之前,在层间介质层300和金属栅极280上沉积顶层400,参考图10。所述顶层400的材料可以是氮化硅、氧化物或其组合,通过CVD、等离子体增强CVD、高密度等离子体CVD、旋涂或其他合适的方法形成在层间介质层300和金属栅极280之上。在该半导体结构形成的后续过程中,顶层400可以用来保护金属栅极280不受到破坏。此时,所述顶层材料与所述层间介质层材料需不同。例如,在后续工序中,向接触孔310内沉积金属层形成金属硅化物层后,通过选择性刻蚀去除未反应的金属层时,顶层400可以有效地防止金属栅极280被刻蚀。
在本发明的实施例中,如果沉积了顶层400,则形成接触孔310的刻蚀需要进行相应调整,例如,用不同的刻蚀气体刻蚀顶层400和层间介质层310。
参考图1和图12,在步骤S108中,在所述源/漏区110的暴露区域和接触孔310在非晶硅层251中的侧壁表面形成接触层111。可以通过金属溅镀方式或化学气相沉积法,在接触孔310的底部形成金属层。在本实施例中,所述金属层的材料可以是Ni或者NiPt,厚度例如在10nm至25nm之间,经过退火与硅发生反应后所形成的所述金属硅化物层111为NiSi或者Ni(Pt)Si2-y。在其他实施例中,可以采用其他可行的金属作为金属层。然后,对该半导体结构进行退火,退火可以采用包括快速退火、尖峰退火等其他合适的方法实施,使沉积的金属层的与源/漏区110的暴露区域和接触孔310在非晶硅层251中的侧壁表面相接触的部分与硅反应形成金属硅化物层111。
如图12所示,在所述源/漏区110的暴露区域以及接触孔310在非晶硅层251中的侧壁表面形成了所述金属硅化物层111。不同的金属层厚度和材料,在不同温度下形成的金属硅化物层111在电阻率的表现上截然不同,通过分析这种关系,确定出金属层的厚度以及生成的金属硅化物层的厚度,以保证电阻率处于相对较小的水平上。
参考图1和图13,最后,执行步骤S109,在所述接触孔310中填充接触金属(文中也称为“第二导电材料”),形成接触塞320。所述接触金属可以是W、TiAl、Al等金属或合金。可选地,在向所述接触孔310中填充接触金属之前,可以通过ALD、CVD、PVD等沉积工艺先在接触孔310整个内壁和底部沉积一层衬层(未示出),所述衬层的材料可以是Ti、TiN、Ta、TaN或其组合,其厚度的范围是5nm-20nm,如10nm或15nm。填充接触金属后,对所述接触金属进行CMP平坦化处理,使接触金属的上表面与层间介质层300的上表面齐平。
随后按照常规半导体制造工艺的步骤完成该半导体器件的制造。
在上述步骤完成后,在所述半导体结构中,形成的金属硅化物不需要经受对高K栅介质层的高温处理,生成时可以控制其厚度,降低了源/漏区与金属硅化物层之间的接触电阻。除此之外,由于非晶硅层的存在,使得所形成的接触层111的面积增大(不仅存在于源/漏区110的暴露区域上,而且存在于接触孔310在非晶硅层251中的侧壁表面上),所以本发明提供的半导体结构的制造方法,可以有效地减小源/漏区与接触塞之间的接触电阻,利于提高半导体器件的性能。
为了更清楚地理解根据上述半导体结构的制造方法所形成的半导体结构,下面根据图13对所述半导体结构进行说明。
参考图13,图13为完成图1中所示的步骤后最终形成的半导体结构的剖面图。在本实施例中,所述半导体结构包括:衬底(100);形成于所述衬底(100)之上的栅堆叠结构;形成于所述衬底(100)之中,且位于所述栅堆叠结构两侧的源/漏区(110);覆盖所述源/漏区(110)的非晶硅层(251);覆盖所述非晶硅层(251)和所述栅堆叠结构的层间介质层(300);以及贯穿层间介质层(300)以及所述非晶硅层(251)并与所述源/漏区(110)电连接的,由第二导电材料构成的接触塞(320)。其中在所述接触塞(320)与所述源/漏区(110)以及所述非晶硅层(251)之间存在接触层(111)。
所述接触层111由金属硅化物组成,包括NiSi或者Ni(Pt)Si2-y中的一种,其厚度的范围可以在15nm-35nm之间。
在又一个实施例中,接触塞320的底部延伸至源/漏区内,从而进一步增大金属硅化物层111的面积,减小源/漏区与金属硅化物层之间的接触电阻。
其中,对半导体结构各实施例中各部分的结构组成、材料及形成方法等均可与前述半导体结构形成的方法实施例中描述的相同,不在赘述。
虽然关于示例实施例及其优点已经详细说明,应当理解在不脱离本发明的精神和所附权利要求限定的保护范围的情况下,可以对这些实施例进行各种变化、替换和修改。对于其他例子,本领域的普通技术人员应当容易理解在保持本发明保护范围内的同时,工艺步骤的次序可以变化。
此外,本发明的应用范围不局限于说明书中描述的特定实施例的工艺、机构、制造、物质组成、手段、方法及步骤。从本发明的公开内容,作为本领域的普通技术人员将容易地理解,对于目前已存在或者以后即将开发出的工艺、机构、制造、物质组成、手段、方法或步骤,其中它们执行与本发明描述的对应实施例大体相同的功能或者获得大体相同的结果,依照本发明可以对它们进行应用。因此,本发明所附权利要求旨在将这些工艺、机构、制造、物质组成、手段、方法或步骤包含在其保护范围内。
Claims (10)
1.一种半导体结构的制造方法,该方法包括以下步骤:
a)提供衬底(100);
b)在所述衬底(100)上形成伪栅堆叠、附着于所述伪栅堆叠侧壁的侧墙(240)、以及位于所述伪栅堆叠两侧的源/漏区(110),其中所述伪栅堆叠至少包括第一栅极介质层和伪栅极(220);
c)在所述源/漏区(110)表面形成与所述源/漏区同型掺杂的非晶硅层(251);其中,形成所述掺杂非晶硅层(251)的步骤包括:
形成非晶硅层(250),覆盖伪栅堆叠、附着于所述伪栅堆叠侧壁的侧墙(240)、以及位于所述伪栅堆叠两侧的源/漏区(110);
对所述非晶硅层(250)进行掺杂,其掺杂类型与源/漏区的相同;
对所述非晶硅层(250)进行构图,保留源/漏区上方的非晶硅层,去除其余部分的非晶硅层,形成所述掺杂非晶硅层(251);
d)形成覆盖所述掺杂非晶硅层(251)以及伪栅堆叠的层间介质层(300);
e)去除所述层间介质层(300)的一部分以暴露所述伪栅堆叠;
f)去除所述伪栅堆叠以形成开口,在所述开口(260)内填充第二栅介质层和第一导电材料(280),以形成栅堆叠结构,或者去除所述伪栅堆叠在第一栅极介质层以上的部分以形成开口,在所述开口(260)内填充第一导电材料(280),以形成栅堆叠结构;
g)形成贯穿层间介质层(300)和所述非晶硅层(251)的接触孔(310),所述接触孔(310)至少部分暴露所述源/漏区(110);
h)在所述源/漏区(110)的暴露区域和接触孔(310)在非晶硅层(251)中的侧壁表面形成接触层(111);
i)在所述接触孔中填充第二导电材料,形成接触塞(320)。
2.根据权利要求1所述的方法,其中,在所述步骤f)和所述步骤g)之间还执行:
j)形成覆盖所述栅堆叠结构和所述层间介质层(301)的顶层(400),所述顶层(400)材料与所述层间介质层(301)材料不同。
3.根据权利要求1所述的方法,其中,所述接触层(111)包括NiSi或者Ni(Pt)Si2-y中的一种。
4.根据权利要求1所述的方法,其中,所述步骤h)包括:
形成覆盖所述源/漏区(110)的暴露区域和接触孔(310)的侧壁的金属层;
执行第一退火操作,使所述金属层与所述源/漏区(110)的暴露区域和接触孔(310)在非晶硅层(251)中的侧壁表面反应,形成接触层(111);
去除未反应的所述金属层。
5.根据权利要求4所述的方法,其中:
所述金属层的材料包括Ni或者NiPt中的一种。
6.根据权利要求4所述的方法,其中:
如果所述金属层的材料为NiPt,则NiPt中Pt的含量小于5%。
7.根据权利要求4或5所述的方法,其中:
所述金属层的厚度在10nm至25nm的范围内。
8.根据权利要求4或5所述的方法,其中:
所述退火温度在500℃~600℃之间。
9.根据权利要求4所述的方法,其中所述接触层(111)的厚度在15nm至35nm的范围内。
10.根据权利要求1所述的方法,其中,在所述步骤f)中,在填充所述第一导电材料(280)之前还包括:
进行第二退火操作,以修整在填充第一导电材料之前已形成的结构。
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- 2011-11-15 CN CN201110362350.9A patent/CN103107091B/zh active Active
- 2011-12-02 WO PCT/CN2011/083331 patent/WO2013071656A1/zh active Application Filing
- 2011-12-02 US US13/989,808 patent/US20130240990A1/en not_active Abandoned
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US6033963A (en) * | 1999-08-30 | 2000-03-07 | Taiwan Semiconductor Manufacturing Company | Method of forming a metal gate for CMOS devices using a replacement gate process |
CN101790778A (zh) * | 2005-12-20 | 2010-07-28 | 英特尔公司 | 高k/金属栅极晶体管的接触部中的硅化物层 |
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