CN107275210B - 半导体元件及其制作方法 - Google Patents

半导体元件及其制作方法 Download PDF

Info

Publication number
CN107275210B
CN107275210B CN201610209916.7A CN201610209916A CN107275210B CN 107275210 B CN107275210 B CN 107275210B CN 201610209916 A CN201610209916 A CN 201610209916A CN 107275210 B CN107275210 B CN 107275210B
Authority
CN
China
Prior art keywords
layer
substrate
epitaxial layer
epitaxial
forming
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201610209916.7A
Other languages
English (en)
Other versions
CN107275210A (zh
Inventor
许智凯
傅思逸
洪裕祥
程伟麒
郑志祥
杨宗穆
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
United Microelectronics Corp
Original Assignee
United Microelectronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by United Microelectronics Corp filed Critical United Microelectronics Corp
Priority to CN201610209916.7A priority Critical patent/CN107275210B/zh
Priority to US15/144,842 priority patent/US9929234B2/en
Publication of CN107275210A publication Critical patent/CN107275210A/zh
Priority to US15/890,320 priority patent/US10546922B2/en
Application granted granted Critical
Publication of CN107275210B publication Critical patent/CN107275210B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66636—Lateral single gate silicon transistors with source or drain recessed by etching or first recessed by etching and then refilled
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0642—Isolation within the component, i.e. internal isolation
    • H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
    • H01L29/0653—Dielectric regions, e.g. SiO2 regions, air gaps adjoining the input or output region of a field-effect device, e.g. the source or drain region
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System
    • H01L21/28518—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System the conductive layers comprising silicides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76805—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics the opening being a via or contact hole penetrating the underlying conductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76853—Barrier, adhesion or liner layers characterized by particular after-treatment steps
    • H01L21/76855—After-treatment introducing at least one additional element into the layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76895—Local interconnects; Local pads, as exemplified by patent document EP0896365
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
    • H01L23/485—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/535—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including internal interconnections, e.g. cross-under constructions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0843—Source or drain regions of field-effect devices
    • H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/41791—Source or drain electrodes for field effect devices for transistors with a horizontal current flow in a vertical sidewall, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
    • H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
    • H01L29/7848—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate the means being located in the source/drain region, e.g. SiGe source and drain
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H01L29/7851—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET with the body tied to the substrate

Abstract

本发明公开一种半导体元件及其制作方法。该制作方法包括：首先提供一基底，然后形成一栅极结构于基底上，形成一凹槽于栅极结构两侧的基底中，形成一外延层于凹槽内，其中外延层的上表面低于基底的上表面，之后再形成一遮盖层于外延层上，其中遮盖层的上表面高于基底的上表面。

Description

半导体元件及其制作方法
技术领域
本发明涉及一种制作半导体元件的方法，尤其是涉及一种于外延层上形成遮盖层的方法。
背景技术
为了能增加半导体结构的载流子迁移率，可以选择对于栅极通道施加压缩应力或是伸张应力。举例来说，若需要施加的是压缩应力，现有技术常利用选择性外延成长(selective epitaxial growth,SEG)技术于一硅基底内形成晶格排列与该硅基底相同的外延结构，例如硅锗(silicon germanium,SiGe)外延结构。利用硅锗外延结构的晶格常数(lattice constant)大于该硅基底晶格的特点，对P型金氧半导体晶体管的通道区产生应力，增加通道区的载流子迁移率(carrier mobility)，并用于增加金氧半导体晶体管的速度。反之，若是N型半导体晶体管则可选择于硅基底内形成硅碳(silicon carbide,SiC)外延结构，对栅极通道区产生伸张应力。
现今以外延成长方式形成外延层的晶体管过程中通常会先以蚀刻拔除栅极结构上的硬掩模再进行后续接触插塞制作工艺。然而在去除硬掩模的过程中所使用的蚀刻溶液容易损害外延层的表面并影响元件运作。因此，如何改良现有制作工艺技术以解决现有瓶颈即为现今一重要课题。
发明内容
本发明较佳实施例公开一种制作半导体元件的方法。首先提供一基底，然后形成一栅极结构于基底上，形成一凹槽于栅极结构两侧的基底中，形成一外延层于凹槽内，其中外延层的上表面低于基底的上表面，之后再形成一遮盖层于外延层上，其中遮盖层的上表面高于基底的上表面。
本发明另一实施例公开一种半导体元件，其包含一基底；一栅极结构设于基底上；一外延层设于栅极结构两侧的基底中以及一遮盖层设于外延层上，其中该遮盖层为V型。
附图说明
图1至图5为本发明较佳实施例制作一半导体元件的方法示意图；
图6为本发明一实施例的一半导体元件结构示意图；
图7为本发明一实施例的一半导体元件结构示意图；
图8为本发明一实施例的一半导体元件结构示意图。
主要元件符号说明
12      基底                     14     栅极结构
16      栅极介电层               18     栅极材料层
20      硬掩模                   22     间隙壁
24      轻掺杂漏极               26     凹槽
28      缓冲层                   30     外延层
32      V型轮廓                  34     遮盖层
36      接触洞蚀刻停止层         38     层间介电层
40      高介电常数介电层         42     功函数金属层
44      低阻抗金属层             46     硬掩模
48      接触插塞                 50     第一金属层
52      第二金属层               54     金属硅化物
56      第三金属层               58     垂直部
60      凸出部
具体实施方式
请参照图1至图5，图1至图5为本发明较佳实施例制作一半导体元件的方法示意图。如图1所示，首先提供一基底12，然后于基底上形成至少一栅极结构14。在本实施例中，形成栅极结构14的方式较佳依序形成一栅极介电层、一栅极材料层以及一硬掩模于基底12上，并利用一图案化光致抗蚀剂(图未示)当作掩模进行一图案转移制作工艺，以单次蚀刻或逐次蚀刻步骤，去除部分硬掩模、部分栅极材料层以及部分栅极介电层，然后剥除图案化光致抗蚀剂，以于基底12上形成至少一由图案化的栅极介电层16、图案化的栅极材料层18以及图案化的硬掩模20所构成的栅极结构14。
在本实施例中，基底12例如是硅基底、外延硅基底、碳化硅基底或硅覆绝缘(silicon-on-insulator,SOI)基底等的半导体基底，但不以此为限。栅极介电层16可包含二氧化硅(SiO2)、氮化硅(SiN)或高介电常数(high dielectric constant,high-k)材料；栅极材料层18可包含金属材料、多晶硅或金属硅化物(silicide)等导电材料；硬掩模20可选自由氧化硅、氮化硅、碳化硅(SiC)以及氮氧化硅(SiON)所构成的群组，但不局限于此。
此外，在一实施例中，还可选择预先在基底12中形成多个掺杂阱(未绘示)或多个作为电性隔离之用的浅沟槽隔离(shallow trench isolation,STI)。并且，本实施例虽以平面型晶体管为例，但在其他变化实施例中，本发明的半导体制作工艺也可应用于非平面晶体管，例如是鳍状晶体管(Fin-FET)，此时，图1所标示的基底12即相对应代表为形成于一基底12上的鳍状结构。
然后在栅极结构14侧壁形成至少一间隙壁22，并选择性进行一轻掺杂离子注入，利用约930℃温度进行一快速升温退火制作工艺活化植入基底12的掺质，以于间隙壁22两侧的基底12中形成一轻掺杂漏极24。在本实施例中，间隙壁22可为单一间隙壁或复合式间隙壁，例如可细部包含一偏位间隙壁(图未示)以及一主间隙壁(图未示)，偏位间隙壁与主间隙壁较佳包含不同材料，且间隙壁可选自由氧化硅、氮化硅、氮氧化硅以及氮碳化硅所构成的群组，但不局限于此。
如图2所示，随后进行一干蚀刻及/或湿蚀刻制作工艺，利用栅极结构14与间隙壁22作为蚀刻掩模，沿着间隙壁22向下单次或多次蚀刻基底12，以于栅极结构14两侧的基底12中形成一凹槽26。
如图3所示，接着依序形成一缓冲层28以及一外延层30于凹槽26内，其中缓冲层28较佳覆盖凹槽26表面且较佳具有均一厚度。外延层30则填满大部分凹槽26，且外延层30中可具有掺质而形成一源极/漏极区域。其中所填入的外延层30上表面包含一V型轮廓32，且V型轮廓32略低于基底12上表面。之后再形成一遮盖层34于外延层30上，并使遮盖层34上表面高于基底12上表面。需注意的是，本实施例中的遮盖层34上表面虽较佳高于基底12上表面，但依据产品需求又可控制遮盖层34上表面使其低于基底12上表面，此实施例也属本发明所涵盖的范围。
值得注意的是，在此阶段遮盖层34上表面较佳为一平坦表面，而遮盖层34下表面则与外延层30上表面同为V型，且由于遮盖层34较佳填满外延层30的V型轮廓32上的空间，因此遮盖层34本体又同时包含或呈现一三角形。
在本实施例中，缓冲层28、外延层30以及遮盖层34均较佳包含磷化硅(SiP)，其中外延层30的磷浓度较佳高于缓冲层28的磷浓度，而遮盖层34的磷浓度则较佳低于外延层30的磷浓度。换句话说，外延层30的磷浓度较佳同时高于缓冲层28与遮盖层34的磷浓度，但缓冲层28与遮盖层34之间的磷浓度并无特别限制，例如缓冲层28的磷浓度可高于遮盖层34的磷浓度，或遮盖层34的磷浓度可高于缓冲层28的磷浓度，这些均属本发明所涵盖的范围。
如图4所示，然后可选择性形成一由氮化硅所构成的接触洞蚀刻停止层(contactetch stop layer,CESL)36于基底12上并覆盖栅极结构14与遮盖层34，再形成一层间介电层38于CESL 36上。接着进行一平坦化制作工艺，例如利用化学机械研磨(chemicalmechanical polishing,CMP)去除部分层间介电层38、部分接触洞蚀刻停止层36以及硬掩模20并暴露出由多晶硅材料所构成的栅极材料层18，使栅极材料层18上表面与层间介电层38上表面齐平。
随后进行一金属栅极置换制作工艺将栅极结构14转换为金属栅极。例如可先进行一选择性的干蚀刻或湿蚀刻制作工艺，例如利用氨水(ammonium hydroxide,NH4OH)或氢氧化四甲铵(Tetramethylammonium Hydroxide,TMAH)等蚀刻溶液来去除栅极结构14中的栅极材料层18，以于层间介电层38中形成一凹槽(图未示)。之后依序形成一高介电常数介电层40以及至少包含U型功函数金属层42与低阻抗金属层44的导电层于凹槽内，并再搭配进行一平坦化制作工艺使U型高介电常数介电层40、U型功函数金属层42与低阻抗金属层44的表面与层间介电层38表面齐平。
在本实施例中，高介电常数介电层40包含介电常数大于4的介电材料，例如选自氧化铪(hafnium oxide，HfO2)、硅酸铪氧化合物(hafnium silicon oxide，HfSiO4)、硅酸铪氮氧化合物(hafnium silicon oxynitride，HfSiON)、氧化铝(aluminum oxide，Al2O3)、氧化镧(lanthanum oxide，La2O3)、氧化钽(tantalum oxide，Ta2O5)、氧化钇(yttrium oxide，Y2O3)、氧化锆(zirconium oxide，ZrO2)、钛酸锶(strontium titanate oxide，SrTiO3)、硅酸锆氧化合物(zirconium silicon oxide，ZrSiO4)、锆酸铪(hafnium zirconium oxide，HfZrO4)、锶铋钽氧化物(strontium bismuth tantalate,SrBi2Ta2O9,SBT)、锆钛酸铅(leadzirconate titanate,PbZrxTi1-xO3,PZT)、钛酸钡锶(barium strontium titanate,BaxSr1- xTiO3,BST)、或其组合所组成的群组。
功函数金属层42较佳用以调整形成金属栅极的功函数，使其适用于N型晶体管(NMOS)或P型晶体管(PMOS)。若晶体管为N型晶体管，功函数金属层42可选用功函数为3.9电子伏特(eV)～4.3eV的金属材料，如铝化钛(TiAl)、铝化锆(ZrAl)、铝化钨(WAl)、铝化钽(TaAl)、铝化铪(HfAl)或TiAlC(碳化钛铝)等，但不以此为限；若晶体管为P型晶体管，功函数金属层42可选用功函数为4.8eV～5.2eV的金属材料，如氮化钛(TiN)、氮化钽(TaN)或碳化钽(TaC)等，但不以此为限。功函数金属层42与低阻抗金属层44之间可包含另一阻障层(图未示)，其中阻障层的材料可包含钛(Ti)、氮化钛(TiN)、钽(Ta)、氮化钽(TaN)等材料。低阻抗金属层44则可选自铜(Cu)、铝(Al)、钨(W)、钛铝合金(TiAl)、钴钨磷化物(cobalttungsten phosphide，CoWP)等低电阻材料或其组合。由于依据金属栅极置换制作工艺将虚置栅极转换为金属栅极是此领域者所熟知技术，在此不另加赘述。接着可去除部分高介电常数介电层40、部分功函数金属层42与部分低阻抗金属层44形成凹槽(图未示)，然后再填入一硬掩模46于凹槽内并使硬掩模46与层间介电层38表面齐平，其中硬掩模46可选自由氧化硅、氮化硅、氮氧化硅以及氮碳化硅所构成的群组。
如图5所示，接着进行一接触插塞制作工艺搭配金属硅化物制作工艺形成一金属硅化物54于外延层30表面以及一接触插塞48电连接栅极结构14两侧的外延层30或源极/漏极区域。在本实施例中，接触插塞制作工艺可利用图案化掩模进行一蚀刻制作工艺，去除栅极结构14旁的部分层间介电层38以形成接触洞(图未示)暴露遮盖层34表面。然后依序沉积一第一金属层50与第二金属层52于接触洞中，其中第一金属层50与第二金属层52较佳共形地(conformally)形成于遮盖层34表面及接触洞的内侧侧壁。在本实施例中，第一金属层50较佳选自钛、钴、镍及铂等所构成的群组，且最佳为钛，第二金属层52则较佳包含氮化钛、氮化钽等金属化合物。
在连续沉积第一金属层50与第二金属层52之后，依序进行一第一热处理制作工艺与一第二热处理制作工艺以形成一金属硅化物54于遮盖层34上。值得注意的是，本实施例较佳在形成金属硅化物54的时候，设置于接触洞底部的第一金属层50会与部分的遮盖层34反应形成金属硅化物54，进而同时改变原本遮盖层34的形状，例如将遮盖层34原本的平坦表面以及三角形形状转变为V型，且遮盖层34的整体厚度较佳介于10埃至100埃，或更加控制在小于40埃的范围内，而所形成的V型金属硅化物54则贴附在V型的遮盖层34表面。
另外在本实施例中，第一热处理制作工艺包含一常温退火(soak anneal)制作工艺，其温度较佳介于500℃至600℃，且最佳为550℃，而其处理时间则较佳介于10秒至60秒，且最佳为30秒。第二热处理制作工艺包含一峰值退火(spike anneal)制作工艺，其温度较佳介于600℃至950℃，且最佳为600℃，而其处理较佳时间则较佳介于100毫秒至5秒，且最佳为5秒。
迨进行两次热处理制作工艺后，形成一第三金属层56并填满接触洞。在本实施例中，第三金属层56较佳包含钨，但不局限于此。最后进行一平坦化制作工艺，例如以CMP制作工艺部分去除第三金属层56、部分第二金属层52及部分第一金属层50，甚至可视制作工艺需求接着去除部分层间介电层38，以形成接触插塞48电连接遮盖层34与外延层30。至此即完成本发明较佳实施例一半导体元件的制作。
请继续参照图5，其另公开本发明较佳实施例的一半导体元件结构。如图5所示，半导体元件较佳包含至少一栅极结构14设于基底12上，一缓冲层28设于栅极结构14两侧的基底12内，一外延层30设于缓冲层28上，一遮盖层34设于外延层30上，一层间介电层38环绕栅极结构14，以及至少一接触插塞48镶嵌于层间介电层38中接触并电连接遮盖层34。其中栅极结构14较佳为一金属栅极，其更细部包含一U型高介电常数介电层40、一U型功函数金属层42以及一低阻抗金属层44。
更具体而言，外延层30上表面包含一V型轮廓32，且V型轮廓32整体略低于基底12上表面。遮盖层34较佳包含或呈现一V型，其中遮盖层34上表面较佳略高于基底12表面，且遮盖层34的整体厚度较佳介于10埃至100埃，或更加控制在小于40埃的范围内。
在本实施例中，缓冲层28、外延层30以及遮盖层34均较佳包含磷化硅(SiP)，其中外延层30的磷浓度较佳高于缓冲层28的磷浓度，而遮盖层34的磷浓度则较佳低于外延层30的磷浓度，或是外延层30的磷浓度同时高于缓冲层28与遮盖层34的磷浓度，但缓冲层28与遮盖层34之间的磷浓度并无特别限制，例如缓冲层28的磷浓度可高于遮盖层34的磷浓度，或遮盖层34的磷浓度可高于缓冲层28的磷浓度，这些均属本发明所涵盖的范围。
请参照图6，图6为本发明一实施例的一半导体元件结构示意图。如图6所示，本发明可依据前述图5形成接触插塞48时使第一金属层50与所有的遮盖层34完全反应形成金属硅化物54，且所形成的金属硅化物54较佳为V型。此实施例也属本发明所涵盖的范围。
请参照图7，图7为本发明一实施例的一半导体元件结构示意图。如图7所示，本发明可依据前述图5形成接触插塞48时使第一金属层50与部分遮盖层34反应形成金属硅化物54，而所形成的金属硅化物54较佳完全重叠遮盖层34。
请参照图8，图8为本发明一实施例的一半导体元件结构示意图。如图8所示，本发明可依据前述图5形成接触洞时更深入遮盖层34，使后续的第一金属层50与部分遮盖层34反应形成金属硅化物54。其中所形成的金属硅化物54上表面与遮盖层34上表面除了均为平整表面之外又相互切齐，另外金属硅化物又更细部包含一垂直部58连接一V型的凸出部60。
综上所述，本发明较佳于形成外延层后再形成一遮盖层于外延层表面，其中外延层上表面较佳包含一V型轮廓，遮盖层较佳为V型且与外延层的V型轮廓直接接触，且遮盖层与外延层均较佳包含磷化硅。依据本发明的较佳实施例，遮盖层的厚度较佳控制在40埃以内且遮盖层的磷浓度较佳低于外延层主体的磷浓度，其中遮盖层的设置除了可用来改善外延层上表面的V型轮廓，又可同时避免形成接触插塞时造成过多的外延层流失。
以上所述仅为本发明的较佳实施例，凡依本发明权利要求所做的均等变化与修饰，皆应属本发明的涵盖范围。

Claims (14)

1.一种制作半导体元件的方法，包含：
提供一基底；
形成一栅极结构于该基底上；
形成一凹槽于该栅极结构两侧的该基底中；
形成一缓冲层于该凹槽内；
形成一外延层于该凹槽内，其中该外延层的上表面低于该基底的上表面且不与该基底的上表面切齐，该外延层的上表面与该缓冲层的上表面共同构成一V型轮廓；
形成一遮盖层于该外延层上，其中该遮盖层为V型，该遮盖层的上表面高于该基底的上表面，该遮盖层同时接触覆盖该外延层及该缓冲层，该外延层的上表面的面积小于该遮盖层的下表面的面积，且该遮盖层与该栅极结构于垂直方向不重叠。
2.如权利要求1所述的方法，其中该缓冲层包含磷化硅。
3.如权利要求1所述的方法，其中该外延层及该遮盖层包含磷化硅。
4.如权利要求3所述的方法，其中该遮盖层的磷浓度小于该外延层的磷浓度。
5.如权利要求1所述的方法，其中形成V型的该遮盖层的方法包括：形成包含一三角形的该遮盖层。
6.如权利要求5所述的方法，另包含形成一接触插塞，接触该遮盖层并将该遮盖层的三角形转变为该V型。
7.如权利要求1所述的方法，其中该遮盖层的厚度介于10埃至100埃。
8.一种半导体元件，包含：
基底；
栅极结构，设于该基底上；
外延层，设于该栅极结构两侧的该基底中，其中该外延层的上表面低于该基底的上表面且不与该基底的上表面切齐；
缓冲层，设于该外延层及该基底之间；以及
遮盖层，设于该外延层上，其中该遮盖层为V型；
其中该外延层的上表面与该缓冲层的上表面共同构成一V型轮廓，该遮盖层同时接触覆盖该外延层及该缓冲层，该外延层的上表面的面积小于该遮盖层的下表面的面积，且该遮盖层与该栅极结构于垂直方向不重叠。
9.如权利要求8所述的半导体元件，其中该缓冲层包含磷化硅。
10.如权利要求8所述的半导体元件，其中该外延层及该遮盖层包含磷化硅。
11.如权利要求10所述的半导体元件，其中该遮盖层的磷浓度小于该外延层的磷浓度。
12.如权利要求8所述的半导体元件，其中该外延层的上表面包含一V型轮廓。
13.如权利要求8所述的半导体元件，另包含一接触插塞，接触该遮盖层。
14.如权利要求8所述的半导体元件，其中该遮盖层的厚度介于10埃至100埃。
CN201610209916.7A 2016-04-06 2016-04-06 半导体元件及其制作方法 Active CN107275210B (zh)

Priority Applications (3)

Application Number Priority Date Filing Date Title
CN201610209916.7A CN107275210B (zh) 2016-04-06 2016-04-06 半导体元件及其制作方法
US15/144,842 US9929234B2 (en) 2016-04-06 2016-05-03 Semiconductor device having a cap layer with V-shape
US15/890,320 US10546922B2 (en) 2016-04-06 2018-02-06 Method for fabricating cap layer on an epitaxial layer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201610209916.7A CN107275210B (zh) 2016-04-06 2016-04-06 半导体元件及其制作方法

Publications (2)

Publication Number Publication Date
CN107275210A CN107275210A (zh) 2017-10-20
CN107275210B true CN107275210B (zh) 2023-05-02

Family

ID=60000029

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201610209916.7A Active CN107275210B (zh) 2016-04-06 2016-04-06 半导体元件及其制作方法

Country Status (2)

Country Link
US (2) US9929234B2 (zh)
CN (1) CN107275210B (zh)

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102018100114B4 (de) * 2017-11-15 2020-07-23 Taiwan Semiconductor Manufacturing Co., Ltd. Halbleitervorrichtung und verfahren zu ihrer herstellung
KR102432894B1 (ko) * 2017-11-17 2022-08-17 삼성전자주식회사 반도체 소자
KR20190110845A (ko) * 2018-03-21 2019-10-01 삼성전자주식회사 반도체 소자
US10629739B2 (en) 2018-07-18 2020-04-21 Globalfoundries Inc. Methods of forming spacers adjacent gate structures of a transistor device
CN109524470A (zh) * 2018-10-29 2019-03-26 上海华力集成电路制造有限公司 Nmos管及其制造方法
CN111106173B (zh) * 2018-10-29 2023-06-06 联华电子股份有限公司 半导体装置及其形成方法
TWI788487B (zh) * 2018-12-21 2023-01-01 聯華電子股份有限公司 半導體元件
CN113611736B (zh) 2020-05-29 2022-11-22 联芯集成电路制造(厦门)有限公司 半导体元件及其制作方法
US20220051945A1 (en) * 2020-08-13 2022-02-17 Taiwan Semiconductor Manufacturing Co., Ltd. Embedded Stressors in Epitaxy Source/Drain Regions
US11854904B2 (en) * 2020-08-13 2023-12-26 Taiwan Semiconductor Manufacturing Co., Ltd. Different source/drain profiles for n-type FinFETs and p-type FinFETs
US11646377B2 (en) * 2020-08-21 2023-05-09 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device and method of manufacture
JP2022046155A (ja) * 2020-09-10 2022-03-23 キオクシア株式会社 半導体装置およびその製造方法

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104347412A (zh) * 2013-08-01 2015-02-11 北大方正集团有限公司 Vvmos管的制作方法及vvmos管
CN104377199A (zh) * 2013-08-16 2015-02-25 台湾积体电路制造股份有限公司 嵌入在mos器件中的锗阻挡件

Family Cites Families (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6187641B1 (en) 1997-12-05 2001-02-13 Texas Instruments Incorporated Lateral MOSFET having a barrier between the source/drain region and the channel region using a heterostructure raised source/drain region
TWI256157B (en) * 2005-09-22 2006-06-01 Epitech Technology Corp Method for manufacturing light-emitting diode
JP4345774B2 (ja) * 2006-04-26 2009-10-14 ソニー株式会社 半導体装置の製造方法
US7554110B2 (en) 2006-09-15 2009-06-30 Taiwan Semiconductor Manufacturing Company, Ltd. MOS devices with partial stressor channel
KR101438136B1 (ko) * 2007-12-20 2014-09-05 삼성전자주식회사 고전압 트랜지스터
US7834457B2 (en) * 2008-02-28 2010-11-16 International Business Machines Corporation Bilayer metal capping layer for interconnect applications
US8471307B2 (en) * 2008-06-13 2013-06-25 Texas Instruments Incorporated In-situ carbon doped e-SiGeCB stack for MOS transistor
US7994014B2 (en) * 2008-10-10 2011-08-09 Advanced Micro Devices, Inc. Semiconductor devices having faceted silicide contacts, and related fabrication methods
US8652945B2 (en) * 2011-02-08 2014-02-18 Applied Materials, Inc. Epitaxy of high tensile silicon alloy for tensile strain applications
US8426284B2 (en) * 2011-05-11 2013-04-23 United Microelectronics Corp. Manufacturing method for semiconductor structure
US9142642B2 (en) * 2012-02-10 2015-09-22 Taiwan Semiconductor Manufacturing Company, Ltd. Methods and apparatus for doped SiGe source/drain stressor deposition
US9093468B2 (en) * 2013-03-13 2015-07-28 Taiwan Semiconductor Manufacturing Company, Ltd. Asymmetric cyclic depositon and etch process for epitaxial formation mechanisms of source and drain regions
US9064893B2 (en) 2013-05-13 2015-06-23 United Microelectronics Corp. Gradient dopant of strained substrate manufacturing method of semiconductor device
US9583483B2 (en) * 2013-09-03 2017-02-28 Taiwan Semiconductor Manufacturing Company, Ltd. Source and drain stressors with recessed top surfaces
US9412656B2 (en) * 2014-02-14 2016-08-09 Taiwan Semiconductor Manufacturing Co., Ltd. Reverse tone self-aligned contact
US9543387B2 (en) * 2014-03-10 2017-01-10 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor device and manufacturing method thereof
US10084063B2 (en) * 2014-06-23 2018-09-25 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor device and manufacturing method thereof
US9601574B2 (en) * 2014-12-29 2017-03-21 Taiwan Semiconductor Manufacturing Company, Ltd. V-shaped epitaxially formed semiconductor layer
US9406680B1 (en) * 2015-02-13 2016-08-02 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device including fin structures and manufacturing method thereof
US9741829B2 (en) * 2015-05-15 2017-08-22 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device and manufacturing method thereof

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104347412A (zh) * 2013-08-01 2015-02-11 北大方正集团有限公司 Vvmos管的制作方法及vvmos管
CN104377199A (zh) * 2013-08-16 2015-02-25 台湾积体电路制造股份有限公司 嵌入在mos器件中的锗阻挡件

Also Published As

Publication number Publication date
US9929234B2 (en) 2018-03-27
US20180166532A1 (en) 2018-06-14
US10546922B2 (en) 2020-01-28
US20170294508A1 (en) 2017-10-12
CN107275210A (zh) 2017-10-20

Similar Documents

Publication Publication Date Title
CN107275210B (zh) 半导体元件及其制作方法
US8765546B1 (en) Method for fabricating fin-shaped field-effect transistor
TWI722073B (zh) 半導體元件及其製作方法
CN113659004B (zh) 半导体元件及其制作方法
CN106684041B (zh) 半导体元件及其制作方法
US20160104673A1 (en) Fin-shaped field-effect transistor with a germanium epitaxial cap and a method for fabricating the same
CN106920839B (zh) 半导体元件及其制作方法
CN116705613A (zh) 半导体元件及其制作方法
CN107026126B (zh) 半导体元件及其制作方法
US10978398B2 (en) Semiconductor device and method for fabricating the same
CN106158857B (zh) 半导体元件及其制作方法
US11545560B2 (en) Semiconductor device and method for fabricating the same
TWI814888B (zh) 一種製作半導體元件的方法
TWI690984B (zh) 半導體元件及其製作方法
US10446667B2 (en) Method for fabricating semiconductor device
CN112736079A (zh) 具有连接pmos区域栅极结构的接触插塞的半导体元件
US10978556B2 (en) Semiconductor device and method for fabricating the same
CN110828377B (zh) 一种具有不对称功函数金属层的半导体元件
CN114121660B (zh) 半导体元件及其制作方法
CN109545747B (zh) 半导体元件及其制作方法
CN116504828A (zh) 半导体元件
CN115881538A (zh) 半导体元件及其制作方法

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant