CN111106173B - 半导体装置及其形成方法 - Google Patents

半导体装置及其形成方法 Download PDF

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CN111106173B
CN111106173B CN201811267020.XA CN201811267020A CN111106173B CN 111106173 B CN111106173 B CN 111106173B CN 201811267020 A CN201811267020 A CN 201811267020A CN 111106173 B CN111106173 B CN 111106173B
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epitaxial
layer
substrate
epitaxial layer
semiconductor device
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CN111106173A (zh
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陈广修
蔡松蒝
唐启轩
游峻伟
王俞仁
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United Microelectronics Corp
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United Microelectronics Corp
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Priority to US16/205,233 priority patent/US11049971B2/en
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Priority to US17/330,443 priority patent/US11735661B2/en
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Abstract

本发明公开一种半导体装置及其形成方法，其中该半导体装置包含一基底，一栅极结构与一外延结构。该栅极结构设置在该基底上，而该外延结构则设置在该基底内，位于该栅极结构一侧。其中，该外延结构包含凸伸于该基底一顶面的一部分，该部分包含一不连续侧壁，且该不连续侧壁上的一转折点至该栅极结构之间的距离为该外延结构与该栅极结构之间相隔的最大距离。

Description

半导体装置及其形成方法
技术领域
本发明涉及一种半导体装置及其形成方法，特别是涉及一种具有外延结构的半导体装置及其形成方法。
背景技术
为了能增加半导体结构的载流子迁移率，可以选择对于栅极通道施加压缩应力或是伸张应力。举例来说，若需要施加的是压缩应力，现有技术常利用选择性外延成长(selective epitaxial growth,SEG)技术于一硅基底内形成晶格排列与该硅基底相同之外延结构，例如硅锗(silicon germanium,SiGe)外延结构。利用硅锗外延结构的晶格常数(lattice constant)大于该硅基底晶格的特点，对P型金属氧化物半导体晶体管的通道区产生应力，增加通道区的载流子迁移率(carrier mobility)，并用于增加金属氧化物半导体晶体管的速度。反之，若是N型半导体晶体管则可选择于硅基底内形成硅碳(siliconcarbide,SiC)外延结构，对栅极通道区产生伸张应力
前述方法虽然可以有效提升通道区的载流子迁移率，却导致整体制作工艺控制的难度，尤其是在半导体装置尺寸持续缩小的趋势下。有鉴于此，如何有效改良半导体装置的结构与制作工艺仍为现今一重要课题，以获得更具有可靠度的元件。
发明内容
本发明的一目的在于提供一种半导体装置及其形成方法，其使外延结构在凸伸于基底顶面的部分与栅极结构之间可相隔一定距离，进而避免影响该半导体装置整体的电性表现。
为达上述目的，本发明的一较佳实施例提供一种半导体装置，包含一基底，一栅极结构与一外延结构。该栅极结构设置在该基底上，而该外延结构则设置在该基底内，位于该栅极结构一侧。其中，该外延结构包含凸伸于该基底一顶面的一部分，该部分包含一不连续侧壁，且该不连续侧壁上的一转折点至该栅极结构之间的距离为该外延结构与该栅极结构之间相隔的最大距离。
为达上述目的，本发明的一较佳实施例提供一种半导体装置的形成方法，其包含以下步骤。首先，提供一基底，并且，于该基底上形成一栅极结构。然后，于该基底内形成一外延结构，位于该栅极结构一侧，其中，该外延结构包含凸伸于该基底一顶面的一部分，该部分包含一不连续侧壁，且该不连续侧壁上的一转折点至该栅极结构之间的距离为该外延结构与该栅极结构之间相隔的最大距离。
本发明分别利用两次沉积的两沉积层分别限定外延结构突出于基底或鳍状结构的部分的形成形式。使得该外延结构突出于该基底或该鳍状结构的部分可具有不连续侧壁，并且使得该不连续侧壁上的转折点与相邻栅极结构之间可间隔出一最大距离，以便能尽可能地拉开该外延结构与该栅极结构之间的距离。较佳地，该外延结构与该栅极结构之间间隔的最大距离可以尽可能地靠近该基底或该鳍状结构顶面，例如是间隔约200埃左右或约200埃以上的距离。由此，可避免该外延结构的设置影响位于该栅极结构两侧的该基底或该鳍状结构内的元件效能，如轻掺杂源极/漏极等，以利于提供整体功能更为优化的半导体装置。
附图说明
图1至图6为本发明第一实施例中半导体装置的形成方法的步骤示意图，其中：
图1为本发明的一半导体装置于形成方法之初的剖面示意图；
图2为本发明的一半导体装置于形成外延层后的剖面示意图；
图3为本发明的一半导体装置于形成沉积材料层后的剖面示意图；
图4为本发明的一半导体装置于进行一蚀刻制作工艺后的剖面示意图；
图5为本发明的一半导体装置于形成另一外延层后的剖面示意图；
图6为本发明的一半导体装置于形成外延结构后的剖面示意图。
图7至图8为本发明第二实施例中半导体装置的形成方法的步骤示意图，其中：
图7为本发明的一半导体装置于形成一外延层后的剖面示意图；
图8为本发明的一半导体装置于形成外延结构后的剖面示意图。
图9为本发明另一实施例中半导体装置法的结构示意图。
图10为本发明第三实施例中半导体装置的形成方法的步骤示意图。
主要元件符号说明
300 基底
320 鳍状结构
340 栅极结构
300 基底
320 鳍状结构
340 栅极结构
341 栅极介电层
341a 高介电常数介电层
342 栅极层
342a 金属栅极
343 盖层
344、344a 侧壁子
345 掩模层
346 轻掺杂源极/漏极
351、355 沉积层
352 沉积材料层
352a、356a 沉积层
370、370a 外延结构
371、373 外延层
371a、373a 渐缩部
371b、373b 侧壁
372、374 外延层
372b、374b 侧壁
d1、d2 最大距离
g1、g2、g3 空间
t1、t2、t3 厚度
具体实施方式
为使熟悉本发明所属技术领域的一般技术人员能更进一步了解本发明，下文特列举本发明的数个较佳实施例，并配合所附的附图，详细说明本发明的构成内容及所欲达成的功效。
请参照图1至图6，所绘示的为本发明第一较佳实施例中形成半导体装置的制作工艺示意图。首先，提供一基底300，例如一硅基底(silicon substrate)、外延硅(epitaxialsilicon substrate)、硅锗半导体基底(silicon germanium substrate)、碳化硅基底(silicon carbide substrate)或硅覆绝缘(silicon on insulation,SOI)基底。此外，基底300内可先利用一般光刻及蚀刻(photolithography-etching process,PEP)制作工艺或一多重曝光(multi-patterning)等制作工艺进一步形成一鳍状结构(fin structure)320，而成为非平面(non-planar)基底，但不以此为限。在其他实施例中，也可省略鳍状结构320，直接提供一平面(plannar)基底(未绘示)。
基底300上则形成有至少一栅极结构340，横跨鳍状结构320。本实施例虽是以在同一鳍状结构320上横跨三个栅极结构340为例，但其具体数量并不以此为限，可依据产品需求进行调整，例如可在同一鳍状结构320形成一根或一根以上的栅极结构340横跨于其上。具体来说，各栅极结构340包含一堆叠结构(未绘示)以及环绕该堆叠结构的一侧壁子344，该堆叠结构例如包含依序堆叠的一栅极介电层(gate dielectric layer)341例如可包含氧化硅，一栅极(gate)层342例如包含多晶硅或非晶硅，一盖层(capping layer)343例如包含氧化硅、氮化硅或氮氧化硅，与一掩模层345例如包含碳氮化硅等，但不以此为限。在一实施例中，栅极结构340的形成步骤，例如包含先在基底300上依序形成一介电材料层(未绘示)、一栅极材料层(未绘示)、一帽盖材料层(未绘示)与一掩模材料层后，再图案化这些堆叠层，进而形成该堆叠结构。接着，在该堆叠结构两侧的鳍状结构320(基底300)内分别形成一轻掺杂源极/漏极346，再于该堆叠结构的侧壁上进一步形成侧壁子344，例如包含氧化硅等材质，构成栅极结构340。本实施例中，虽是以形成单层结构的侧壁子344为例，但其具体设置形式并不以此为限，可依据产品需求进行调整。在另一实施例中，也可选择形成具有多层结构的侧壁子(未绘示)。
然后，进行一沉积制作工艺，以在各栅极结构340的侧壁子344上额外形成一沉积层351。在一实施例中，沉积层351例如是包含与侧壁子344具蚀刻选择的材质，如氮化硅或碳氮化硅等，其是先整体性地被沉积于鳍状结构320(即基底300)上，覆盖鳍状结构320的顶面与各栅极结构340，之后再通过一回蚀刻制作工艺，形成如图1所示的沉积层351。
接着，在各栅极结构340两侧的鳍状结构320(即基底300)内形成一外延结构370，作为源极/漏极区。首先，例如是先进行一蚀刻制作工艺，例如是干蚀刻、湿蚀刻或依序进行干蚀刻及湿蚀刻，以在各栅极结构340两侧的鳍状结构320中形成至少一凹槽(recess)360，再于凹槽360内进行一选择性外延成长(selective epitaxial growth,SEG)制作工艺，形成一外延层371，凸伸于鳍状结构320的顶面。需注意的是，本实施例的外延层371是通过事先沉积的沉积层351定义其形成位置，使得外延层371可具有逐渐往上渐缩的一渐缩部371a，还至少部分突出于鳍状结构320该顶面，如图2所示。详细来说，渐缩部371a具有一倾斜侧壁371b，连续地往远离栅极结构340的一方向渐缩，使渐缩部371a整体具有连续往下扩增的一宽度(未绘示)，并逐渐远离且不直接接触沉积层351。如此，外延层371紧邻沉积层351的一侧与沉积层351之间可进一步夹设出一空间(gap)g1。
此外，外延层371可依据后续所形成金属氧化物半导体(MOS)晶体管的类型而可具有不同的材质，例如可选择包含硅锗(silicon germanium,SiGe)或碳化硅(siliconcarbide,SiC)等。并且，在进行该选择性外延成长制作工艺时，可选择同步(in-situ)进行一掺杂制作工艺，依据后续所形成金属氧化物半导体晶体管的类型，掺杂合适的P型离子或N型离子，或者是，也可选择在该选择性外延成长制作工艺之后或之前，再额外进行一离子布植制作工艺以在外延层371中形成合适的掺质。举例来说，本实施例是以形成P型的金属氧化物半导体晶体管为例，而使外延层371选择包含硅锗，并同步掺杂一定浓度的硼(boron,B)离子，但不以此为限。
然后，进行另一沉积制作工艺，以在各栅极结构340上额外形成一沉积材料层352，并整体性地覆盖鳍状结构320(即基底300)的顶面、各栅极结构340与外延层371，如图3所示。在本实施例中，沉积材料层352较佳与沉积层351具有相同的材质，例如都是包含氮化硅，并且具有大于沉积层351的一厚度(未绘示)，较佳的约为90至100埃(angstroms)，以便能填满空间g1，并进一步覆盖住外延层371的顶面。之后，则进行另一回蚀刻制作工艺，例如是一干蚀刻制作工艺，移除大部分的沉积材料层352，形成沉积层352a以暴露出外延层371的该顶面。在本实施例中，较佳的是将沉积材料层352移除至低于外延层371该顶面处，如图4所示，使得沉积层352a仅能部分填满外延层371与沉积层351之间的空间g1，但不以此为限。在另一实施例中，也可选择仅将沉积材料层352移除至与外延层371的该顶面齐平，意即，使得所形成的该沉积层(未绘示)仍可填满外延层371与沉积层351之间的空间g1。
而后，自外延层371的该顶面进行另一选择性外延成长制作工艺，形成一外延层372，使得外延层372可具有整体均匀的一厚度t1。在本实施例中，外延层372是自外延层371暴露于沉积层352a外的该顶面往上成长所形成，因而整体呈现逐渐往上渐扩的一渐扩部。并且，该渐扩部亦具有一倾斜侧壁372b，连续地往朝向栅极结构340的一方向渐扩，以使该渐扩部整体具有连续往上扩增的一宽度(未绘示)，如图5、图6所示。此外，外延层372同样可依据后续所形成金属氧化物半导体晶体管的类型而可具有不同的材质与掺质，并且较佳的是与外延层371具有相同的材质与掺质。也就是说，本实施例的外延层372例如同样可包含硅锗，并同步掺杂一定浓度的硼离子，并且，外延层372中硼离子的掺杂浓度较佳的是大于外延层371中硼离子的掺杂浓度。
后续，则进行一蚀刻制作工艺，完全移除剩余的沉积层352a与沉积层351，使得外延层372与外延层371凸伸于鳍状结构320(即基底300)顶面的上半部可进一步拉开与两侧的栅极结构340之间的间隔，特别是使邻近于鳍状结构320该顶面的位置处可被拉开约200埃的间隔，如图6所示。由此，外延层371、372即可构成外延结构370，形成该金属氧化物半导体晶体管的源极/漏极区(未绘示)。具体来说，外延结构370凸伸于鳍状结构320(即基底300)顶面的部分由外延层372与部分的外延层371(即部分的渐缩部371a)构成，又因外延层372与该部分的外延层371都具有分别渐扩或渐缩的侧壁372b、371b，使得外延结构370凸伸于鳍状结构320顶面的该部分整体上具有一不连续侧壁(未绘示)。该不连续侧壁的下半部即为外延层371(渐缩部371a)的侧壁371b，其在形成时因受到沉积层351影响而朝远离栅极结构340的方向连续地倾斜，而该不连续侧壁的上半部即为外延层372(渐扩部)的侧壁372b，其因从外延层371的暴露顶面形成反而朝着栅极结构340的方向连续地倾斜，如图6所示。在此情况下，外延层371(渐缩部)与外延层372(渐扩部)之间的一转折点(未绘示)与相邻栅极结构340之间的间隔距离则可成为外延结构370与相邻栅极结构340之间相隔的最大距离d1，例如是约为200埃至250埃，如图6所示。并且，在一实施中，该最大距离较佳的是尽可能地位于靠近鳍状结构320(即基底300)顶面的位置，由此，可拉开外延结构370与栅极结构340在鳍状结构320上的距离，避免外延结构370的设置影响到栅极结构340两侧鳍状结构320内的电流密集区，如轻掺杂源极/漏极346等，但不以此为限。
由此，即完成本发明第一较佳实施例中的半导体装置。本实施例的形成方法主要是通过两次沉积的沉积层351、352分别限定外延结构370突出于基底300部分的形成形式，尽可能地拉开外延结构370与栅极结构340之间的距离，特别是指靠近基底300顶面的位置可被拉开约200埃左右的间隔。由此，可避免栅极结构340两侧基底300内的电流密集区(如轻掺杂源极/漏极346等)受到外延结构370的影响，以改善该半导体装置整体的元件效能。
此外，本领域技术员应可轻易了解，为能满足实际产品需求的前提下，本发明半导体装置的形成方法也可能有其它形式，而不限于前述。因此，下文将进一步针对本发明半导体装置的形成方法的其他实施例或变化型进行说明。且为简化说明，以下说明主要针对各实施例不同之处进行详述，而不再对相同之处作重复赘述。此外，本发明的各实施例中相同的元件以相同的标号进行标示，以利于各实施例间互相对照。
请参照图7至图8所示，其绘示本发明第二较佳实施例中的半导体装置的形成方法，本实施例的步骤大体上与前述第一较佳实施例相同，在此不在赘述。本实施例的制作工艺与前述第一较佳实施例主要差异在于，形成具有倾斜轮廓的侧壁子344a，以便能进一步限制外延层373突出于鳍状结构320该顶面的部位。
详细来说，本实施例的侧壁子344a例如是在其下半部的位置形成有一倾斜轮廓，如图7所示。或者，也可在另一实施例中，使该侧壁子整体上具有连续倾斜的轮廓(未绘示)，但不以此为限。如此，后续沉积在侧壁子344a上的沉积层355则可共型地形成一倾斜轮廓。在此情况下，外延层373在形成时即会受到侧壁子344a与沉积层355的双重限制，使得其渐缩部373a的倾斜侧壁373b更进一步地倾斜，并且相较于前述实施例中的外延层371而具有更大的倾斜角度，同时使得外延层373与沉积层355之间有更大的空间g2，如图7所示。而后，即可同样如前述实施例中图3至图5所示，依序形成至少部分填满空间g2的沉积层356a与外延层374，并且，再通过一蚀刻制作工艺，完全移除沉积层356a与沉积层355，使得外延层374与外延层373可构成外延结构370a，作为本实施例中该金属氧化物半导体晶体管的源极/漏极区(未绘示)。
需注意的是，本实施例的外延层374同样自外延层373暴露于沉积层356a外的该顶面往上成长所形成，因而整体上也呈现逐渐往上渐扩的一渐扩部。并且，该渐扩部也具有一倾斜侧壁374b，连续地往朝向栅极结构340的一方向靠近，以使该渐扩部整体具有连续往上扩增的一宽度(未绘示)，如图7、图8所示。另一方面，本实施例的外延层374亦具有整体均匀的一厚度t2，且其厚度t2较佳的是大于下方外延层373的渐缩部373a突出于鳍状结构320(即基底300)表面的厚度(未绘示)，但不以此为限。
本实施例的外延结构370a大体上具有与外延结构370相同的特征。外延结构370a凸伸于鳍状结构320(即基底300)顶面的部分由外延层374与部分的外延层373(即部分的渐缩部373a)构成，又因外延层374与该部分的外延层373都具有分别渐扩或渐缩的侧壁374b、373b，使得外延结构370a凸伸于鳍状结构320顶面的该部分也可具有一不连续侧壁(未绘示)。该不连续侧壁的下半部即为外延层373(渐缩部373a)的侧壁373b，上半部则为外延层374(即该渐扩部)的侧壁374b，如图8所示。在此情况下，外延层373(渐缩部373a)与外延层374(该渐扩部)之间的一转折点(未绘示)与相邻栅极结构340之间的相隔距离则可成为外延结构370a与相邻栅极结构340之间相隔的最大距离d2，例如是约为250埃至270埃。由此，可进一步拉开外延结构370a与栅极结构340之间的距离，特别是使其邻近于鳍状结构320该顶面的位置处可被拉开约200埃以上的间隔，如图8所示。
另一方面，因本实施例中外延结构370a凸伸于鳍状结构320(即基底300)顶面的该部分具有倾斜角度更大的不连续侧壁，因此，其上的该转折点与相邻栅极结构340之间相隔距离更可进一步被拉开，而在外延层374与部分的外延层373(即部分的渐缩部373a)之间额外夹设出一空间g3，如图8所示。空间g3在后续形成覆盖鳍状结构320(即基底300)的层间介电层(未绘示)时，易残留空气而形成气孔(void,未绘示)，进而提升外延结构370与栅极结构340之间的隔离效果，以利于提供整体功能更为优化的半导体装置。
由此，即完成本发明第二较佳实施例中的半导体装置。本实施例的形成方法主要是额外利用侧壁子344a的倾斜轮廓进一步限定外延层373凸伸于基底300该顶面的部位的倾斜角度，使得外延层373的侧壁373b可朝远离栅极结构340的方向进一步倾斜，进而更有利于拉开外延结构370a与栅极结构340之间的距离，特别是在外延结构370a邻近于基底300该顶面的位置处。由此，更能有效地避免外延结构370a的设置影响到栅极结构340两侧基底300内的电流密集区，如轻掺杂源极/漏极346等，以进一步提升该半导体装置整体的元件效能。
此外，本案前述实施例中所述另一选择性外延成长制作工艺，虽皆是以自外延层371、373暴露于沉积层352a、356a外的该顶面往上形成外延层372、374为实施状态说明，但并不以此为限。换言之，本发明的另一选择性外延成长制作工艺也可选择不形成倒梯形状(reverse trapezoid shape)的外延层372、374，而是使得该另一选择性外延成长制作工艺在进行时，自外延层371、373暴露于沉积层352a、356a外的该顶面同时往上且往两侧成长，而使得所形成的外延层376可呈现一平台状(platform like shape)，并且悬空地设置在下方的外延层371、373上，如图9所示。其中，外延层376可具有均匀的一厚度t3。
如图10，其绘示本发明第三较佳实施例中的半导体装置的形成方法，本实施例的步骤大体上与前述第二较佳实施例相同，于此不在赘述。本实施例的制作工艺与前述第二较佳实施例主要差异在于，在形成栅极结构340时，亦可选择直接形成一金属栅极，其至少包含一高介电常数介电层341a例如包含氧化铪(hafnium oxide，HfO2)、硅酸铪氧化合物(hafnium silicon oxide，HfSiO4)或硅酸铪氮氧化合物(hafnium silicon oxynitride，HfSiON)等材质，与一金属栅极层342a例如包含铝(Al)、钛或钨(W)等金属材质，如图9所示。或者，在另一实施例中，也可选择在形成该层间介电层之后，另进行一金属栅极置换(replacement metal gate,RMG)制作工艺，将栅极结构340的栅极层342转换为一金属栅极342a，如图10所示。
整体来说，本发明的形成方法分别利用两次沉积的两沉积层分别限定外延结构突出于基底或鳍状结构的部分的形成形式。使得该外延结构突出于该基底或该鳍状结构的部分可具有不连续侧壁，并且使得该不连续侧壁上的转折点与相邻栅极结构之间可间隔出一最大距离，以便能尽可能地拉开该外延结构与该栅极结构之间的距离。较佳地，该外延结构与该栅极结构之间间隔的最大距离可以尽可能地靠近该基底或该鳍状结构顶面，例如是间隔约200埃左右或约200埃以上的距离。藉此，可避免该外延结构的设置影响位于该栅极结构两侧的该基底或该鳍状结构内的元件效能，如轻掺杂源极/漏极等，以利于提供整体功能更为优化的半导体装置。
以上所述仅为本发明的较佳实施例，凡依本发明权利要求所做的均等变化与修饰，皆应属本发明的涵盖范围。

Claims (19)

1.一种半导体装置，其特征在于包含：
基底；
栅极结构，设置在该基底上；以及
外延结构，设置在该基底内，位于该栅极结构一侧，该外延结构包含凸伸于该基底一顶面的一部分，该部分包含渐缩部与渐扩部，该渐缩部与该渐扩部之间设有转折点，其中该渐扩部完全覆盖该渐缩部的顶面，且该转折点至该栅极结构之间的距离为该外延结构与该栅极结构之间相隔的最大距离。
2.依据权利要求1所述的半导体装置，其特征在于，该渐扩部具有大于该渐缩部的厚度。
3.依据权利要求1所述的半导体装置，其特征在于，该渐扩部具有大于该渐缩部的掺杂浓度。
4.依据权利要求1所述的半导体装置，其特征在于，该渐扩部设置在该渐缩部上，且该渐扩部的宽度逐渐往上扩增。
5.依据权利要求4所述的半导体装置，其特征在于，该渐缩部的宽度逐渐往下扩增。
6.依据权利要求1所述的半导体装置，其特征在于，该渐扩部包含悬空平台。
7.依据权利要求6所述的半导体装置，其特征在于，该悬空平台具有均匀的厚度。
8.依据权利要求1所述的半导体装置，其特征在于，该最大距离邻接该基底该顶面。
9.依据权利要求1所述的半导体装置，其特征在于，该栅极结构包含侧壁子，该侧壁子环绕栅极且包含倾斜侧壁。
10.一种半导体装置的形成方法，其特征在于包含：
提供基底；
在该基底上形成栅极结构；以及
在该基底内形成外延结构，位于该栅极结构一侧，该外延结构包含凸伸于该基底一顶面的一部分，该部分包含渐缩部与渐扩部，该渐缩部与该渐扩部之间设有转折点，其中该渐扩部完全覆盖该渐缩部的顶面，且该转折点至该栅极结构之间的距离为该外延结构与该栅极结构之间相隔的最大距离。
11.依据权利要求10所述的半导体装置的形成方法，其特征在于，该外延结构的形成包含：
在该基底内形成第一外延层，位于该栅极结构一侧，该第一外延层具有该渐缩部，凸伸于该基底的顶面；
形成第一沉积层，夹设于该栅极结构与该第一外延层之间，暴露出该第一外延层的顶面；以及
自该第一外延层的该顶面形成第二外延层。
12.依据权利要求11所述的半导体装置的形成方法，其特征在于，该第一外延层的形成包含：
形成第二沉积层，覆盖该栅极结构，该第二沉积层具有倾斜侧壁；以及
在该基底内形成该第一外延层。
13.依据权利要求12所述的半导体装置的形成方法，其特征在于，该第一沉积层的形成还包含：
在该第二沉积层形成之后，形成材料层，覆盖该栅极结构与该第一外延层；以及
部分移除该材料层，以暴露出该第一外延层的该顶面，并形成该第一沉积层。
14.依据权利要求12所述的半导体装置的形成方法，其特征在于，还包含：
完全移除该第一沉积层与该第二沉积层，以形成该外延结构。
15.依据权利要求11所述的半导体装置的形成方法，其特征在于，该第一外延层的该渐缩部具有连续渐缩的宽度。
16.依据权利要求11所述的半导体装置的形成方法，其特征在于，该转折点位于该第一外延层的该渐缩部与该第二外延层之间。
17.依据权利要求11所述的半导体装置的形成方法，其特征在于，该第二外延层具有连续渐增的宽度。
18.依据权利要求11所述的半导体装置的形成方法，其特征在于，该第二外延层具有均匀的厚度。
19.依据权利要求11所述的半导体装置的形成方法，其特征在于，该第二外延层具有大于该第一外延层的掺杂浓度。
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