CN110957275B - 集成电路及其制造方法 - Google Patents

集成电路及其制造方法 Download PDF

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CN110957275B
CN110957275B CN201910917170.9A CN201910917170A CN110957275B CN 110957275 B CN110957275 B CN 110957275B CN 201910917170 A CN201910917170 A CN 201910917170A CN 110957275 B CN110957275 B CN 110957275B
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layer
substrate
silicon
base layer
stack
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CN110957275A (zh
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李东颖
张开泰
萧孟轩
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

本揭露描述的实施方式描述由个别形成的纳米线半导体带的堆叠形成栅极全环(“GAA”)元件的技术，即集成电路及其制造方法。个别形成的纳米线半导体带未各别栅极全环元件量身订做。形成沟渠于磊晶层的第一堆叠中，以定义出形成磊晶层的第二堆叠的空间。将沟渠底部修改成在形状或结晶晶面取向上具有确定或已知参数。利用沟渠底部的已知参数选择适合制程来以相对平坦基底面的方式填充沟渠底部。

Description

集成电路及其制造方法
技术领域
本揭露的实施方式是有关于集成电路。
背景技术
互补式金氧半导体(CMOS)晶体管为集成电路的建构组件。更快的互补式金氧半导体开关速度需要较高的驱动电流，其驱使互补式金氧半导体晶体管的栅极长度持续缩减。较短的栅极长度导致不受欢迎的“短通道效应 (short-channel effect)”，其中栅极的电流控制功能受到连累。除了别的之外，已发展鳍式场效晶体管(FinFET)来克服短通道效应。依照朝改善通道的静电控制的进一步步骤，已发展出具环绕栅极的晶体管，其中栅极部分可从半导体通道或通道带的上表面、下表面、及/或侧壁围绕半导体通道或通道带。
发明内容
在一实施方式中，一种集成电路包含基材、第一元件、第二元件、以及半导体基底层。基材包含第一基材区与第二基材区。第一元件包含第一半导体材料的第一复数个带位于第一基材区之上、第一栅极结构环绕第一复数个带的至少一者、以及第一源极/漏极结构接触第一复数个带的此至少一者。第二元件包含第二半导体材料的第二复数个带位于第二基材区之上、第二栅极结构环绕第二复数个带的至少一者、以及第二源极/漏极结构接触第二复数个带的此至少一者。半导体基底层嵌在第一基材区或第二基材区的一者中，且位于第一元件或第二元件的对应一者之下。
在一结构实施方式中，结构包含基材、基底层、以及元件。基底层嵌于基材的凹陷部中。元件位于基底层之上，元件包含半导体材料的复数个带、栅极结构环绕复数个带的至少一者、以及第一源极/漏极结构接触复数个带的此至少一者。基底层包含不同于基材的材料。
在一方法实施方式中，形成第一复数个半导体层的第一堆叠于结晶基材之上，形成沟渠于第一堆叠中，以透过沟渠暴露出结晶基材。形成元件间隙壁邻近沟渠的侧壁。利用蚀刻制程形成凹陷部于沟渠的底部，此蚀刻制程在结晶基材的结晶晶面中为非等向性，如此凹陷具有底部以及对底部具有一角度的倾斜侧壁部。形成半导体基底层于凹陷部内。形成第二复数个半导体层的第二堆叠于半导体基底层之上。
附图说明
从以下结合所附附图所做的详细描述，可对本揭露的态样有更佳的了解。在附图中，除非内文表明，否则相同参考数字识别类似元件或动作。在附图中元件的尺寸与相对位置无须依比例绘示。事实上，为了使讨论更为清楚，各特征的尺寸都可任意地增加或减少。
图1是绘示一个例示集成电路(IC)的剖面图；
图2是绘示一个例示制程的流程示意图；以及
图3A至图3J是绘示一晶圆在制造具有栅极全环(GAA)元件的集成电路的例示制程的各阶段中的剖面图。
【符号说明】
100 集成电路
102 基材
102S 表面、上表面
102U 上表面
104 n型井、基材区、N型井、基材
104P 鳍状基材部、鳍状基材图案
106 p型井、基材区、第二基材区
106P 鳍状基材部
106U 上表面
108 介电体、元件间隙壁
108L 下表面
110 第一元件、元件、p型场效晶体管元件
120 纳米线带、通道区、通道
130 栅极结构、栅极
132 外间隙壁
134 内间隙壁
140 源极/漏极区、源极/漏极结构
142 介电层
150 第二元件、元件、n型场效晶体管元件
160 纳米线带、通道区、通道
170 栅极结构、栅极
172 外间隙壁
174 内间隙壁
180 源极/漏极区、源极/漏极结构
182 介电层
190 基底层、图案化部
190B 底部
190S 表面
190SW 倾斜侧壁部
192 硅锗基底层
194 硅基底层
196 图案化部
205 例示操作
210 例示操作
215 例示操作
220 例示操作
225 例示操作
230 例示操作
235 例示操作
240 例示操作
245 例示操作
238 预烘烤制程
300 晶圆
310 第一堆叠、堆叠、纳米线堆叠
310P 第一图案化堆叠
310U 上表面
312 磊晶层、层、硅锗层、硅锗磊晶层、硅锗纳米线带、牺牲纳米线带、纳米线带
314 磊晶层、层、硅层、硅磊晶层、硅纳米线带、纳米线带
320 沟渠
320B 底部
320BB 中央底部、底部
320BS 倾斜底侧壁部
320SW 侧壁
321 罩幕层、光阻层
322 介电层
330 凹陷部、凹陷
330B 底部
330BS 倾斜侧壁部、侧壁
330E 边缘
340 半导体基底层、基底层
340E 边缘部
340U 上表面
342 硅锗层、硅锗基底层、硅锗磊晶层、磊晶层、基底层
342U 上表面
344 基底层、硅基底层、硅层
346 取向、晶面方向
348 取向、晶面方向
350 第二堆叠、堆叠、纳米线堆叠
350P 第二图案化堆叠
350U 上表面
352 磊晶层、硅锗磊晶层、硅锗层、硅锗纳米线带、纳米线带
354 磊晶层、硅磊晶层、硅层、硅纳米线带、牺牲纳米线带、纳米线带
360 介电层
D1 深度
T1 厚度
T2 厚度
T3 厚度
T4 厚度
T5 厚度
θ1 角度
θ2 角度
具体实施方式
本揭露的实施方式描述由各别形成的纳米线半导体带的堆叠制作栅极全环(gate-all-around，“GAA”)元件的技术。于在此的描述中，“纳米线带(nanowire strip)”或“纳米线(nanowire)”是指具有边缘面(edge surface)尺寸范围从约 2nm至约50nm的带状结构。“纳米线带”可指具有边缘面直径范围从约2nm 至约15nm的带状结构。“纳米线带”可指具有边缘面其具高度范围从约2nm 至约10nm与宽度范围从约6nm至约50nm的带状结构。其他尺寸参数的纳米线半导体带亦可行。于在此的描述中，用语“纳米线”或“纳米线带”或“带”用以指任何类型的带状结构，包含但不限于纳米线、纳米片(nanosheet)、或纳米板(nanoslab)。
各别形成的纳米半导体带是针对各别栅极全环元件量身订做。举例而言，这些带的尺寸、材料组成、与定位各别针对n型场效晶体管(nFET)与p型场效晶体管(pFET)元件设计。在n型场效晶体管与p型场效晶体管元件之间，此两种类型的元件的至少一种由在一定义空间中局部形成的纳米带所制成。发明人已注意到，于定义的空间中，像是沟渠中，成长磊晶层时，所沉积的磊晶层的外形受到所定义的空间的底面与邻近此底面的侧壁部分的形状所影响。具体而言，邻近于底面的侧壁部分的结晶晶面(crystalline facet)影响靠侧壁的磊晶层的成长。在实际生产中，沟渠底部的形状可能受到许多因素有意与无意的影响。
本技术包含故意修改或形成沟渠底部，使其在形状上或结晶晶面取向 (facetorientation)具有确定或已知参数的制程。因而利用具有这样所确定的参数进行后续制造制程。
举例而言，进行晶体非等向性(anisotropic)湿蚀刻，以形成凹陷部于沟渠的底部中。根据非等向性蚀刻，决定凹陷部的深度以及凹陷部的侧壁的倾斜角。利用所给的这类参数，形成硅锗磊晶层于凹陷部中来填充凹陷部。控制硅锗磊晶成长，如此硅锗材料沿例如{100}晶面硅的凹陷部的底面的晶面取向的成长远快于沿例如硅的{111}晶面的凹陷部的侧壁的晶面取向。举例而言，可设计硅锗磊晶制程，以利硅锗成长在{100}晶面而非{111}晶面。因晶格不匹配 (lattice mismatch)，{100}晶面硅锗不会留在{111}晶面硅的凹陷部的侧壁上。由于硅锗磊晶层实质沿{100}晶面而非其{111}面成长，因此硅锗磊晶层相对于例如{100}晶面硅的凹陷部的底部实质平坦。由于基底硅锗磊晶层实质平坦，因此沉积在基底硅锗磊晶层上方的硅与硅锗的磊晶层亦趋于平坦。
在一方法实施方式中，磊晶硅层与磊晶硅锗层的第一堆叠形成于基材，例如硅基材之上。磊晶硅锗层与磊晶硅层以交替方式垂直堆叠。第一堆叠中的一硅锗层具有第一厚度与第一锗浓度，例如锗在硅与锗总数中的原子比率。第一堆叠中的一硅层具有第二厚度，其不同于第一堆叠中的硅锗的第一厚度。在一实施方式中，第一堆叠中的硅层与硅锗层是利用磊晶制程制作且称为磊晶层。
形成沟渠，以使其至少局部位于第一堆叠的磊晶层中，而暴露出硅基材。选择性地，通过沟渠的侧壁形成介电材料的元件间隙壁。于沟渠形成后或于元件间隙壁形成后，沟渠的底面可包含凹陷位于硅基材中。通常，凹陷包含第一部分，其为凹陷的相对平坦底部。凹陷的第二部分为邻近该平坦底部的倾斜侧壁部。在数个晶圆之中，凹陷的实际形状或参数可能会有所变化。
进行晶体非等向性蚀刻，以改变凹陷部的形状。具体而言，透过晶体非等向性蚀刻制程在基材的不同结晶晶面/平面具有不同蚀刻速率，而达成此修改。举例而言，控制晶体非等向性蚀刻制程，而使其在{110}与{100}晶面上具有较在{111}晶面上高的蚀刻速率。作为结果而发生的，将凹陷部的侧壁修改成实质位在硅基材的{111}晶面。对于硅，{111}晶面具有相对于{100}平面约54.7 度的角度。于此修改后，凹陷部的侧壁具有相对于底部约54.7度的角度。侧壁的其他角度亦是可以的，只要这些角度是已知且可控制的。举例而言，可将侧壁的角度形成在约45度至约65度的范围内，此范围通常符合硅的{111}晶面与{100}平面之间的角度。
于修改凹陷部后，透过磊晶制程形成硅锗基底层于凹陷部中。硅锗具有良好的填隙性能，因此硅锗基底层可填充凹陷的底部上的细微不平坦。此外，可选择与控制磊晶条件，如此因例如晶格的不匹配，硅锗材料不会形成在{111} 晶面上。因此，硅锗基底层实质为无晶面在边缘部，且相对平坦。取决于欲形成在沟渠内的磊晶层的堆叠，可将硅的磊晶基底层形成于硅锗基底层之上。有鉴于硅锗基底层的表面相对平坦，硅基底层的表面亦相对平坦。硅基底层之上表面与硅基材实质等高。硅锗与硅基底层用来填充凹陷与产生平坦表面，以供后续磊晶层在沟渠内的沉积。它们并非用以形成半导体主体，例如元件的通道。
硅磊晶层与硅锗磊晶层的第二堆叠形成在沟渠中的基底层之上。在一实施方式中，第二堆叠中的一硅锗磊晶层具有第三厚度与第二锗浓度。第二堆叠中的一硅层具有第四厚度。在一实施方式中，第二堆叠中的硅锗层的第三厚度不同于第一堆叠中的硅锗层的第一厚度。第二堆叠中的硅层的第四厚度不同于第一堆叠中的硅层的第二厚度。此外，第二堆叠中的硅锗层的第二锗浓度不同于第一堆叠中的硅锗层的第一锗浓度。
图案化第一堆叠磊晶层与第二堆叠磊晶层，以定义出第一元件与第二元件的第一鳍状区与第二鳍状区。第一元件形成于第一鳍状区之上。第二元件形成于第二鳍状区之上。亦可图案化第二鳍状区下方的硅锗基底层与硅基底层。硅锗基底层具有倒锥(invertedtapered)侧壁，此倒锥侧壁与硅锗层的底面具有约 54.7度的角度。
以下的揭露提供了许多不同实施方式或例子，以实施所揭露的标的的不同特征。以下描述的构件与安排的特定例子是用以简化本说明。当然，这些仅为例子，并非用以作为限制。举例而言，于描述中，第一特征形成于第二特征的上方或之上，可能包含第一特征与第二特征以直接接触的方式形成的实施方式，亦可能包含额外特征可能形成在第一特征与第二特征之间的实施方式，如此第一特征与第二特征可能不会直接接触。此外，本揭露的实施方式可能会在各例子中重复参考数字及/或文字。这样的重复是基于简化与清楚的目的，以其本身而言并非用以指定所讨论的各实施方式及/或配置之间的关系。
再者，在此可能会使用空间相对用语，例如“在下(beneath)”、“下方 (below)”、“较低(lower)”、“上方(above)”、“较高(upper)”与类似用语，以方便说明来描述如附图所绘示的一构件或一特征与另一(另一些)构件或特征之间的关系。除了在图中所绘示的方位外，这些空间相对用词意欲含括元件在使用或操作中的不同方位。设备可能以不同方式定位(旋转90度或在其他方位上)，因此可利用同样的方式来解释在此所使用的空间相对描述符号。
在以下的描述中，阐明特定具体细节，以提供对本揭露的许多实施方式的透彻了解。然而，熟悉的技艺者将了解到，可在无需这些具体细节的情况下实施本揭露的实施方式。在其他情况下，并未详细描述与电子构件及制造技术有关的知名结构，以避免对本揭露的实施方式的描述造成不必要的模糊。
除非内文要求，否则以下整篇说明书与申请专利范围的用字“包含 (comprise)”及其变化，例如“包含(comprises)”与“包含(comprising)”，以开放与包含观念解释，意即“包含(including)，但不限于”。
序数词，例如第一、第二、第三的使用不见得意味次序的排名，而仅是为了在一动作或结构的多个情况之间作区别。
此整个说明书中提及的“一个实施方式”或“一实施方式”意旨关于此实施方式描述的特定特征、结构、或特性包含在至少一实施方式中。因此，在整个说明书中的各地方出现的词组“在一个实施方式中”或“在一实施方式中”不必然指称相同实施方式。再者，在一或多个实施方式中，特定特征、结构、或特性可以任何适合方式结合。
如在此说明书与所附申请专利范围中所使用的单数型态的用语“一(a)”、“一(an)”、与“该(the)”包含复数指示对象，除非内文清楚规定。亦应注意的一点是，用语“或(or)”通常以其意义包含“及/或(and/or)”的方式应用，除非内文清楚规定。
可利用任何适合方法来图案化栅极全环(GAA)晶体管结构。举例而言，可利用一或多道光学微影制程来图案化这些结构，光学微影制程包含双重图案化 (double-patterning)或多重图案化(multi-patterning)制程。一般而言，双重图案化或多重图案化制程结合光学微影与自我对准制程，可形成具有例如间距小于利用单一与直接光学微影制程的其他方式可获得的图案的图案。举例而言，在一实施方式中，形成牺牲层于基材上方，并利用光学微影制程予以图案化。利用自我对准制程在图案化后的牺牲层旁边形成间隙壁。接着移除牺牲层，接下来可利用留下的间隙壁来图案化栅极全环结构。
图1是绘示一个包含互补式金氧半导体(CMOS)组件的例示集成电路结构“集成电路(IC)”100的剖面图。请参考图1，集成电路100包含基材102。基材102选择性地包含n型掺杂区“n型井(n-well)”104以及p型掺杂区“p 型井(p-well)”106。第一元件110，例如p型场效晶体管，形成于n型井104 之上及/或之中。第二元件150，例如n型场效晶体管，形成于p型井106之上及/或之中。设置一或多个介电体108(亦称为元件间隙壁108)，以将第一元件110与第二元件150彼此隔开。应了解到的一点是，根据元件设计或配置，基材102可能不需要n型井104或p型井106。于在此的描述中，n型井104与 p型井106用以举例说明，而为了一般化的目的称为基材区104与基材区106。
每个第一元件110与第二元件150分别包含数个分开的半导体纳米线带 120与160的垂直堆叠。在一实施方式中，纳米线带120为硅锗，纳米线带160 为硅。每个第一元件110与第二元件150包含栅极结构130与170，栅极结构 130与170围绕，例如环绕，各别的分开纳米线带120与160的至少一些。分开的纳米线带120与160配置以作为元件110与150的通道区，且与各别的源极/漏极区140及180形成接合。源极/漏极区140及180和各自的栅极130与170被内间隙壁134与174及/或外间隙壁132与172所隔开。
在一实施方式中，元件110配置为p型场效晶体管，元件150配置为n 型场效晶体管。纳米线带120为硅锗或其他适合的半导体材料。源极/漏极区 140为硅锗(“SiGe”)或硅锗硼(“SiGeB”)、或其他适合P型元件的材料。源极/漏极区180为磷化硅碳(“SiCP”)、碳化硅(“SiC”)、磷化硅(“SiP”)、或其他适合N型元件的半导体材料。每个源极/漏极区140及180可以许多方式掺杂。举例而言，源极/漏极区140以硼、镓、铟、以及其他在III族中的适合掺质掺杂。源极/漏极区180以砷、磷、以及其他在V族中的适合掺质掺杂。
图1显示出源极/漏极区140及180的例示实施方式。在所示的实施方式中，每个源极/漏极区140及180经由纳米线带120与160的边缘面接触各自的纳米线带120与160。此外，每个源极/漏极区140及180邻接各自的介电层 142与182。介电层142与182可为一相同层或可为二不同层。介电层142与 182可包含与元件间隙壁108相同的介电材料，或者可包含不同于元件间隙壁 108的介电材料的介电材料。介电层142与182可为氧化硅、氮化硅、低介电常数介电材料、或其他适合介电材料。
作为一个例示例子，图1显示源极/漏极区140及180与通道区120及160 之间的例示结构配置。具体而言，每个源极/漏极区140及180接触各自通道120及160的边缘面。此例示实施方式并未限制本揭露的实施方式与其他实施方式的范围。源极/漏极区140/180与半导体纳米线带120/160的其他结构配置亦是可行的，且包含在本揭露的实施方式中。举例而言，源极/漏极区140/180 可环绕各自的半导体纳米线带120/160的至少一些。纳米线带120及160可在各自的介电层142与182之间后退(如图1所示)或一直延伸。
基材102可包含结晶结构的硅基材及/或其他适合半导体，像是锗。二者择一或此外，基材102可包含化合物半导体，例如碳化硅、砷化镓、砷化铟、及/或磷化铟。此外，基材102亦可包含绝缘体上硅(SOI)结构。为提升性能，基材102可包含磊晶层及/或可经应变。
在一实施方式中，基材102包含硅的{100}晶面的晶面区。
在一实施方式中，每个栅极结构130与170形成为替换金属栅极。以下的描述列出栅极结构130与170的材料的例子。每个栅极130与170的栅极电极 (为简化而未个别绘示出)包含导电材料，例如金属或金属化合物。栅极结构130 与170的栅极电极的适合金属材料包含钌、钯、铂、钨、钴、镍、及/或导电金属氧化物、与其他适合的P型金属材料，且包含铪(Hf)、锆(Zr)、钛(Ti)、钽 (Ta)、铝(Al)、铝化物、及/或导电金属碳化物(例如，碳化铪、碳化锆、碳化钛、与碳化铝)、与其他适合n型金属材料的材料。在一些例子中，每个栅极结构 130与170的栅极电极包含功函数层，功函数层经调控以具有提升场效晶体管元件的性能的适当功函数。举例而言，适合的n型功函数金属包含钽、钛铝合金(TiAl)、氮化钛铝(TiAlN)、碳氮化钽(TaCN)、其他n型功函数金属、或其组合，适合的p型功函数金属材料包含氮化钛(TiN)、氮化钽(TaN)、其他p型功函数金属、或其组合。在一些例子中，导电层，例如铝层、铜层、钴层、或钨层，形成于功函数层之上，如此每个栅极结构130与170的栅极电极包含一功函数层设于栅极介电质之上、以及一导电层设于功函数层之上与一栅极覆盖之下(为了简化而未绘示)。在一例子中，根据设计需求，每个栅极结构130与170 的栅极电极具有范围从约5nm至约40nm的厚度。
在例示实施方式中，栅极结构130与170的栅极介电层(为了简化而未个别绘示出)包含界面氧化硅层(为了简化而未个别绘示出)，例如具有厚度范围从约
Figure RE-GDA0002326439200000101
至约
Figure RE-GDA0002326439200000102
的热或化学氧化物。在例示实施方式中，栅极介电层还包含高介电常数(high-k)介电材料，高介电常数介电材料选自于氧化铪(HfO2)、硅氧化铪(HfSiO)、氮氧化铪硅(HfSiON)、氧化铪钽(HfTaO)、氧化铪钛(HfTiO)、氧化铪锆(HfZrO)、其组合、及/或其他适合材料中的一或多个。在一些应用中，高介电常数介电材料包含介电常数值大于6。根据于设计需求，使用介电常数值7或更高的介电材料。可利用原子层沉积(ALD)或其他适合技术形成高介电常数介电层。依照在此所描述的实施方式，栅极介电层的高介电常数介电层包含范围从约
Figure RE-GDA0002326439200000111
至约
Figure RE-GDA0002326439200000112
的厚度或其他适合厚度。
在一实施方式中，外间隙壁132与172由低介电常数介电材料所组成，此低介电常数介电材料例如为介电常数值低于3.9，例如氮氧化硅(SiON)、一氧化硅(SiO)、氮碳氧化硅(SiONC)、碳氧化硅(SiOC)、真空(vacuum)、与其他介电质或其他适合材料。可利用化学气相沉积(CVD)、高密度电浆化学气相沉积、旋转涂布(spin-on)、溅镀(sputtering)、或其他适合方法形成外间隙壁132与172。
在一实施方式中，内间隙壁134与174由低介电常数介电材料所组成。在一些实施方式中，内间隙壁134与174的低介电常数介电材料可具有不同于各自的外间隙壁132与172的介电常数的介电常数。内间隙壁134与174的低介电常数材料包含氮氧化硅(SiON)、一氧化硅(SiO)、氮碳氧化硅(SiONC)、碳氧化硅(SiOC)、或其他适合的低介电常数介电材料的一或多个。在一些实施方式中，内间隙壁134及174材料的介电常数值与外间隙壁132及172材料的介电常数值相同。在一例子中，内间隙壁134及174亦包含一或多个空气间隔邻近于各自的栅极结构130及170或各自的源极/漏极结构140及180的一或多个。
在一实施方式中，基底层190设于基材102内且位于元件110或元件150 的一或多个的下方。图1显示出基底层190设于基材区104内且位于元件110 之下，其作为一个例示例子，而未限制本揭露的实施方式的范围。在一实施方式中，基底层190包含硅锗基底层192，硅锗基底层192直接形成在下方基材 102，例如N型井104之上。在一些情况中，硅基底层194形成于硅锗基底层 192之上，硅基底层194与硅锗基底层192均为基底层190的一部分。在一些实施方式中，基底层190可包含多个硅锗基底层与多个硅基底层以交替方式垂直堆叠。在一实施方式中，基底层190的表面190S与基材102的表面102S 实质等高。
在一实施方式中，基底层190包含底部190B与倾斜侧壁部190SW。底部 190B与倾斜侧壁部190SW之间的角度θ1落在约5度至约89度之间的范围内。在一实施方式中，角度θ1落在约45度至约65度之间的范围内。在又一实施方式中，于基材102为结晶硅的例子中，角度θ1实质约为54.7度。
硅锗基底层192的厚度T1的范围介于约2nm至如硅锗基底层192的硅锗材料的关键厚度般大。硅锗材料的关键厚度取决于硅锗材料的锗浓度。硅锗 (Si1-xGex)的关键厚度是指硅锗(Si1-xGex)于因错位差排形成而发生应变的松弛前可在硅上方成长的最大厚度。硅锗(Si1-xGex)的关键厚度强烈地取决于锗含量，即“x”。具体而言，愈高的锗浓度导致硅锗材料的较低关键厚度。举例而言，在锗基底层190的锗浓度为约20％的例子中，厚度T1落在约2nm至约 60nm的范围内。
纳米线带120与纳米线带160由磊晶层的堆叠所组成，磊晶层的堆叠是以不同磊晶成长程序分别沉积。在一实施方式中，纳米线带160的磊晶层沉积于第一区中，而纳米线带120的磊晶层沉积于包含在第一区内的第二区中。具体而言，纳米线带120的磊晶层形成于沟渠中，而此沟渠形成在纳米线带160 的磊晶层中。在此详细描述沉积程序。纳米线带120与纳米线带160可包含不同厚度。由于应用于制作元件110及150的一者的牺牲带与第一元件110或第二元件150的另一者的纳米线带120及160并非由相同磊晶层组成，因此它们无须对齐彼此。因此，元件110及150的一者的内间隙壁134及174可能没有侧向对齐元件150及110的另一者的纳米线带160及120。再次注意，如在此以更详细的方式所描述，纳米线带120与纳米线带160由磊晶层的堆叠所组成，且磊晶层的堆叠以不同磊晶程序分别沉积。
图1显示出n型井104与p型井106彼此邻接形成，但并不限制于此。在其他实施方式中，p型井106与n型井104可被一或多个绝缘体，例如浅沟渠绝缘(“STI”)，所隔开。图1显示出应用双筒(dual-tub)制程，即p型井106 与n型井104均形成在基材102中。其他制程，如p型井制程于n型基材中或 n型井制程于p型基材中，亦是可行的且包含在本揭露的实施方式中。意即，基材区104及106的一者位于掺杂的局部区中，另一者位于掺杂的基材中是可行的。基材区104与基材区106均为本质(intrinsic)或本质(intrinsically)掺杂，例如非故意掺杂，亦是可以的。
图2是绘示一种制造集成电路元件，例如图1的例示集成电路100，的例示制程。图3A至图3J是绘示一晶圆300在依照图2的例示制程的制造例示集成电路100的制程中的不同阶段的剖面图。
在例示操作205中，接收晶圆300。图3A显示出晶圆300包含基材102，且基材102包含基材区104，例如n型井，以及基材区106，例如p型井，基材区104及106在基材102的上表面102S处彼此共平面。作为例示例子，基材102为{100}结晶晶面的硅基材。作为一个非限制性的例示例子，图3A显示出基材区104与基材区106彼此交接。n型井104可用V族元素的掺质或杂质，如砷或磷或其各种组合，而以各种方式掺杂。p型井106可用III族元素的掺质或杂质，如硼或镓或其各种组合，而以各种方式掺杂。
在例示操作210中，亦请参照图3B，全面性地形成半导体磊晶层的第一堆叠310于基材区104与基材区106两者的顶部上。用语“全面性(globally)”意指第一堆叠310形成于基材区104与106两者上，相较于“局部(locally)”是意指基材区104或基材区106的一者。在此所使用的用语“全面性”未必指第一堆叠310形成于晶圆的整个表面上方。在一实施方式中，第一堆叠310 包含第一半导体材料的多个磊晶层312(如图示例子所示的四层)以及第二半导体材料的多个磊晶层314(如图示例子所示的四层)。在一实施方式中，层312 为硅锗，层314为硅。
在一实施方式中，每个硅锗磊晶层312具有厚度T2，厚度T2在约2nm 至约6nm的范围内。每个硅磊晶层314具有厚度T3，厚度T3在约4nm至约 10nm的范围内。在一实施方式中，硅磊晶层314的厚度T3大于硅锗磊晶层 312的厚度T2。在一实施方式中，硅磊晶层314的厚度T3为约8nm，且硅锗磊晶层312的厚度T2为约5nm。
利用减压化学气相沉积(“RP-CVD”)、电浆增益化学气相沉积(“PECVD”)、常压化学气相沉积、感应耦合(inductively coupled)电浆增益化学气相沉积、热丝(hot wire)化学气相沉积、原子层沉积、分子层沉积、或其他适合磊晶方法，来形成第一堆叠310的磊晶层312与314。
在例示操作215中，亦请参照图3C，形成沟渠320穿过第一基材区104 上方的第一堆叠310。举例而言，形成氧化物罩幕层或光阻层321，并予以图案化而暴露出形成沟渠320的表面。沟渠320暴露出第一基材区104的至少一部分。在一实施方式中，利用干蚀刻制程，例如反应离子蚀刻(“RIE”)或其他适合干蚀刻制程，形成沟渠320。由于反应离子蚀刻是定向的，因此沟渠320 的侧壁320SW相对垂直。期望沟渠320的底部320B是相对平坦。然而，在实际生产中，反应离子蚀刻可能产生包含相对平坦的中央底部320BB与倾斜底侧壁部320BS。在图3C中，中央底部320BB与倾斜底侧壁部320BS以虚线绘示。
在例示操作220中，亦请参照图3D，沉积共形介电层322于包含第一堆叠310与沟渠320的晶圆300上方。介电层322为氧化物、氮化物、或其他适合介电材料，且利用化学气相沉积、原子层沉积、或其他适合沉积技术制作。介电层322的沉积厚度为约5nm至约60nm。将介电层322仅沉积在沟渠320 内而没有沉积在第一堆叠310之上亦是可行的。在一实施方式中，罩幕层231 仍覆盖第一堆叠310。
在例示操作225中，亦请参照图3E，形成元件间隙壁108于第一堆叠310 与沟渠320之间。具体而言，元件间隙壁108将沟渠320与第一堆叠310侧向隔开。元件间隙壁108是利用图案化介电层322而形成。在后续制程中，例如于后来移除罩幕层321后，可能改变元件间隙壁108的尺寸，其为半导体晶圆制造领域中可获得理解的。
在元件间隙壁108的制作下，沟渠320的底部320B可受到蚀刻进一步的影响，底部320B实际上可包含相对平坦的底部320BB与倾斜底侧壁部320BS，如虚线所示。
在例示操作230中，亦请参照图3F，通过修改沟渠320的底部320B，形成凹陷部330。在一实施方式中，透过非等向性蚀刻完成此修改，非等向性蚀刻对于基材102的材料的不同结晶晶面取向具有不同蚀刻速率。举例而言，在基材102为硅的例子中，可利用氨、氯化氢(HCl)、氢氧化钾(KOH)、四甲基氢氧化铵(TMAH)、或乙二胺邻苯二酚(EDP)等蚀刻剂中的一或多种来执行晶体非等向性蚀刻。举例而言，对于氨，在各硅晶面中的相对蚀刻速率为{110}> {100}>>{110}。对于氯化氢，在{100}、{110}、与{111}晶面中的蚀刻速率差异为10：78：9。对于氢氧化钾，在{100}、{110}、与{111}晶面中的蚀刻速率差异为300：600：1。对于四甲基氢氧化铵，在{100}、{110}、与{111}晶面中的蚀刻速率差异为37：68：1。对于乙二胺邻苯二酚，在{100}、{110}、与{111}晶面中的蚀刻速率差异为20：10：1。通过应用适合的蚀刻剂于蚀刻制程中，可形成凹陷部330的对应外形。举例而言，在基材102为硅的{100} 晶面的例子中，氢氧化钾或四甲基氢氧化铵蚀刻剂将形成具有相对平坦底部 330B、以及实质位于硅的{111}晶面的倾斜侧壁部330BS的凹陷部330。利用蚀刻速率在硅的{100}、{110}、与{111}晶面中的巨大差异可达成此形状。举例而言，在一实施方式中，凹陷部330的侧壁330BS与底部330B之间的角度θ2实质为54.7度，其基本上为硅的{111}晶面平面至{100}晶面平面之间的角度。
通过选用不同的蚀刻剂与不同的蚀刻条件，例如蚀刻剂溶液浓度、温度、压力等等，凹陷部330的外形或形状会改变。举例而言，角度θ2可在约5度至约89度之间变化。此角度范围对于维持侧壁330BS倾斜而非铅直/垂直，例如90度，是重要的。凹陷部330的深度D1，例如从底部330B至基材102的表面，亦可从约2nm变化至约80nm。然而，所有那些变化可受到控制或为可控制的变化。因此，透过模拟或实验数据，相对确定或得知凹陷部330所生成的外形与形状，例如角度θ2及/或深度D1的参数。所生成的凹陷部330的这些已知参数使得技术可以适当方式来填充凹陷部330，如此一或多个填充物层的表面相对平坦。
在一实施方式中，由于非等向性蚀刻制程是在元件间隙壁108形成后进行，因此蚀刻制程移除元件间隙壁108下方的基材102的部分。因此，形成底切(undercut)，且凹陷部330的边缘330E延伸于元件间隙壁108的下方。
在例示操作235中，亦请参照图3G，形成半导体基底层340于凹陷部330 内并填充凹陷部330。在一实施方式中，半导体基底层包含具有填隙特性的材料的半导体基底层。举例而言，硅锗为适合的填隙特性的半导体材料。在一实施方式中，半导体基底层340包含一或多个硅锗层342，具有其中一硅锗层342 直接位于下方的基材102上。意即，硅锗层342填充凹陷部330的底部330B 上的微小间隙，若有任何微小间隙的话，而这些微小间隙不会转移到硅锗基底层342的上表面342U。
在一实施方式中，将磊晶制程应用在沉积硅锗基底层342上。以硅锗材料沿凹陷部330的底部330B的晶面取向346成长快于沿侧壁330BS的晶面取向 348的方式调整磊晶制程。因此，沿晶面取向348的磊晶成长受到抑制，且硅锗基底层342实质沿取向346沉积而具有实质平坦的上表面342U。举例而言，在倾斜侧壁300BS位于硅的{111}晶面平面且底部330B位于硅的{100}晶面平面的例子中，调整硅锗磊晶制程，以沉积{100}晶面硅锗。因晶格不匹配，所成长的{100}晶面的硅锗并没有停留在{111}晶面硅的倾斜侧壁330BS上。举例而言，磊晶制程可包含范围介于约500℃至约650℃的温度、以及范围介于约10Torr至300torr的压力。前驱物可为SiH2Cl2(“二氯硅烷”)与GeH4(“锗烷”)、硅甲烷(SiH4)、乙硅烷(Si2H6)与二锗烷(Ge2H6)、或其他适合硅与锗的前驱物。
应了解到的是，根据凹陷330的已知或确定的参数，例如侧壁330BS的角度θ2，来调整硅锗基底层的磊晶制程。当角度θ2非正好54.7度时，例如{111} 晶面，侧壁330BS的晶面取向348可能包含{100}晶面、{110}晶面、与{111} 晶面成分。磊晶制程的微调确定适合的一组磊晶条件，以实现硅锗层342沿晶面取向346而非晶面取向348的选择性成长。此外，例示操作235与例示操作 230亦可以相反的方式配合，其中根据固定的磊晶制程，例如在不同晶面取向中采已知的硅锗沉积速率，决定侧壁330BS的角度θ2。借此，选择适合的晶体非等向性蚀刻制程，以形成适合磊晶制程的具确定角度θ2的凹陷部330。
利用所应用的此技术，修改或决定沟渠320的底部外形。透过模拟或实验，获得如角度θ2与深度D1的参数。利用所提供的这类参数，形成硅锗基底层 342的磊晶制程为可控制的，借以实现相对平坦的上表面342U。
此外，利用所提供的凹陷部330的深度D1，可准确设计硅锗磊晶层342 的沉积厚度，并可在磊晶制程期间透过例如振荡石英谐振器(oscillating quartz resonator)临场(in-situ)监控硅锗磊晶层342的沉积厚度。这样的临场监控对磊晶制程的薄膜沉积部分的厚度控制提供实质即时回馈。因此，通过在沉积制程期间透过即时监控与回馈方式动态优化磊晶参数，可提升磊晶层342的厚度的精确控制。
此外，延伸在元件间隙壁108下方的边缘330E的结构特征对硅锗磊晶层 342提供一个深宽比(aspect ratio)变化基准。利用此深宽比变化基准，可控制磊晶制程，如此基底层340的硅锗磊晶层342或任何额外磊晶层停在边缘330E 处或在元件间隙壁108的下表面108L。因此，在元件间隙壁108所在之处，上表面340U与基材102的上表面102U实质等高。此外，基底层340的边缘部340E延伸在元件间隙壁108的下表面108L下。
在一实施方式中，根据形成于半导体基底层340上方的磊晶层的材料，可形成另一基底层344于硅锗基底层342之上。举例而言，可形成硅基底层344 于硅锗基底层342之上。将侧壁330BS的晶面方向348上与底部330B的晶面方向346上的磊晶成长的类似控制应用于硅基底层344的沉积上。如此一来，硅基底层344的上表面相对平坦。
作为图示例子，图3G显示出半导体基底层340分别包含硅锗层342与硅层344两层。此特定例子并非限制本揭露的实施方式的范围。基底层340可包含其他适合沿不同晶面方向选择性磊晶成长的半导体材料。此外，根据凹陷部 330的深度D1、一基底层的关键厚度、以及直接成长在基底层340的上表面 340U上的磊晶层的材料，半导体基底层340可包含超过二层的不同基底层。举例而言，硅锗基底层342应较其关键厚度薄，以维持结构完整性。硅锗层的关键厚度取决于其锗浓度。举例而言，在锗浓度为约20％的例子中，关键厚度为约60nm。
在一实施方式中，形成基底层340包含预烘烤(pre-baking)制程238，预烘烤制程238在基底层340的磊晶制程前加热凹陷部330。预烘烤制程238移除凹陷部330的底部上的原始氧化物。在一实施方式中，以800℃至950℃的表面温度、100Torr至300Torr的表面压力、以及氢流，进行约10秒至100秒的预烘烤制程。
在例示操作240中，亦请参照图3H，形成磊晶层352与354的第二堆叠 350于基底层340之上与沟渠320内。第二堆叠350包含硅锗磊晶层352与硅磊晶层354以交替方式垂直堆叠。在一实施方式中，第二堆叠350中的硅锗层 352的厚度T4与第一堆叠310中的硅锗层312的厚度T2不同。第二堆叠350 中的硅层354的厚度T5与第一堆叠310中的硅层314的厚度T3不同。此外，在第二堆叠350中，硅锗层352的厚度T4不同于硅层354的厚度T5。
此外，当第二堆叠350的硅锗层352与第一堆叠310的硅锗层312个别形成时，硅锗层352可包含不同于硅锗层312的锗浓度。
如图3H所示，于第二堆叠350形成后。可透过例如蚀刻或平坦化移除罩幕层321(图3G)，且可透过平坦化制程将元件间隙壁108截短，以降低垂直尺寸。
在一实施方式中，可针对第一堆叠310与第二堆叠350分别设计厚度T2、 T3、T4、与T5。因素可能包含各别磊晶层312、314、352、与354是用以形成通道纳米线带或作为牺牲纳米线带。因素亦可能包含欲从此形成的元件的各别类型。分别形成第一堆叠310与第二堆叠350，以制作不同类型的元件，例如n型场效晶体管与p型场效晶体管元件。利用所揭露的技术，分别形成第一堆叠310与第二堆叠350，且分别控制磊晶层312、314、352、与354的厚度T2、T3、T4、与T5，以符合各别的元件，例如n型场效晶体管与p型场效晶体管元件，的独特元件设计或操作设计。
在一实施方式中，为有利于后续的制造制程，第一堆叠310与第二堆叠 350个别的上表面310U与上表面350U实质等高。第二堆叠350的硅锗层352 的厚度T4与第一堆叠310的硅层314的厚度T3实质相同，在此例如8nm。第二堆叠350的硅层354的厚度T5与第一堆叠310的硅锗层312的厚度T2 实质相同，在此例如5nm。
图3H显示出第一堆叠310与第二堆叠350在个别的硅锗磊晶层312与352 以及硅磊晶层314与354中包含相同顺序。意即，堆叠310与350均在底部以硅锗磊晶层312与352开始，而在顶部以硅磊晶层314与354结束。图示例子并未限制本揭露的实施方式的范围。第一堆叠310或第二堆叠350的一或多个可在底部以硅磊晶层开始，其亦可行且包含在本揭露的实施方式中。
作为图示例子，图3H显示出第二堆叠350与第一堆叠310均包含硅与硅锗磊晶层。此例子并未限制本揭露的实施方式的范围。在其他例子中，第二堆叠350可包含不同于第一堆叠310的磊晶层的材料组合的磊晶层材料组合。
在栅极全环制程中，第一堆叠310的硅磊晶层314用以制作n型场效晶体管元件的纳米线通道区，第一堆叠310的硅锗磊晶层312用以制作牺牲纳米线带，例如后来将被移除。第二堆叠350的硅锗磊晶层352用以制作p型场效晶体管元件的纳米线通道区，第二堆叠350的硅磊晶层354用以制作牺牲纳米线带。
在例示操作245中，亦请参照图3I，图案化第一堆叠310与第二堆叠350，以形成硅锗纳米线带312与硅纳米线带314的第一图案化堆叠310P、以及硅锗纳米线带352与硅纳米线带354的第二图案化堆叠350P。在一些实施方式中，第一图案化堆叠310P与第二图案化堆叠350P为鳍状。
在一些实施方式中，此图案化亦可能形成鳍状基材部106P与104P(均以虚线表示)分别位于鳍状的第一图案化堆叠310P与第二图案化堆叠350P下方。可形成介电层环绕鳍状基材部106P与104P分别达第二基材区106与基底层 340的上表面106U与340U的高度。鳍状基材部104P包含基底层340的图案化部196(图1)。
在例示操作250中，亦请参照图3J，利用栅极全环(“GAA”)制程，分别形成n型场效晶体管元件150与p型场效晶体管元件110于第一图案化堆叠 310P与第二图案化堆叠350P之上。举例而言，n型场效晶体管元件150的通道160由硅纳米线带314所组成，p型场效晶体管元件110的通道120由硅锗纳米线带352所组成。移除硅锗的牺牲纳米线带312，且以n型场效晶体管元件150的栅极结构170取代。移除硅的牺牲纳米线带354，且以p型场效晶体管元件110的栅极结构130取代。
硅锗基底层192(由基底层342图案化)与硅基底层194(由基底层344图案化)为p型场效晶体管元件110下方的图案化基材104P的一部分。基底硅锗层 192与基底硅层194并非用以制作通道区120，因其沉积是为了填充凹陷部330 而非为了供制作通道区。
由于基底层340的边缘部340E延伸在元件间隙壁108之下，因此边缘部 340E的至少一部分于图案化基材104且形成鳍状基材图案104P后会留下。在一实施方式中，留下的边缘部340E在顶部邻接元件间隙壁108且在侧边邻接介电层360。留下的边缘部340E为基底层190的一部分，且均图案化自相同基底层340。
如所见，图3J从不同于图1的视角显示元件110与150。图1与图3J的任一者或两者并非用以在关于一集成电路中呈互补方式的n型场效晶体管元件150与p型场效晶体管元件110之间的相对位置及/或连接安排上限制本揭露的实施方式的范围。
如在此所描述的，在个别形成的纳米线堆叠310与350中的纳米线带312、 314、352、与354的顺序、材料、厚度、或其他参数可针对每个元件150与 110个别订制与优化。这样的弹性在分别与各别改善p型场效晶体管与n型场效晶体管元件的元件性能上有优势。此外，元件间隙壁108整合在纳米线堆叠 310与350的制作中，而简化互补式金氧半导体制程至高电压模拟制程的整合，如双极性-互补式金氧半元件-扩散式金氧半元件(Bipolar-CMOS-DMOS，“BCD”)制程。
此外，所揭露的形成基底层340的技术解决了在沟渠的倾斜底部中磊晶成长的问题。凹陷部330的经控制的晶面角度以及基底层340中的基底层的经控制的磊晶成长实现基底层340的相对平坦上表面。这样的基底层340有利于在其上方的半导体层的磊晶成长。
在图3C的一个替代或另一实施方式中，于沟渠320形成后，硬罩幕层留在第一堆叠310之上。举例而言，在蚀刻沟渠320时，可将硬罩幕层图案化为蚀刻终止层。透过蚀刻形成沟渠320后，并未移除或者近来未移除硬罩幕层。留下的硬罩幕层可在包含蚀刻部分或后续化学机械研磨(CMP)制程的后续制程中作为额外的蚀刻终止层或化学机械研磨终止层。举例而言，后续磊晶制程可能包含蚀刻部分。硬罩幕层为氧化硅、氧化铝铪、氧化镁铝、氮化硅、或其他适合蚀刻终止材料的一或多种。
硬罩幕层在移除沉积在第一堆叠310上方的过量介电层322中作为蚀刻终止或化学机械研磨终止层。
可保留硬罩幕层直至形成第二堆叠350于沟渠320中，形成第二堆叠350 时是利用类似于图3F至图3H所示的那些制程的制程。于第二堆叠350已经形成后，可例如利用研磨制程移除硬罩幕层，而可得到图3H的结构。
可由以下的实施方式的描述更理解本揭露的实施方式：
在一实施方式中，一种集成电路包含基材，基材包含第一基材区与第二基材区。集成电路亦包含第一元件位于第一基材区之上以及第二元件位于第二基材区之上。第一元件包含第一半导体材料的第一复数个纳米线带、第一栅极结构环绕至少一第一复数个纳米线带、以及第一源极/漏极结构接触此至少一第一复数个纳米线带。第二元件包含第二半导体材料的第二复数个纳米线带位于第二基材区之上、第二栅极结构环绕至少一第二复数个纳米线带、以及第二源极/漏极结构接触此至少一第二复数个纳米线带。集成电路亦包含半导体基底层嵌在第一基材区或第二基材区的一中，且位于第一元件或第二元件的对应一者之下。
在一实施例中，集成电路还包含元件间隙壁设于第一元件与第二元件之间。在一实施例中，半导体基底层延伸在元件间隙壁之下。在一实施例中，第一复数个带包含第一带与第二带邻近第一带，第一带与第二带之间的垂直距离小于第一带的厚度。在一实施例中，第二复数个带包含第三带与第四带邻近于第三带，第三带与第四带之间的垂直距离小于第三带的厚度。在一实施例中，第一半导体材料为硅，第二半导体材料为硅锗。在一实施例中，半导体基底层包含硅锗基底层直接位于基材之上。在一实施例中，半导体基底层还包含硅基底层位于硅锗基底层之上。在一实施例中，半导体基底层的侧壁倾斜。
在一结构实施方式中，结构包含基材、基底层嵌于基材中的凹陷部中、元件位于半导体基底区之上。基底区包含不同于基材的材料。元件包含半导体材料的复数个纳米线带、栅极结构环绕至少一复数个纳米线带、以及源极/漏极结构接触此至少一复数个纳米线带。
在一结构实施方式中，结构包含基材、基底层、以及元件。基底层嵌于基材的凹陷部中。元件位于基底层之上，元件包含半导体材料的复数个带、栅极结构环绕复数个带的至少一者、以及第一源极/漏极结构接触复数个带的此至少一者。基底层包含不同于基材的材料。
在一实施例中，基底层侧向延伸在复数个带之外。在一实施例中，结构还包含介电元件间隙壁位于基材之上，基底层的边缘延伸在介电元件间隙壁之下。在一实施例中，栅极结构与源极/漏极结构被内间隙壁隔开。
在一方法实施方式中，形成第一复数个半导体层的第一堆叠于结晶基材之上，形成沟渠于第一堆叠中，以透过沟渠暴露出结晶基材。形成元件间隙壁邻近沟渠的侧壁。利用蚀刻制程形成凹陷部于沟渠的底部，此蚀刻制程在结晶基材的结晶晶面中为非等向性，如此凹陷具有底部以及对底部具有一角度的倾斜侧壁部。形成半导体基底层于凹陷部内。形成第二复数个半导体层的第二堆叠于半导体基底层之上。
在一实施例中，形成半导体基底层包含预烘烤制程。在一实施例中，倾斜侧壁部对底部的角度介于约5度至约89度之间。在一实施例中，结晶基材为硅，且角度落在介于约45度至约65度之间的范围内。在一实施例中，利用磊晶制程在形成半导体基底层中，磊晶制程沿倾斜侧壁部的晶面取向形成半导体基底层的磊晶材料较沿底部的晶面取向慢。在一实施例中，第一堆叠包含第一硅锗层，第二堆叠包含第二硅锗层，第二硅锗层包含不同于第一硅锗层的锗浓度。在一实施例中，第一堆叠包含第一硅层，第二堆叠包含第二硅层，第二硅层包含不同于第一硅层的厚度。
可结合上述的多个实施方式，以提供更多的实施方式。在此说明书中所参照及/或列在申请资料表中的所有专利案、专利申请公开案、专利申请案、以及非专利出版品全体在此并入参照。若需应用各个专利案、申请案、或出版品的概念以提供更进一步的实施方式时，可修改实施方式的态样。
鉴于上面的详细描述，可对实施方式进行这些与其他改变。一般而言，在下列的申请专利范围中，所使用的用语不应解释为将申请专利范围限制于说明书与申请专利范围中所揭露的特定实施方式，而应解释成包含所有可能实施方式与这些申请专利范围所被授予的等效的全部范围。因此，申请专利范围不受限于此揭露的实施方式。

Claims (20)

1.一种集成电路，其特征在于，该集成电路包含：
一基材，包含一第一基材区与一第二基材区；
一第一元件，包含一第一半导体材料的一第一复数个带位于该第一基材区之上、一第一栅极结构环绕该第一复数个带的至少一者、以及一第一源极/漏极结构接触该第一复数个带的该至少一者；
一第二元件，包含一第二半导体材料的一第二复数个带位于该第二基材区之上、一第二栅极结构环绕该第二复数个带的至少一者、以及一第二源极/漏极结构接触该第二复数个带的该至少一者；以及
一半导体基底层，嵌在该第一基材区或该第二基材区的一者中，且位于该第一元件或该第二元件的对应一者之下，该半导体基底层的一侧壁倾斜。
2.根据权利要求1所述的集成电路，其特征在于，该集成电路还包含一元件间隙壁设于该第一元件与该第二元件之间。
3.根据权利要求2所述的集成电路，其特征在于，该半导体基底层延伸在该元件间隙壁之下。
4.根据权利要求1所述的集成电路，其特征在于，该第一复数个带包含一第一带与一第二带邻近该第一带，该第一带与该第二带之间的一垂直距离小于该第一带的一厚度。
5.根据权利要求4所述的集成电路，其特征在于，该第二复数个带包含一第三带与一第四带邻近于该第三带，该第三带与该第四带之间的一垂直距离小于该第三带的一厚度。
6.根据权利要求1所述的集成电路，其特征在于，该第一半导体材料为硅，该第二半导体材料为硅锗。
7.根据权利要求1所述的集成电路，其特征在于，该半导体基底层包含一硅锗基底层直接位于该基材之上。
8.根据权利要求7所述的集成电路，其特征在于，该半导体基底层还包含一硅基底层位于该硅锗基底层之上。
9.根据权利要求1所述的集成电路，其特征在于，该基材包含一结晶基材。
10.一种集成电路，其特征在于，该集成电路包含：
一基材；
一基底层，嵌于该基材的一凹陷部中，该基底层的一侧壁倾斜；以及
一元件，位于该基底层之上，该元件包含一半导体材料的复数个带、一栅极结构环绕该复数个带的至少一者、以及一第一源极/漏极结构接触该复数个带的该至少一者；
其中该基底层包含不同于该基材的一材料。
11.根据权利要求10所述的集成电路，其特征在于，该基底层侧向延伸在该复数个带之外。
12.根据权利要求10所述的集成电路，其特征在于，该集成电路还包含一介电元件间隙壁位于该基材之上，该基底层的一边缘延伸在该介电元件间隙壁之下。
13.根据权利要求10所述的集成电路，其特征在于，该栅极结构与该源极/漏极结构被一内间隙壁隔开。
14.一种集成电路的制造方法，其特征在于，该方法包含：
形成一第一复数个半导体层的一第一堆叠于一结晶基材之上；
形成一沟渠于该第一堆叠中，以暴露出该结晶基材；
形成一元件间隙壁邻近该沟渠的一侧壁；
利用一蚀刻制程形成一凹陷部于该沟渠的一底部，该蚀刻制程在该结晶基材的复数个结晶晶面中为非等向性，该凹陷具有一底部以及对该底部具有一角度的一倾斜侧壁部；
形成一半导体基底层于该凹陷部内；以及
形成一第二复数个半导体层的一第二堆叠于该半导体基底层之上。
15.根据权利要求14所述的方法，其特征在于，形成该半导体基底层包含一预烘烤制程。
16.根据权利要求14所述的方法，其特征在于，该倾斜侧壁部对该底部的该角度介于5度至89度之间。
17.根据权利要求16所述的方法，其特征在于，该结晶基材为硅，且该角度落在介于45度至65度之间的一范围内。
18.根据权利要求14所述的方法，其特征在于，利用一磊晶制程在形成该半导体基底层中，该磊晶制程沿该倾斜侧壁部的一晶面取向形成该半导体基底层的一磊晶材料较沿该底部的一晶面取向慢。
19.根据权利要求14所述的方法，其特征在于，该第一堆叠包含一第一硅锗层，该第二堆叠包含一第二硅锗层，该第二硅锗层包含不同于该第一硅锗层的一锗浓度。
20.根据权利要求14所述的方法，其特征在于，该第一堆叠包含一第一硅层，该第二堆叠包含一第二硅层，该第二硅层包含不同于该第一硅层的一厚度。
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