CN104377199A - 嵌入在mos器件中的锗阻挡件 - Google Patents
嵌入在mos器件中的锗阻挡件 Download PDFInfo
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- CN104377199A CN104377199A CN201410376999.XA CN201410376999A CN104377199A CN 104377199 A CN104377199 A CN 104377199A CN 201410376999 A CN201410376999 A CN 201410376999A CN 104377199 A CN104377199 A CN 104377199A
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
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- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
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- H01L29/772—Field effect transistors
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Abstract
本发明提供了一种集成电路结构,包括位于半导体衬底上方的栅叠件以及延伸至半导体衬底内的开口,其中,开口邻近栅叠件。第一硅锗区位于开口中,其中,第一硅锗区具有第一锗百分比。第二硅锗区位于第一硅锗区的上方,其中,第二硅锗区的第二锗百分比大于第一锗百分比。第三硅锗区位于第二硅锗区的上方,其中,第三硅锗区的第三锗百分比小于第二锗百分比。本发明还提供了一种形成集成电路结构的方法。
Description
技术领域
本发明总体涉及半导体,更具体地,涉及金属氧化物半导体(MOS)。
背景技术
金属氧化物半导体(MOS)器件是集成电路的重要部件。MOS器件的性能影响着其中设置有MOS器件的整个集成电路的性能。因此,已研究了用于提高MOS器件的性能的方法。
发明内容
根据本发明的一方面,提供了一种集成电路结构,包括:半导体衬底;栅叠件,位于半导体衬底的上方;开口,延伸至半导体衬底内,其中,开口邻近栅叠件;第一硅锗区,位于开口中,其中,第一硅锗区具有第一锗百分比;第二硅锗区,位于第一硅锗区的上方,其中,第二硅锗区的第二锗百分比大于第一锗百分比;以及第三硅锗区,位于第二硅锗区的上方,其中,第三硅锗区的第三锗百分比小于第二锗百分比。
优选地,该集成电路结构还包括:基本不含锗的硅盖,位于第三硅锗区的上方。
优选地,该集成电路结构还包括:金属硅化物区,位于硅盖的上方并且与硅盖接触。
优选地,第二锗百分比与第一锗百分比之间的差大于约10%。
优选地,第二锗百分比与第三锗百分比之间的差大于约10%。
优选地,第一硅锗区和第三硅锗区中的至少一个具有持续增加的锗百分比,并且第一硅锗区和第三硅锗区中的至少一个的上部的锗百分比大于相应的下部中的锗百分比。
优选地,该集成电路结构还包括:金属氧化物半导体(MOS)器件,其中,第二硅锗区和硅锗区形成MOS器件的源/漏极区。
根据本发明的另一方面,提供了一种集成电路结构,包括:
半导体衬底;
栅叠件,位于半导体衬底的上方,其中,栅叠件包含在金属氧化物半导体(MOS)器件中;
MOS器件的源/漏极区,延伸至半导体衬底内,其中,源/漏极区包括:第一硅锗层,其中,第一硅锗层具有第一锗百分比;第二硅锗层,位于第一硅锗层的上方,其中,第二硅锗层的第二锗百分比比第一锗百分比大约10%;以及第三硅锗层,位于第二硅锗层的上方,其中,第三硅锗层的第三锗百分比比第二锗百分比小约10%;以及金属硅化物区,位于第三硅锗层的上方并且电连接至第三硅锗层。
优选地,第一硅锗层和第二硅锗层低于衬底和栅叠件之间的界面。
优选地,第二锗百分比大于第一锗百分比,并且第二锗百分与第一锗百分比之间的差介于约10%至约50%的范围内。
优选地,锗百分比在第一硅锗层和第二硅锗层之间的界面处发生急剧变化。
优选地,锗百分比在第二硅锗层和第三硅锗层之间的界面处发生急剧变化。
优选地,第一硅锗层的厚度介于约1nm至约10nm的范围内。
优选地,第二硅锗层的厚度介于约1nm至约10nm的范围内。
根据本发明的又一方面,提供了一种方法,包括:在半导体衬底的上方形成栅叠件;形成延伸至半导体衬底内的开口,其中,开口位于栅叠件的一侧;实施第一外延以在开口中生长第一硅锗层,其中,第一硅锗层具有第一锗百分比;实施第二外延以在第一硅锗层的上方生长第二硅锗层,其中,第二硅锗层的第二锗百分比大于第一锗百分比;以及实施第三外延以在第二硅锗层的上方生长第三硅锗层,其中,第三硅锗层的第三锗百分比小于第二锗百分比。
优选地,该方法还包括:在从第一外延转换至第二外延的时间点处,增大含锗前体的流速与含硅前体的流速之间的流速比率;以及在从第二外延转换至第三外延的时间点处,降低流速比率。
优选地,该方法还包括:形成位于第三硅锗层的上方并且与第三硅锗层接触的硅盖,其中,硅盖基本不含锗。
优选地,该方法还包括:形成硅盖之后,在栅叠件和硅盖的上方形成层间电介质(ILD);在ILD中形成接触开口,其中,硅盖暴露于接触开口;形成接触开口之后,对硅盖实施硅化;以及用导电材料填充接触开口。
优选地,该方法还包括:在形成硅盖之后,实施硅化以硅化硅盖。
优选地,在第一外延期间,不原位掺杂p型杂质,而在第二外延期间,原位掺杂p型杂质。
附图说明
为了更全面地理解实施例及其优势,现参考结合附图进行的以下描述,其中:
图1至图11是根据一些示例性实施例的金属氧化物半导体(MOS)器件在制造的中间阶段的截面图;以及
图12示意性地示出了根据一些实施例的在MOS器件的外延区中的锗百分比的示例性分布图。
具体实施方式
下面详细讨论本发明各实施例的制造和使用。然而,应该理解,实施例提供了许多可以在各种具体环境中实现的可应用的概念。所讨论的具体实施例仅仅是说明性的,而不用于限制本发明的范围。
在过去的几十年里,降低半导体器件(如,金属氧化物半导体(MOS)器件)的尺寸和固有特征已使集成电路的速度、性能、密度和每单元功能成本得到不断的提高。根据MOS器件的设计及其固有特性中的一个特性,调节MOS器件的位于栅极下面的源极和漏极之间的沟道区的长度改变了与沟道区相关的电阻,从而影响MOS器件的性能。更具体地,缩短沟道区的长度降低了MOS器件的源极至漏极电阻,假设其他参数保持相对不变,当将足够的电压施加给MOS器件的栅极时,这可增强源极和漏极之间的电流。
为了进一步增强MOS器件的性能,可将应力引入MOS器件的沟道区内以提高载流子迁移率。通常,需要在n型MOS(“NMOS”)器件的沟道区中沿着源极至漏极方向引入拉伸应力,而需要在p型MOS(“PMOS”)器件的沟道区中沿着源极至漏极方向引入压缩应力。
一种将压缩应力施加给PMOS器件的沟道区的有效方法是在源极和漏极区中生长SiGe应力源。这种方法通常包括以下步骤:在半导体衬底上形成栅叠件;在栅叠件的侧壁上形成间隔件;在硅衬底内沿着栅极间隔件形成凹槽;以及在凹槽中外延生长SiGe应力源。外延SiGe应力源将压缩应力施加给沟道区,而沟道区位于源极SiGe应力源与漏极SiGe应力源之间。
根据各个示例性实施例提供了一种形成具有应力源的金属氧化物半导体(MOS)器件的工艺。示出了形成MOS器件的中间阶段。讨论了实施例的变化。贯穿各个视图和示例性实施例,相似的参考标号用于指代相似的元件。
图1示出了衬底20,其为晶圆10的一部分。衬底20可以是块状半导体衬底(诸如,硅衬底),或可具有复合结构(诸如,绝缘体上硅(SOI)结构)。可选地,包括III族、IV族和/或V族元素的其他半导体材料也可包含在衬底20中,这样的半导体材料可包括硅锗、碳化硅和/或III族至V族化合物半导体材料。
栅叠件22形成在衬底20的上方,并且包括栅介质24和栅电极26。栅极电介质24可包括氧化硅和/或具有高k值(例如,大于约7)的高k材料。栅电极26可包括常用的导电材料,诸如,掺杂多晶硅、金属、金属硅化物、金属氮化物和它们的组合。栅叠件22还可包括硬掩模28,例如,硬掩模28可包括氮化硅,但是也可使用其他材料,诸如,碳化硅和氮氧化硅等。在形成替代栅极的实施例中,可或可不形成硬掩模28。
如图2所示,例如,通过将p型杂质(诸如,硼和/或铟)注入衬底20内来形成轻掺杂的漏极/源极(LDD)区30。栅叠件22和硬掩模28用作注入掩模,从而使得LDD区30的内边缘分别与栅叠件22的边缘基本对准。可使用介于约1keV至约10keV范围内的能量和介于约1×1013/cm2至约1×1016/cm2范围内的剂量进行LDD注入。然而,应该理解,通篇描述中所引用的值仅为实例,并且可改变为不同的值。LDD注入可以是倾斜或垂直的,并且倾斜角介于约0度至约30度的范围内。此外,例如,可以通过将诸如砷或磷等的n型杂质注入衬底20内来形成口袋(pocket)区32。口袋注入可以是倾斜的,并且倾斜角大于LDD注入的倾斜角。在一些实施例中,口袋注入的倾斜角介于约15度至约45度的范围内。为了清楚,在后续附图中没有示出口袋区32。
参考图3,在栅介质24和栅电极26的侧壁上形成栅极间隔件34。在一些实施例中,每个栅极间隔件34均包括氧化硅层(未示出)和氧化硅层上方的氮化硅层,其中,氧化硅层可具有介于约至约范围内的厚度,而氮化硅层的厚度可介于约至约的范围内。在可选的实施例中,栅极间隔件34包括一个或多个层,每个层均包括氧化硅、氮化硅、氮氧化硅和/或其他介电材料。有效的形成方法包括等离子体增强化学汽相沉积(PECVD)、低压化学汽相沉积(LPCVD)、次大气压化学汽相沉积(SACVD)和其他沉积方法。
还如图3所示,根据一些实施例,可进行各向同性蚀刻以在衬底20内形成开口36。各向同性蚀刻可以是干蚀刻,其中,蚀刻气体可选自CF4、Cl2、NF3、SF6和它们的组合。例如,开口36的深度D1可介于约和约的范围内。在可选的实施例中,跳过图3中的各向同性蚀刻步骤,而是实施图4中的步骤以形成如图4所示的开口36。
接着,如图4所示,实施湿蚀刻以扩展开口36。例如,可使用四甲基氢氧化铵(TMAH)或氢氧化钾(KOH)溶液等实施湿蚀刻。在一些示例性实施例中,TMAH溶液的浓度介于约1%至约30%的范围内。湿蚀刻之后,在开口36中形成小晶面(facet),这些面可包括衬底20的(111)晶面。在一些示例性实施例中,在湿蚀刻之后,例如,开口36的深度D2可以介于约至约的范围内。
例如,使用HF基气体或SiCoNi基气体可进行预清洗。预清洗可以去除由于开口36中暴露的表面的自然氧化而形成的氧化硅。
图5示出了硅锗(SiGe)层38的形成,硅锗(SiGe)层38形成为薄层。在外延过程中,通过选择性外延生长(SEG)工艺在开口36(图4)中外延生长SiGe,从而形成SiGe层38。工艺气体可包括H2、N2、二氯硅烷(DCS)、SiH4、GeH4等。在外延过程中晶圆10的温度可介于约600℃至约900℃的范围内。在一些实施例中,添加蚀刻气体以促进在衬底20的暴露表面上的选择性生长,但是不在诸如栅极间隔件34和硬掩模28的介电质上进行选择性生长。工艺气体的压力可以介于约10托和约200托的范围内。
在一些实施例中,在外延SiGe层38期间,无p型杂质被原位掺杂、或基本无p型杂质(例如,p型杂质浓度低于约1014/cm3)被掺杂。在可选实施例中,在外延生长期间,随着生长的进行而掺杂p型杂质。例如,当要掺杂硼时,在工艺气体中可以包括B2H6。可将SiGe层38中的p型杂质掺杂为低于约1E20/cm3的第一p型杂质浓度PC1。例如,SiGe层38可具有介于约10%至约30%范围内的第一锗原子百分比GP1,但是,也可使用不同的锗百分比。
SiGe层38形成为薄层。在一些实施例中,SiGe层38的厚度T1(SiGe层38的底部的厚度)小于约20nm。厚度T1也可介于约5nm至约30nm的范围内。此外,距离T2介于约1nm至约20nm的范围内。距离T2是SiGe层38的侧壁部分的左边缘和右边缘之间的横向距离,其中,在等于D2/2的深度处测量距离T2,D2/2为凹槽36的深度D2的一半。保持T1值和T2值大于某些值(例如,约1nm)可有利地保持随后形成的富锗层40(图6)不会太靠近衬底20。这样进而减少了由富锗层40和衬底20之间的晶格失配所导致的缺陷。另一方面,保持值T1和T2足够小,(例如,小于约20nm)可保持降低硼扩散的益处,下文将给出后续的讨论。
参考图6,通过外延工艺在SiGe层38的上方生长外延层40。在一些实施例中,外延层40是SiGe层,它的锗原子百分比明显高于SiGe层38中的锗原子百分比。在通篇描述中,外延层40被称为富锗SiGe层。当开始外延生长富锗SiGe层40时,调整工艺条件,并且明显增加含锗前体(诸如,GeH4)的流速与含硅前体(诸如SiH4)的流速之间的流速比率。因此,富锗SiGe层40的第二锗原子百分比GP2明显大于SiGe层38中的锗百分比GP1。在一些示例性实施例中,锗原子百分比GP2介于约30%至约60%的范围内。锗百分比的差(GP2-GP1)可介于约10%和约50%之间。在一些实施例中,富锗SiGe层40的厚度T3可介于约1nm和约10nm之间。
此外,在形成外延区40的外延生长期间,在进行外延的同时,可原位掺杂p型杂质。外延区40中的p型杂质浓度大于SiGe层38中的p型杂质浓度。在一些实施例中,PIM40/PIM38比率(即,外延区40中的p型杂质浓度PIM40与SiGe层38中的p型杂质浓度PIM38的比率)大于约3。在一些实施例中,PIM40/PIM38比也可大于约2。
参考图7,通过外延工艺在外延区40的上方生长外延层42。在一些实施例中,外延层42是SiGe层,它的锗原子百分比GP3明显小于SiGe层40中的锗原子百分比GP2。下文中,外延层42被称为SiGe层42。当SiGe层42的外延开始时,调整工艺条件,并且明显减小含锗前体(诸如,GeH4)的流速与含硅前体(诸如,SiH4)的流速之间的流速比率。因此,SiGe层42中的锗原子百分比GP3明显小于外延区40中的锗百分比GP2。在一些示例性实施例中,锗原子百分比GP3介于约20%至约50%的范围内。锗百分比的差(GP2-GP3)可介于约10%至约50%之间。当SiGe层42的顶面齐平于或高于栅介质24和衬底20之间的界面时,完成外延区42的形成。
在形成外延区42的外延期间,在进行外延的同时,可原位掺杂p型杂质。此外,外延区42中的p型杂质浓度大于SiGe层38中的p型杂质浓度。在一些实施例中,外延区42中的p型杂质浓度PIM42和SiGe层38中的p型杂质浓度PIM38具有大于约3的PIM42/PIM38比率。在一些实施例中,PIM42/PIM38比率也可大于约2。
在一些实施例中,在SiGe层38和42的每个层中,沉积的锗百分比基本均匀。在可选实施例中,SiGe层38和/或SiGe层42具有逐渐且持续变化的锗百分比。在各自的外延期间,含锗前体(诸如,GeH4)的流速可逐渐且持续地变化。在这些实施例中,在锗百分比逐渐变化的层中,层的下部具有的锗百分比小于上部的锗百分比,在区38和42中形成的锗分布与图12所示的锗分布相似。
图12示意性地示出了SiGe层38、40和42中的锗百分比,其为从各自的区域至衬底20的顶面之间的垂直距离的函数。在图7中,垂直距离标示为D3。图12中标示出了区38、40和42以及各自的锗浓度GP1、GP2和GP3。图12示出了区38和42具有持续增加的锗百分比,并且由于锗百分比从GP1急剧增加至GP2并且从GP2急剧降低至GP3,所以在区40中产生锗百分比的弓起(hump)。
在形成SiGe区42之后,在SiGe区42的上方通过外延形成如图8所示的覆盖层44。覆盖层44的组成(包括其中含有的元素以及这些元素的百分比)可与SiGe区42的组成不同。覆盖层44可以是其中不含有锗的纯硅层,或可以是基本纯硅层,具有例如小于2%或1%的锗。因此,在通篇描述中,可选地将覆盖层44称为硅盖。覆盖层44在进行外延的同时可原位掺杂p型杂质,或不原位掺杂。在SiGe层38、42和/或覆盖层44的外延期间,无p型杂质或基本无p型杂质掺杂的实施例中,可实施p型杂质注入以形成各自的MOS器件的源极区和漏极区。
接着,参考图9,去除硬掩模28(如果有)(参考图8),并且根据一些实施例形成替代栅极以代替栅介质24和栅电极26。在可选的实施例中,栅介质24和栅电极26不被替代栅极代替。在形成替代栅极的实施例中,栅介质24和栅电极26(图8)用作被去除的伪栅极。图9示出了包括替代栅极的示例性结构。形成工艺可包括:形成层间介电质(ILD)46;实施CMP以使ILD 46的顶面与栅电极26(或硬掩模28,如果有)的顶面齐平;以及去除伪栅极。然后,可形成栅极介电层和栅电极层以填充通过去除伪栅极所留下的开口,然后通过CMP去除栅极介电层和栅电极层的多余部分。保留的替代栅极包括栅介质24’和栅电极26’。例如,栅介质24’可包括具有(例如)大于约7.0的k值的高k介电材料,并且栅电极26’可包括金属或金属合金。ILD 46可由介电材料(诸如,磷硅酸盐玻璃(PSG)、硼硅酸盐玻璃(BSG)、硼磷硅酸盐玻璃(BPSG)等)形成。接着,形成接触开口48,从而暴露下方的覆盖层44。
图10示出了源/漏极硅化物区52的形成。通过在器件(包括覆盖层44的暴露表面)的上方沉积硅化物金属(诸如,钛、钴、镍、钨等)的薄层(未示出)可形成硅化物区52。然后实施退火以使金属与硅/锗反应。在反应之后,在硅和金属之间形成金属硅化物层。通过使用腐蚀金属但不腐蚀硅化物的蚀刻剂来选择性地去除未反应的金属。由于硅化,源/漏极硅化物区52延伸至覆盖层44内,并且可以延伸至SiGe层42内。可选地,覆盖层44的顶部被硅化,而覆盖层44的底部不被硅化。在硅化之后,覆盖层44的一些剩余部分可能保持不被硅化,其中,覆盖层44的剩余部分齐平于源/漏极硅化物区52并且位于源/漏极硅化物区52的相对两侧上。
图11示出了源/漏极接触插塞54的形成,其中,通过在开口48内填充诸如钨、铜、铝、钛、钴、硅、锗等的导电材料,并且实施CMP以使接触插塞54的顶面齐平于ILD 46的顶面,从而形成源/漏极接触插塞54。因此,形成MOS晶体管60,其包括用作源极区和漏极区的外延层38、40和42和覆盖层44的可能的剩余部分。
本发明的实施例具有一些优势特征。高锗区具有很好地防止硼扩散的能力。因此,通过形成邻近衬底的富锗SiGe层,通过富锗SiGe层可阻止硼从MOS器件的源/漏极区至衬底的扩散。因此,富锗SiGe层和之上的SiGe区可具有高硼浓度而无需担心太多的硼扩散进入沟道内。因为将具有低锗百分比的SiGe薄层插入各富锗SiGe层与衬底之间,所以,将由富锗SiGe层与衬底之间的晶格失配所导致的缺陷降到最少。
根据一些实施例,一种集成电路结构包括位于半导体衬底的上方的栅叠件和延伸至半导体衬底中的开口,其中,开口邻近栅叠件。第一硅锗区位于开口中,其中,第一硅锗区具有第一锗百分比。第二硅锗区位于第一硅锗区的上方,其中,第二硅锗区的第二锗百分比大于第一锗百分比。第三硅锗区位于第二硅锗区的上方,其中,第三硅锗区的第三锗百分比小于第二锗百分比。
根据其他实施例,一种集成电路结构包括半导体衬底、位于半导体衬底的上方的栅叠件和延伸至半导体衬底内的MOS器件的源/漏极区,其中,栅叠件包含在MOS器件中。源/漏极区包括第一硅锗层、位于第一硅锗层的上方的第二硅锗层以及位于第二硅锗层的上方的第三硅锗层。第一硅锗层具有第一锗百分比。第二硅锗层的第二锗百分比第一锗百分比大约10%。第三硅锗层的第三锗百分比比第二锗百分比小约10%。金属硅化物区位于第三硅锗层的上方并且电连接至第三硅锗层。
根据又一些其他实施例,一种方法包括:在半导体衬底的上方形成栅叠件;以及形成延伸至半导体衬底内的开口,其中,开口位于栅叠件的一侧。实施第一外延以在开口中生长第一硅锗层,其中,第一硅锗层具有第一锗百分比。实施第二外延以在第一硅锗层的上方形成第二硅锗层,其中,第二硅锗层的第二锗百分比大于第一锗百分比。实施第三外延以在第二硅锗层的上方形成第三硅锗层,其中,第三硅锗层的第三锗百分比小于第二锗百分比。
尽管已经详细地描述了本实施例及其优势,但是应该理解,在不背离由所附权利要求限定的实施例的精神和范围的情况下,可以对本发明做出各种改变、替代和变化。此外,本申请的范围不旨在限于说明书中描述的工艺、机器、制造、物质组成、工具、方法和步骤的特定实施例。作为本领域的技术人员容易理解,通过本发明,可以使用现有的或今后将开发的用于与本文中所描述的相应实施例实施基本相同的功能或者实现基本相同的结构的工艺、机器、制造、物质组成、工具、方法或步骤。因此,所附权利要求旨在将这些工艺、机器、制造、物质组成、工具、方法或步骤包括在它们的范围内。此外,每个权利要求构成单独的实施例,并且各个权利要求和实施例的组合在本发明的范围内。
Claims (10)
1.一种集成电路结构,包括:
半导体衬底;
栅叠件,位于所述半导体衬底的上方;
开口,延伸至所述半导体衬底内,其中,所述开口邻近所述栅叠件;
第一硅锗区,位于所述开口中,其中,所述第一硅锗区具有第一锗百分比;
第二硅锗区,位于所述第一硅锗区的上方,其中,所述第二硅锗区的第二锗百分比大于所述第一锗百分比;以及
第三硅锗区,位于所述第二硅锗区的上方,其中,所述第三硅锗区的第三锗百分比小于所述第二锗百分比。
2.根据权利要求1所述的集成电路结构,还包括:基本不含锗的硅盖,位于所述第三硅锗区的上方。
3.根据权利要求2所述的集成电路结构,还包括:金属硅化物区,位于所述硅盖的上方并且与所述硅盖接触。
4.根据权利要求1所述的集成电路结构,其中,所述第二锗百分比与所述第一锗百分比之间的差大于约10%。
5.根据权利要求1所述的集成电路结构,其中,所述第二锗百分比与所述第三锗百分比之间的差大于约10%。
6.根据权利要求1所述的集成电路结构,其中,所述第一硅锗区和所述第三硅锗区中的至少一个具有持续增加的锗百分比,并且所述第一硅锗区和所述第三硅锗区中的所述至少一个的上部的锗百分比大于相应的下部中的锗百分比。
7.根据权利要求1所述的集成电路结构,还包括:金属氧化物半导体(MOS)器件,其中,所述第二硅锗区和所述硅锗区形成所述MOS器件的源/漏极区。
8.一种集成电路结构,包括:
半导体衬底;
栅叠件,位于所述半导体衬底的上方,其中,所述栅叠件包含在金属氧化物半导体(MOS)器件中;
所述MOS器件的源/漏极区,延伸至所述半导体衬底内,其中,所述源/漏极区包括:
第一硅锗层,其中,所述第一硅锗层具有第一锗百分比;
第二硅锗层,位于所述第一硅锗层的上方,其中,所述第二硅锗层的第二锗百分比比所述第一锗百分比大约10%;以及
第三硅锗层,位于所述第二硅锗层的上方,其中,所述第三硅锗层的第三锗百分比比所述第二锗百分比小约10%;以及
金属硅化物区,位于所述第三硅锗层的上方并且电连接至所述第三硅锗层。
9.根据权利要求8所述的集成电路结构,其中,所述第一硅锗层和所述第二硅锗层低于所述衬底和所述栅叠件之间的界面。
10.一种方法,包括:
在半导体衬底的上方形成栅叠件;
形成延伸至所述半导体衬底内的开口,其中,所述开口位于所述栅叠件的一侧;
实施第一外延以在所述开口中生长第一硅锗层,其中,所述第一硅锗层具有第一锗百分比;
实施第二外延以在所述第一硅锗层的上方生长第二硅锗层,其中,所述第二硅锗层的第二锗百分比大于所述第一锗百分比;以及
实施第三外延以在所述第二硅锗层的上方生长第三硅锗层,其中,所述第三硅锗层的第三锗百分比小于所述第二锗百分比。
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