CN104347688B - 调节mos器件中的锗百分比 - Google Patents

调节mos器件中的锗百分比 Download PDF

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Publication number
CN104347688B
CN104347688B CN201310594148.8A CN201310594148A CN104347688B CN 104347688 B CN104347688 B CN 104347688B CN 201310594148 A CN201310594148 A CN 201310594148A CN 104347688 B CN104347688 B CN 104347688B
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silicon
silicon germanium
regions
germanium regions
percentage
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CN104347688A (zh
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郭紫微
李昆穆
宋学昌
李啟弘
李资良
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

本发明涉及调节MOS器件中的锗百分比的技术。本发明的集成电路结构包括：位于半导体衬底上方的栅极堆叠件，以及延伸到半导体衬底内的开口，其中开口邻近栅极堆叠件。第一硅锗区域设置在开口中，其中，第一硅锗区域具有第一锗百分比。第二硅锗区域覆盖第一硅锗区域，其中，第二硅锗区域具有大于第一锗百分比的第二锗百分比。金属硅化物区域位于第二硅锗区域上方并与第二硅锗区域接触。

Description

调节MOS器件中的锗百分比
技术领域
本发明总体上涉及半导体领域，更具体地，涉及调节MOS器件中的锗百分比的技术。
背景技术
金属氧化物半导体（MOS）器件是集成电路的关键部件。MOS器件的性能影响MOS器件所在的整个集成电路的性能。因此，已研究了用于提高MOS器件性能的方法。
发明内容
为解决上述问题，本发明提供了一种集成电路结构，包括：半导体衬底；栅极堆叠件，位于半导体衬底上方；开口，延伸到半导体衬底内，其中，开口邻近栅极堆叠件；第一硅锗区域，位于开口中，第一硅锗区域具有第一锗百分比；第二硅锗区域，位于第一硅锗区域上方，第二硅锗区域具有大于第一锗百分比的第二锗百分比；以及金属硅化物区域，位于第二硅锗区域上方且与第二硅锗区域接触。
该集成电路结构还包括：基本上不含锗的硅帽，位于第二硅锗区域上方，其中，金属硅化物区域穿透硅帽。
其中，第二硅锗区域具有第一厚度，并且硅帽具有大于第一厚度的第二厚度。
其中，第二硅锗区域包括下部，其中，下部的顶面与金属硅化物区域的底面接触，并且下部的底面与第一硅锗区域的顶面接触。
其中，第二硅锗区域还包括：位于下部上方的上部，并且第二硅锗区域的上部位于金属硅化物区域的侧面并与金属硅化物区域平齐。
其中，在第一硅锗区域和第二硅锗区域之间的界面处，锗百分比骤然改变。
其中，第二锗百分比比第一锗百分比高出约5%。
此外，还提供了一种集成电路结构，包括：半导体衬底；栅极堆叠件，位于半导体衬底上方，栅极堆叠件包括在金属氧化物半导体（MOS）器件中；MOS器件的源极/漏极区域，延伸到半导体衬底内，源极/漏极区域包括：第一硅锗区域，其中，第一硅锗区域具有第一锗百分比；和第二硅锗区域，位于第一硅锗区域上方，第二硅锗区域具有大于第一锗百分比的第二锗百分比；硅帽，位于第二硅锗区域上方且与第二硅锗区域接触；以及金属硅化物区域，穿透硅帽以与第二硅锗区域接触。
其中，第二锗百分比比第一锗百分比高出约5%。
其中，第二硅锗区域包括：位于第一硅锗区域和金属硅化物区域之间并与第一硅锗区域和金属硅化物区域接触的一部分。
其中，第二硅锗区域的一部分位于金属硅化物区域的下方并覆盖第一硅锗区域。
其中，第二硅锗区域还包括：位于金属硅化物区域的侧面并与金属硅化物区域平齐的额外部分。
其中，第一硅锗区域与第二硅锗区域之间的界面比半导体衬底与栅极堆叠件之间的界面高。
其中，第二硅锗区域具有小于约10nm的厚度。
此外，还提供了一种方法，包括：在半导体衬底上方形成栅极堆叠件；
形成延伸到半导体衬底内的开口，其中，开口位于栅极堆叠的侧边；实施第一外延以在开口中生长第一硅锗区域，其中，第一硅锗区域具有第一锗百分比；实施第二外延以在第一硅锗区域上方生长第二硅锗区域，其中，第二硅锗区域具有大于第一锗百分比的第二锗百分比；以及在第二硅锗区域上方形成基本上不含锗的硅帽，硅帽与第二硅锗区域接触。
该方法还包括：在形成硅帽之后，实施硅化操作来硅化硅帽，其中，由硅化操作形成的金属硅化物与第二硅锗区域的剩余部分接触。
其中，在硅化操作之后，第二硅锗区域的底层保持未被硅化。
其中，在硅帽内不引入锗。
该方法还包括：在形成硅帽之后，在栅极堆叠件和硅帽上方形成层间电介质（ILD）；在ILD中形成接触开口，硅帽暴露于接触开口；在形成接触开口之后，在硅帽上实施硅化；以及使用导电材料填充接触开口。
其中，第二硅锗区域的厚度小于硅帽的厚度。
附图说明
为了更全面地理解实施例及其优势，现将结合附图所进行的以下描述作为参考，其中：
图1至图10是根据一些示例性实施例的金属氧化物半导体（MOS）器件在制造的中间步骤的截面图；
图11示例性的示出了根据一些实施例的MOS器件的外延区域中的锗百分比的示例性分布曲线；以及
图12示例性的示出了根据可选实施例的MOS器件的一些区域中的锗百分比和硅化物金属的量的示例性分布曲线。
具体实施方式
下面详细论述了各实施例的制造和使用。然而，应该理解，本发明提供了许多可以在各种具体环境中实现的可应用的概念。所论述的具体实施例是示例性的，并且不用于限制本发明的范围。
在过去的几十年里，半导体器件（例如，金属氧化物半导体（MOS）器件）的尺寸的缩小和固有特性使集成电路在每一单位功能（unit function）上的速度、性能、密度和成本不断提高。根据MOS器件的设计以及它的一个固有特性，调节位于MOS器件的源极和漏极之间的栅极下方的沟道区域的长度以改变与沟道区域相关的电阻，从而影响MOS器件的性能。更具体的，假设保持其他参数相对恒定，通过缩短沟道区域的长度减小了MOS器件的源极至漏极的电阻，当足够的电压施加到MOS器件的栅极时，这使得源极和漏极之间的电流增大。
为进一步增强MOS器件的性能，可以将应力引入MOS器件的沟道区域以提高载流子迁移率。总体而言，期望将张应力引入源极至漏极方向中的n型MOS（“NMOS”）器件的沟道区域中，并将压应力引入源极至漏极方向中的p型MOS（“PMOS”）器件的沟道区域中。
用于将压应力施加于PMOS器件的沟道区域的有效方法为在源极和漏极区域中生长SiGe压力源。这种方法通常包括以下步骤：在半导体衬底上形成栅极堆叠件，在栅极堆叠件的侧壁上形成间隔件，沿着栅极间隔件在硅衬底中形成凹槽，在凹槽中外延生长SiGe压力源，以及退火。由于SiGe的晶格常数大于硅的晶格常数，因此其将压应力施加于沟道区域，沟道区域位于源极SiGe压力源与漏极SiGe压力源之间。
本发明根据不同示例性实施例提供了用于形成具有压力源的金属氧化物半导体（MOS）器件的工艺。示出了形成MOS器件的中间步骤。讨论了实施例的变化例。在本发明的各个视图和示例性实施例中，相似的参考标号用于代表相似的原件。
图1示出了晶圆10的一部分的衬底20。衬底20可以是诸如硅衬底的块状半导体衬底，或可以具有诸如绝缘体上硅（SOI）结构的复合结构。可选地，衬底20也可以包括其他半导体材料（包括III族元素、IV族元素和/或V族元素），这些半导体材料可以包括硅锗、碳化硅和/或III-V族元素化合物半导体材料。
栅极堆叠件22形成在衬底20上方，并且包括栅极电介质24和栅电极26。栅极电介质24可以包括氧化硅和/或具有高k值（例如大于约7）的高k材料。栅电极26可以包括常用的导电材料，诸如掺杂的多晶硅、金属、金属硅化物、金属氮化物和它们的组合。栅极堆叠件22还可以包括硬掩模28，例如，硬掩模28可以包括氮化硅，但是也可以使用诸如碳化硅、氮氧化硅等的其他材料。
如图2所示，例如，通过将诸如硼和/或铟的p型杂质注入到衬底20内来形成轻掺杂的漏极/源极（LDD）区域30。栅极堆叠件22和硬掩模28用作注入掩模，从而使LDD区域30的内边缘基本上分别与栅极堆叠件22的边缘对准。可以使用介于约1keV和10keV范围内的能量实施LDD注入，且注入量介于约1×1013/cm2和约1×1016/cm2的范围内。然而，应该理解，说明书中所列举的数值仅为实例，且可以被改变为不同的数值。LDD注入可以是倾斜的或垂直的，倾斜角度介于约0度和约30度之间。此外，例如也可以通过将n型杂质（诸如砷、磷等）注入到衬底20内形成口袋区（pocket region）32。口袋注入（pocket implantation）可以是倾斜的，倾斜角度大于LDD注入的倾斜角度。在一些实施例中，口袋注入的倾斜角度介于约15度和约45度的范围内。为了清楚，未在随后的附图中示出口袋区域32。
参考图3，在栅极电介质24和栅电极26的侧壁上形成栅极间隔件34。在一些实施例中，每一个栅极间隔件34包括氧化硅层（未示出）及位于氧化硅层上方的氮化硅层，其中，氧化硅层的厚度可以介于约和约的范围内，且氮化硅层的厚度可以介于约和约的范围内。在可选实施例中，栅极间隔件34包括一个或多个层，每一个层都包括氧化硅、氮化硅、氮氧化硅和/或其他介电材料。可利用的形成方法包括等离子体增强化学汽相沉积（PECVD）、低压化学汽相沉积（LPCVD）、次常压化学汽相沉积（SACVD）和其他沉积方法。
又如图3所示，根据一些实施例，可以实施各向同性蚀刻以在衬底20中形成开口36。各向同性蚀刻可以为干蚀刻，其中，蚀刻气体可以选自CF4、Cl2、NF3、SF6和它们的组合。例如，开口36的深度D1可以介于例如约和约的范围内。在可选实施例中，跳过图3中的各向同性蚀刻步骤，而是实施图4中的步骤以形成如图4所示的开口36。
接下来，如图4所示，实施湿蚀刻以扩大开口36，例如，可以使用四甲基氢氧化铵（TMAH）、氢氧化钾（KOH）溶液等实施湿蚀刻。在一些示例性实施例中，TMAH溶液的浓度介于约1%和约30%的范围内。在湿蚀刻之后，可以在开口36中形成小平面，其中，小平面包括衬底20的(111)平面。例如，在一些示例性实施例中，在湿蚀刻之后，开口36的深度D2可以介于约和约的范围内。
可以使用例如HF基气体或SiCoNi基气体实施预清洁。预清洁可以去除由于开口36中的露出表面的自然氧化而形成的任何不期望的氧化硅。
图5示出了外延区域38的形成。在外延过程中，通过选择性外延生长（SEG），在开口36（图4）中外延生长诸如硅锗（SiGe）的半导体材料，从而形成外延区域38。因此，在本说明书中，外延区域38也称为SiGe区域38。工艺气体可以包括H2、N2、二氯硅烷（DCS）、SiH4和/或GeH4等。在外延过程中，晶圆10的温度可以介于约500℃和约900℃的范围内。在一些实施例中，加入蚀刻气体以促进在衬底20的露出表面上的选择性生长，但不在诸如栅极间隔件34和硬掩模28的电介质上选择性生长。工艺气体的压力可以介于约10托尔和约200托尔的范围内。
在外延过程中，可以在进行生长的同时掺杂期望的p型杂质。例如，当掺杂硼时，工艺气体中可以包括B2H6。在一些实施例中，外延区域38中p型杂质的杂质浓度介于约5E18/cm3和约5E21/cm3之间。在可选实施例中，在SiGe区域38的外延过程中，未原位掺杂p型杂质，或基本上不掺杂p型杂质（例如，p型杂质的浓度小于约1014/cm3）。在这些实施例中，通过注入，在随后的步骤中形成相应MOS器件的源极和漏极区域。例如，外延区域38可以具有介于约30%和约60%的范围内的第一锗原子百分比，但是也可以使用不同的锗百分比。在一些实施例中，外延区域38的顶面与衬底20和栅极电介质24之间的界面平齐或比该界面高。
参考图6，通过外延工艺在外延区域38上方生长外延层42。在一些实施例中，外延层42为SiGe层，其具有比外延区域38中的锗原子百分比高的锗原子百分比。在一些实施例中，外延层42具有介于约35%和约80%的范围内的第二锗原子百分比。由于具有高锗百分比，因此在本说明书中，外延层42也称为堆积SiGe区域。堆积SiGe区域42与SiGe区域38之间的锗原子百分比差值还可以大于约5%。该差值也可以介于约5%和约20%的范围内。除了调节的含硅气体与含锗气体的比率不同之外，用于形成堆积SiGe区域42的工艺条件可以与用于形成外延区域38的工艺条件相似。组合的外延区域38和42形成MOS器件的源极和漏极区域（且也形成源极或漏极压力源）的部分，MOS器件还包括作为它的栅极的一个栅极堆叠件22。堆积SiGe区域42具有较小的厚度T1，其可以小于约10nm。在一些实施例中，厚度T1可以介于约1nm和约10nm之间。
此外，在形成堆积SiGe区域42的外延过程中，可以随着外延的进程原位掺杂p型杂质。在可选实施例中，在SiGe层42的外延过程中，未原位掺杂p型杂质，或基本上不掺杂p型杂质（例如，p型杂质的浓度小于约1014/cm3）。
在一些实施例中，在每一个外延区域38和42中，锗百分比基本上是均匀的。在可选实施例中，外延区域38和42的一个或两个具有逐渐或连续改变的锗百分比。在相应的外延过程中，含锗前体（诸如GeH4）的流速可以逐渐或连续地改变。在这些实施例中，在锗百分比逐渐改变的层中，层下部的锗百分比比上层的锗百分比小。
如图7所示，在形成堆积SiGe区域42之后，通过外延，在堆积SiGe区域42上方形成覆盖层44。覆盖层44的组成（包括其中所含的元素和元素百分比）与堆积SiGe区域42的组成不同。覆盖层44可以是其中不含锗的纯硅层，或基本纯硅层，例如锗的含量小于2%或1%。因此，在本说明书中，覆盖层44可选地称为硅帽（silicon cap）。可以随着外延的进程使用p型杂质原位掺杂覆盖层44，或非原位掺杂。在SiGe区域38、42和/或覆盖层44的外延过程中，不掺杂非p型杂质或基本上非p型的杂质的实施例中，可以实施p型杂质注入以形成用于相应的MOS器件的源极和漏极区域。
图11示例性的示出了在图7中示出的区域中锗的分布曲线（线64），其中分布曲线表示沿图7中的箭头62的路径的锗百分比。也示出了相应的区域38、42和44以表示锗百分比和相应区域之间的对应关系。X轴表示从覆盖层44（图7）的顶面开始测量的深度。Y轴表示锗百分比。由于图11是示意图，因此未标记X轴和Y轴的数值。如图11所示，覆盖层44中锗百分比非常低，且可以等于0%。在堆积SiGe区域42中，锗百分比显著的高于覆盖层44和下面的外延区域38中的锗百分比。堆积SiGe区域42中的锗百分比比外延层38中的锗百分比高出差值ΔP，其可以介于约5%至约20%的范围内。
再次参考图7，外延区域42具有厚度T1，且覆盖层44具有大于厚度T1的厚度T2。厚度T2也可以显著的大于厚度T1，例如，比率T2/T1大于约2。在一些示例性实施例中，比率T2/T1可以介于约2和约10的范围内。保持厚度T2大于厚度T1有利于减小形成的源极和漏极硅化物区域中的形态退化。如果厚度T2等于或小于厚度T1，由于高锗百分比，由堆积区域42的硅化导致形成的硅化物区域的形态退化会很严重，并可能导致硅化物区域中的隔离，进而导致可靠性问题。
接下来，如图8所示，根据一些实施例，去除硬掩模28（如果存在），且形成替代栅极以代替栅极电介质24和栅电极26。在可选实施例中，未通过替代栅极代替栅极电介质24和栅电极26（图7）。在形成替代栅极的实施例中，栅极电介质24和栅电极26用作伪栅极。图8示出了包括替代栅极的示例性结构。形成工艺可以包括形成层间电介质（ILD）46，实施CMP以使ILD46的顶面与栅电极26或硬掩模28（如果存在）平齐，并去除伪栅极。然后可以形成栅极介电层和栅电极层以填充通过去除伪栅极留下的开口，然后实施CMP以去除栅极介电层和栅电极层的过量部分。保留的替代栅极包括栅极电介质24’和栅电极26’。例如，栅极电介质24’可以包括k值大于约7.0的高k介电材料，栅电极26’可以包括金属或金属合金。可以由诸如磷硅酸盐玻璃（PSG）、硼硅酸盐玻璃（BSG）、硼掺杂的磷硅酸盐玻璃（BPSG）等形成ILD46，接下来，形成接触开口48，从而露出下面的覆盖层44。
图9示出了源极/漏极硅化物区域52的形成。可以通过在器件（包括覆盖层44的露出表面）上方沉积硅化物金属（诸如钛、钴、镍、钨等）的薄层（未示出）形成硅化物区域52。然后加热晶圆10，无论金属在何处与硅接触，其均导致硅化反应的发生。作为反应的结果，在硅/SiGe和金属之间形成金属硅化物层。通过使用腐蚀金属但不腐蚀硅化物的蚀刻剂，选择性地去除未反应的金属。作为硅化的结果，源极/漏极硅化物区域52延伸进入并穿透覆盖层44。源极/漏极硅化物区域52可以与堆积SiGe区域42接触。在一些示例性实施例中，每一个堆积SiGe区域42的顶层被硅化，而每一个堆积SiGe区域42的底层保持未被硅化。因此，堆积SiGe区域42的底层具有与源极/漏极硅化物区域52的底面接触的顶面，以及与外延区域38的顶面接触的底面。此外，外延区域42的顶层可以与相应邻近的硅化物区域52平齐或位于其侧面上。
图10示出了源极/漏极接触插塞54的形成，其通过在开口48（图9）内填充诸如钨、铜、铝、钛、钴、硅、锗等的导电材料而形成，并实施CMP以使接触插塞54的顶面与ILD46的顶面平齐。因此完成了MOS晶体管60的形成。MOS晶体管60包括外延区域38、42和可能作为源极和漏极区域的覆盖层44的保留部分。
图12示例性的示出了在MOS器件60的源极和漏极区域及源极/漏极硅化物区域中的锗分布（线64）。线64表示沿图10中的箭头62的路径的锗百分比。在图12中也示出了图10中相应的区域38、42和44/52以表示锗百分比与相应区域之间的对应关系。X轴示出了从硅化物区域52（图10）的顶面开始测量的深度。Y轴表示示例性的锗百分比。由于图12是示意图，因此X轴和Y轴未标记数值。如图12所示，在硅化物区域52的顶部中的锗百分比（线64）非常低。
图12还示例性示出了在MOS器件60的源极和漏极区域中的金属分布曲线（线66），其中，线66反映出硅化物金属（例如，镍或钴）的相对量。在图12示出的实例中，通过硅化覆盖层44形成硅化物区域52，并基本上不对堆积SiGe区域42进行硅化。因此，在图12中，硅化物金属的量在堆积SiGe区域42内显著的减少。在可选实施例中，硅化物金属的量可以减少至堆积SiGe区域42的中间水平。
在本发明的实施例中，形成具有接触下面的堆积SiGe层的底面的源极/漏极硅化物区域，其中，堆积SiGe层具有高锗百分比。因此，与源极/漏极硅化物区域和具有较低锗百分比的SiGe层之间的势垒高度相比，减小了源极/漏极硅化物区域和相应下面的堆积SiGe层之间的肖特基势垒高度。从而减小了源极/漏极接触件的接触电阻。然而，增加的锗百分比导致形成的硅化物的形态退化，其可以导致硅化物区域中的金属隔离。然而，在本发明的实施例中，具有高锗百分比的堆积SiGe层的厚度非常小，并且由于堆积SiGe层的硅化形成的相应的硅化物非常薄，并且因此，形态退化对源极/漏极硅化物的质量具有最小化效应。
根据一些实施例，一种集成电路结构包括：位于半导体衬底上方的栅极堆叠件，以及延伸到半导体衬底内的开口，其中，开口邻近栅极堆叠件。第一硅锗区域设置在开口中，其中，第一硅锗区域具有第一锗百分比。第二硅锗区域覆盖第一硅锗区域，其中，第二硅锗区域具有大于第一锗百分比的第二锗百分比。金属硅化物区域位于第二硅锗区域上方且与第二硅锗区域接触。
根据其他实施例，一种集成电路结构包括：半导体衬底，以及位于半导体衬底上方的栅极堆叠件，其中，栅极堆叠件包括在MOS器件中。MOS器件的源极/漏极区域延伸到半导体衬底内。源极/漏极区域包括第一硅锗区域，其具有第一锗百分比。源极/漏极区域还包括位于第一硅锗区域上方的第二硅锗区域，其中，第二硅锗区域具有大于第一锗百分比的第二锗百分比。硅帽位于第二硅锗区域上方且与第二硅锗区域接触。金属硅化物区域穿透硅帽以与第二硅锗区域接触。
根据又一些其他实施例，一种方法包括：在半导体衬底上方形成栅极堆叠件，以及形成延伸到半导体衬底内的开口，其中开口位于栅极堆叠件的侧面上。实施第一外延以在开口中生长第一硅锗区域，其中，第一硅锗区域具有第一锗百分比。实施第二外延以在第一硅锗区域上方生长第二硅锗区域，其中，第二硅锗区域具有大于第一锗百分比的第二锗百分比。该方法还包括在第二硅锗区域上方形成基本上不含锗的硅帽，该硅帽与第二硅锗区域接触。
尽管已经详细地描述了实施例及其优势，但应该理解，可以在不背离所附权利要求限定的本发明主旨和范围的情况下，做各种不同的改变，替换和更改。而且，本申请的范围并不仅限于本说明书中描述的工艺、机器、制造、物质组成、工具、方法和步骤的特定实施例。作为本领域普通技术人员应理解，根据本发明，可以使用现有的或今后将开发的用于执行与本发明所述的相应实施例基本相同的功能或获得基本相同结果的工艺、机器、制造、物质组成、工具、方法或步骤。相应的，附加的权利要求旨在将这些工艺、机器、制造、物质组成、工具、方法或步骤包括在它们的范围。此外，每个权利要求构成一个独立的实施例，并且不同权利要求及实施例的组合均在本公开的范围之内。

Claims (15)

1.一种集成电路结构，包括：
半导体衬底；
栅极堆叠件，位于所述半导体衬底上方；
开口，延伸到所述半导体衬底内，其中，所述开口邻近所述栅极堆叠件；
第一硅锗区域，位于所述开口中，所述第一硅锗区域具有第一锗百分比；
第二硅锗区域，位于所述第一硅锗区域上方，所述第二硅锗区域具有大于所述第一锗百分比的第二锗百分比；以及
金属硅化物区域，位于所述第二硅锗区域上方且与所述第二硅锗区域接触；
不含锗的硅帽，位于所述第二硅锗区域上方，所述第二硅锗区域具有第一厚度，并且所述硅帽具有大于所述第一厚度的第二厚度；
其中，所述第二硅锗区域包括位于所述金属硅化物区域的侧面并与所述金属硅化物区域平齐的上部。
2.根据权利要求1所述的集成电路结构，其中，所述金属硅化物区域穿透所述硅帽。
3.根据权利要求1所述的集成电路结构，其中，所述第二硅锗区域包括下部，其中，所述下部的顶面与所述金属硅化物区域的底面接触，并且所述下部的底面与所述第一硅锗区域的顶面接触。
4.根据权利要求1所述的集成电路结构，其中，在所述第一硅锗区域和所述第二硅锗区域之间的界面处，锗百分比骤然改变。
5.根据权利要求1所述的集成电路结构，其中，所述第二锗百分比比所述第一锗百分比高出5％。
6.一种集成电路结构，包括：
半导体衬底；
栅极堆叠件，位于所述半导体衬底上方，所述栅极堆叠件包括在金属氧化物半导体(MOS)器件中；
所述金属氧化物半导体器件的源极/漏极区域，延伸到所述半导体衬底内，所述源极/漏极区域包括：
第一硅锗区域，其中，所述第一硅锗区域具有第一锗百分比；和
第二硅锗区域，位于所述第一硅锗区域上方，所述第二硅锗区域具有大于所述第一锗百分比的第二锗百分比；
硅帽，位于所述第二硅锗区域上方且与所述第二硅锗区域接触；以及
金属硅化物区域，穿透所述硅帽以与所述第二硅锗区域接触；
其中，所述第二硅锗区域包括位于所述金属硅化物区域的侧面并与所述金属硅化物区域平齐的部分，所述硅帽的厚度大于所述第二硅锗区域的厚度。
7.根据权利要求6所述的集成电路结构，其中，所述第二锗百分比比所述第一锗百分比高出5％。
8.根据权利要求6所述的集成电路结构，其中，所述第二硅锗区域包括：位于所述第一硅锗区域和所述金属硅化物区域之间并与所述第一硅锗区域和所述金属硅化物区域接触的一部分。
9.根据权利要求8所述的集成电路结构，其中，所述第二硅锗区域的所述一部分位于所述金属硅化物区域的下方并覆盖所述第一硅锗区域。
10.根据权利要求6所述的集成电路结构，其中，所述第一硅锗区域与所述第二硅锗区域之间的界面比所述半导体衬底与所述栅极堆叠件之间的界面高。
11.根据权利要求6所述的集成电路结构，其中，所述第二硅锗区域具有小于10nm的厚度。
12.一种形成集成电路结构的方法，包括：
在半导体衬底上方形成栅极堆叠件；
形成延伸到所述半导体衬底内的开口，其中，所述开口位于所述栅极堆叠件的侧边；
实施第一外延以在所述开口中生长第一硅锗区域，其中，所述第一硅锗区域具有第一锗百分比；
实施第二外延以在所述第一硅锗区域上方生长第二硅锗区域，其中，所述第二硅锗区域具有大于所述第一锗百分比的第二锗百分比；以及
在所述第二硅锗区域上方形成不含锗的硅帽，所述硅帽与所述第二硅锗区域接触；
在形成所述硅帽之后，实施硅化操作来硅化所述硅帽，其中，由所述硅化操作形成的金属硅化物与所述第二硅锗区域的剩余部分接触；
其中，所述第二硅锗区域包括位于所述金属硅化物的侧面并与所述金属硅化物平齐的部分，所述第二硅锗区域的厚度小于所述硅帽的厚度。
13.根据权利要求12所述的方法，其中，在所述硅化操作之后，所述第二硅锗区域的底层保持未被硅化。
14.根据权利要求12所述的方法，其中，在所述硅帽内不引入锗。
15.根据权利要求12所述的方法，还包括：
在形成所述硅帽之后，在所述栅极堆叠件和所述硅帽上方形成层间电介质(ILD)；
在所述层间电介质中形成接触开口，所述硅帽暴露于所述接触开口；
在形成所述接触开口之后，在所述硅帽上实施硅化；以及
使用导电材料填充所述接触开口。
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