CN104425566B - 具有凹陷顶面的源极/漏极应力源 - Google Patents
具有凹陷顶面的源极/漏极应力源 Download PDFInfo
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- CN104425566B CN104425566B CN201410315566.3A CN201410315566A CN104425566B CN 104425566 B CN104425566 B CN 104425566B CN 201410315566 A CN201410315566 A CN 201410315566A CN 104425566 B CN104425566 B CN 104425566B
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- 229910000577 Silicon-germanium Inorganic materials 0.000 claims abstract description 72
- 239000000758 substrate Substances 0.000 claims abstract description 62
- 239000004065 semiconductor Substances 0.000 claims abstract description 56
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical group [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 claims abstract description 53
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 26
- 229910052710 silicon Inorganic materials 0.000 claims description 26
- 239000010703 silicon Substances 0.000 claims description 26
- 229910044991 metal oxide Inorganic materials 0.000 claims description 8
- 150000004706 metal oxides Chemical class 0.000 claims description 8
- 238000000034 method Methods 0.000 abstract description 22
- 239000010410 layer Substances 0.000 description 16
- 239000011241 protective layer Substances 0.000 description 14
- 229910052732 germanium Inorganic materials 0.000 description 13
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 13
- 239000002184 metal Substances 0.000 description 10
- 239000007789 gas Substances 0.000 description 9
- 229910052751 metal Inorganic materials 0.000 description 9
- 229910021332 silicide Inorganic materials 0.000 description 9
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 8
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 7
- 239000012535 impurity Substances 0.000 description 7
- 230000015572 biosynthetic process Effects 0.000 description 6
- 238000002347 injection Methods 0.000 description 6
- 239000007924 injection Substances 0.000 description 6
- 238000001039 wet etching Methods 0.000 description 6
- 239000013078 crystal Substances 0.000 description 5
- 125000006850 spacer group Chemical group 0.000 description 5
- 229910052581 Si3N4 Inorganic materials 0.000 description 4
- 238000005530 etching Methods 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 4
- 230000026267 regulation of growth Effects 0.000 description 4
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 4
- 230000006835 compression Effects 0.000 description 3
- 238000007906 compression Methods 0.000 description 3
- MROCJMGDEKINLD-UHFFFAOYSA-N dichlorosilane Chemical compound Cl[SiH2]Cl MROCJMGDEKINLD-UHFFFAOYSA-N 0.000 description 3
- 239000003989 dielectric material Substances 0.000 description 3
- 229910001092 metal group alloy Inorganic materials 0.000 description 3
- 239000000203 mixture Substances 0.000 description 3
- 229910052814 silicon oxide Inorganic materials 0.000 description 3
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 2
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 2
- 239000005388 borosilicate glass Substances 0.000 description 2
- 239000010941 cobalt Substances 0.000 description 2
- 229910017052 cobalt Inorganic materials 0.000 description 2
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 description 2
- 239000004020 conductor Substances 0.000 description 2
- 229910052986 germanium hydride Inorganic materials 0.000 description 2
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 239000005360 phosphosilicate glass Substances 0.000 description 2
- 239000000377 silicon dioxide Substances 0.000 description 2
- 239000000243 solution Substances 0.000 description 2
- 239000010936 titanium Substances 0.000 description 2
- 229910052719 titanium Inorganic materials 0.000 description 2
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 2
- 229910052721 tungsten Inorganic materials 0.000 description 2
- 239000010937 tungsten Substances 0.000 description 2
- QGZKDVFQNNGYKY-UHFFFAOYSA-O Ammonium Chemical compound [NH4+] QGZKDVFQNNGYKY-UHFFFAOYSA-O 0.000 description 1
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- KWYUFKZDYYNOTN-UHFFFAOYSA-M Potassium hydroxide Chemical compound [OH-].[K+] KWYUFKZDYYNOTN-UHFFFAOYSA-M 0.000 description 1
- VRZFDJOWKAFVOO-UHFFFAOYSA-N [O-][Si]([O-])([O-])O.[B+3].P Chemical compound [O-][Si]([O-])([O-])O.[B+3].P VRZFDJOWKAFVOO-UHFFFAOYSA-N 0.000 description 1
- 239000004411 aluminium Substances 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- 238000001505 atmospheric-pressure chemical vapour deposition Methods 0.000 description 1
- 238000006701 autoxidation reaction Methods 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 239000002131 composite material Substances 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000002474 experimental method Methods 0.000 description 1
- QUZPNFFHZPRKJD-UHFFFAOYSA-N germane Chemical compound [GeH4] QUZPNFFHZPRKJD-UHFFFAOYSA-N 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 238000011065 in-situ storage Methods 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 238000004904 shortening Methods 0.000 description 1
- -1 silicide metals Chemical class 0.000 description 1
- 229910010271 silicon carbide Inorganic materials 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 125000003698 tetramethyl group Chemical group [H]C([H])([H])* 0.000 description 1
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- H01L29/7848—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate the means being located in the source/drain region, e.g. SiGe source and drain
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Abstract
本发明提供了一种具有源极/漏极应力源的集成电路结构,包括:栅叠件,位于半导体衬底上方;以及硅锗区,延伸至半导体衬底内并且与栅叠件邻近。硅锗区具有顶面,并且顶面的中心部分从顶面的边缘部分凹陷从而形成凹槽。边缘部分位于中心部分的相对两侧。本发明还提供了一种形成该具有源极/漏极应力源的集成电路结构的方法。
Description
技术领域
本发明总体涉及半导体领域,更具体地,涉及金属氧化物半导体(MOS)器件。
背景技术
金属氧化物半导体(MOS)器件是集成电路的关键部件。MOS器件的性能影响了MOS器件所在的整个集成电路的性能。因此,已经研究了用于改进MOS器件的性能的方法。
发明内容
根据本发明的一个方面,提供了一种集成电路结构,包括:半导体衬底;第一栅叠件,位于半导体衬底上方;以及第一硅锗区,延伸至半导体衬底内并且与第一栅叠件邻近,其中,第一硅锗区包括第一顶面,并且第一顶面的中心部分从第一顶面的边缘部分凹陷从而形成凹槽,并且边缘部分位于中心部分的相对两侧。
优选地,该集成电路结构还包括:位于第一硅锗区上方的硅盖,其中,硅盖与第一顶面物理接触。
优选地,该集成电路结构还包括:第二栅叠件,位于半导体衬底上方;第二开口,延伸至半导体衬底内,其中,第二开口与第二栅叠件邻近;以及第二硅锗区,位于第二开口中,其中,第二硅锗区包括第二顶面,并且第二顶面不具有凹陷的中心部分。
优选地,第一硅锗区位于第一栅叠件和第三栅叠件之间,而在第一栅叠件和第三栅叠件之间没有附加的栅叠件,第二硅锗区位于第二栅叠件和第四栅叠件之间,而在第二栅叠件和第四栅叠件之间没有附加的栅叠件,并且第一栅叠件和第三栅叠件之间的第一距离大于第二栅叠件和第四栅叠件之间的第二距离。
优选地,第一硅锗区位于具有第一宽度的第一有源区中,而第二硅锗区位于具有小于第一宽度的第二宽度的第二有源区中,并且在平行于第一栅叠件和第二栅叠件的纵向的方向上分别测得第一宽度和第二宽度。
优选地,凹槽的深度介于约1nm至约10nm的范围内。
优选地,第一顶面的中心部分包括两个向相反方向倾斜的基本平坦的部分。
根据本发明的另一方面,提供了一种集成电路结构,包括:半导体衬底;第一金属氧化物半导体(MOS)晶体管,包括:第一栅叠件,位于半导体衬底的上方;和第一硅锗区,延伸至半导体衬底内并且与第一栅叠件邻近,其中,第一硅锗区包括第一顶面,并且第一顶面的中心部分从第一顶面的边缘部分凹陷从而形成凹槽,并且边缘部分位于中心部分的相对两侧;以及第二MOS晶体管,包括:第二栅叠件,位于半导体衬底的上方;和第二硅锗区,延伸至半导体衬底内并且与第二栅叠件邻近,其中,第二硅锗区包括第二顶面,并且第二顶面不具有凹陷的中心部分。
优选地,该集成电路结构还包括:第一硅盖,位于第一顶面的上方并且与第一顶面接触;以及第二硅盖,位于第二顶面的上方并且与第二顶面接触,其中,第一硅盖和第二硅盖的锗百分比相同且小于第一硅锗区和第二硅锗区的锗百分比。
优选地,凹槽的纵向平行于第一栅叠件的纵向。
优选地,凹槽的深度介于约1nm至约10nm的范围内。
优选地,第一顶面的中心部分包括基本平直而且倾斜的部分,并且基本平直而且倾斜的部分与半导体衬底的主顶面形成介于约5度至约45度的范围内的角度。
优选地,第一顶面高于第一栅叠件和半导体衬底的主顶面之间的界面,并且第二顶面高于第二栅叠件和半导体衬底的主顶面之间的界面。
优选地,第一硅锗区位于第一栅叠件和第三栅叠件之间,而在第一栅叠件和第三栅叠件之间没有附加的栅叠件,第二硅锗区位于第二栅叠件和第四栅叠件之间,而在第二栅叠件和第四栅叠件之间没有附加的栅叠件,并且第一栅叠件和第三栅叠件之间的第一距离大于100nm,而第二栅叠件和第四栅叠件之间的第二距离小于100nm。
优选地,第一硅锗区位于具有大于300nm的第一宽度的第一有源区中,而第二硅锗区位于具有小于300nm的第二宽度的第二有源区中,并且在平行于第一栅叠件和第二栅叠件的纵向的方向上分别测得第一宽度和第二宽度。
根据本发明的又一方面,提供了一种方法,包括:在半导体衬底上方形成第一栅叠件;形成延伸至半导体衬底内的第一开口,其中,第一开口位于第一栅叠件的一侧上并且与第一栅叠件邻近;以及实施外延以在第一开口中生长第一硅锗区,其中,第一硅锗区包括第一顶面,并且第一顶面的中心部分凹陷而低于第一顶面的边缘部分从而形成凹槽,并且边缘部分位于中心部分的相对两侧。
优选地,该方法还包括:在半导体衬底上方形成第二栅叠件;
形成延伸至半导体衬底内的第二开口,其中,第二开口位于第二栅叠件的一侧;以及在第二开口中生长第二硅锗区,其中,第二硅锗区包括第二顶面,并且第二顶面在相应的中心区处没有凹槽。
优选地,同时实施生长第一硅锗区和生长第二硅锗区。
优选地,该方法还包括:形成硅盖,硅盖位于第一硅锗区的第一顶面的上方并且与第一硅锗区的第一顶面接触,其中,硅盖的锗百分比小于第一硅锗区的锗百分比。
优选地,该方法还包括:在形成硅盖之后,实施硅化以使硅盖硅化。
附图说明
为了更充分地理解实施例及其优势,现结合附图参考以下描述,其中:
图1A至图9是根据一些示例性实施例的在制造金属氧化物半导体(MOS)器件的中间阶段的截面图和顶视图。
具体实施方式
下面详细地讨论了本发明的实施例的制造和使用。然而,应该理解,实施例提供了许多能够在各种具体环境中实现的可应用的概念。所讨论的具体实施例是说明性的,但不限制本发明的范围。
在过去的几十年间,半导体器件(例如,金属氧化物半导体(MOS)器件)的尺寸和内在部件的减小已经使集成电路的速度、性能、集成度和每单位功能的成本得到不断的改进。根据MOS器件的设计以及MOS器件的内在特性之一,调节MOS器件中位于栅极下面并且介于源极和漏极之间的沟道区的长度改变了与沟道区相关联的电阻,从而影响MOS器件的性能。更具体地,假设其他参数保持相对不变,缩短沟道区的长度减小了MOS器件的源极-漏极电阻,这样在当向MOS器件的栅极施加足够的电压时,可增大源极和漏极之间的电流。
为了进一步增强MOS器件的性能,可将应力引入到MOS器件的沟道区中以提高载流子迁移率。通常,期望在n型MOS(“NMOS”)器件的沟道区中诱发源极至漏极方向上的拉伸应力,而在p型MOS(“PMOS”)器件的沟道区中诱发源极至漏极方向上的压缩应力。
一种用于向PMOS器件的沟道区施加压缩应力的有效方法是在源极和漏极区中生长SiGe应力源(stressor)。这种方法通常包括以下步骤:在半导体衬底上形成栅叠件;在栅叠件的侧壁上形成间隔件;沿着栅极间隔件在硅衬底中形成凹槽;在凹槽中外延生长SiGe应力源;以及退火。由于SiGe的晶格常数大于硅的晶格常数,所以在退火之后SiGe膨胀,并且向位于源极SiGe应力源和漏极SiGe应力源之间的沟道区施加压缩应力。
根据各个示例性实施例,提供了一种用于形成具有应力源的金属氧化物半导体(MOS)器件的工艺。示出了形成MOS器件的中间阶段。讨论了实施例的变化。贯穿各个视图和说明性实施例,类似的参考符号用于表示类似的元件。
图1A示出了衬底20,衬底20是晶圆10的一部分。衬底20包括器件区100中的第一部分和器件区200中的第二部分。衬底20可以是诸如硅衬底的块体半导体衬底,或者可以具有诸如绝缘体上硅(SOI)结构的复合结构。衬底20的材料可以包括硅、碳化硅等。彼此平行的栅叠件122形成在器件区100中并且位于衬底20的上方。彼此平行的栅叠件222形成在器件区200中并且位于衬底20的上方。在一些实施例中,相邻的栅叠件122彼此均匀地间隔开距离S1,而相邻的栅叠件222彼此均匀地间隔开距离S2,但是相邻的栅叠件122(或222)之间的距离也可以是不均匀的。栅叠件122和222的每个均包括栅介质24和栅电极26。栅介质24可以包括氧化硅或具有高k值(例如,高于约7)的高k材料。栅电极26可以包括掺杂的多晶硅、金属或金属合金以及金属硅化物等。硬掩模28可以形成在栅叠件122和222的上方,其中,硬掩模28可以包括例如氮化硅。
图1B示出了图1A中的结构的顶视图,其中,由图1B中包含线A-A的平面截取获得图1A中的器件区100的截面图,而由图1B中的包含线B-B的平面截取获得图1A中的器件区200的截面图。器件区100和200具有不同的栅叠件的图案密度和/或不同尺寸。例如,区域100中相邻的栅叠件122之间的距离S1可以大于距离S2,而距离S2是区域200中相邻的栅叠件222之间的距离。在一些实施例中,距离S1大于100nm,而距离S2小于100nm。例如,比率S1/S2可以大于约2。
而且,器件区100和200中相应的有源区123和223由浅沟槽隔离(STI)区25限定。栅叠件122横跨有源区123,而栅叠件222横跨有源区223。在一些实施例中,有源区123具有宽度W1,宽度W1大于有源区223的宽度W2。在一些示例性实施例中,宽度W1大于300nm,而宽度W2小于300nm。此外,例如,比率W1/W2可以大于约2。
参照图2,例如,通过将p型杂质注入衬底20内形成轻掺杂漏极/源极(LDD)区130和230。栅叠件122和222以及上面的硬掩模28用作注入掩模,从而使得LDD区130和230的内边缘分别与栅叠件122和222的边缘基本对准。可使用介于约1keV至约10keV范围内的能量和介于约1×1013/cm2至约1×1016/cm2范围内的剂量来实施LDD注入。然而,应该理解,在整篇描述中所引用的数值仅是实例,并且可以改变为不同的数值。可以一定的倾斜角来实施LDD注入,例如,倾斜角小于约30度。可选地,垂直地实施LDD注入。此外,例如,可以通过将诸如砷、磷等的n型杂质注入衬底20内来形成口袋区(未示出)。可使用介于约20keV至约80keV范围内的能量和介于约1×1012/cm2至约1×1014/cm2范围内的剂量来实施口袋注入。口袋注入可以是倾斜的。在一些实施例中,口袋注入的倾斜角介于约15度至约45度的范围内。
参照图3,栅极间隔件34形成在栅叠件122和222的侧壁上。在一些实施例中,每个栅极间隔件34均包括氧化硅层(未示出)和位于氧化硅层上方的氮化硅层,其中,氧化硅层的厚度可以介于约至约的范围内,而氮化硅层的厚度可以介于约至约的范围内。在可选实施例中,栅极间隔件34包括一个或多个层,每个层都包括氧化硅、氮化硅、氮氧化硅和/或其他介电材料。可行的形成方法包括等离子体增强化学汽相沉积(PECVD)、低压化学汽相沉积(LPCVD)、次大气压化学汽相沉积(SACVD)和其他沉积方法。
还如图3所示,实施各向同性蚀刻以分别在器件区100和200中形成开口136和236。各向同性蚀刻可以是干蚀刻,其中,蚀刻气体可以选自CF4、Cl2、NF3、SF6以及它们的组合。例如,开口136和开口236的深度D1可以介于约至约的范围内。
接着,如图4所示,可以实施湿蚀刻以扩大开口136和236,例如,可使用四甲基氢氧化铵(TMAH)、氢氧化钾(KOH)溶液等来实施湿蚀刻。在一些示例性实施例中,TMAH溶液的浓度介于约1%至约30%的范围内。在湿蚀刻期间,TMAH的温度可以介于约20℃至约100℃的范围内。在湿蚀刻之后,在开口136和236中形成小晶面,这些小晶面可包括衬底20的(111)晶面。在一些示例性实施例中,在湿蚀刻之后,开口136和开口236的深度D2例如可以介于约20nm至约60nm的范围内。
在湿蚀刻之后,例如可使用HF基的气体或SiCoNi基的气体来实施预清洗。预清洗可以去除作为开口136和236中露出表面的自然氧化的结果而形成的氧化硅。还可以实施高温烘烤,但是也可以跳过烘烤。可以在存在或不存在HCl气体的情况下实施高温烘烤。烘烤温度可以介于约700℃至约900℃的范围内。烘烤气体的压力可以介于约10Torr至约200Torr的范围内。例如,烘烤持续时间可以介于约30秒至约240秒的范围内。高温烘烤还可以去除衬底20的露出表面上的原生氧化物,其中,露出表面位于开口136和236中。
如图5A所示,通过选择性外延生长(SEG)在开口136和236中外延生长诸如硅锗(SiGe)的半导体材料,从而在凹槽136和236(图4)中分别形成外延区138和238。外延区138和238用作相应的MOS器件的源极和漏极区以及源/漏极应力源。在整篇描述中,外延区138和238也被称为SiGe区。外延区138的顶面138A可以高于栅叠件122与下面半导体衬底20相应的顶面之间的界面,而外延区238的顶面238A可以高于栅叠件222与下面半导体衬底20相应的顶面之间的界面。用于外延生长的工艺气体可以包括H2、N2、二氯硅烷(DCS)、SiH4以及GeH4等。外延生长的温度可以介于约600℃至约900℃的范围内。工艺气体的压力可以介于约10Torr至约200Torr的范围内。在一些实施例中,也可以添加诸如HCl的蚀刻气体以促进在衬底20的露出表面上而不在诸如栅极间隔件34的介电质上选择性的生长。实施外延直到完全填充凹槽136和236(图4)。在外延生长期间,可在进行生长的同时,掺杂期望的杂质。例如,当要掺杂硼时,在工艺气体中可以包括B2H6。例如,外延区138和238可以具有介于约15%至约60%范围内的锗百分比,但是也可以使用不同的锗百分比。
由于不同的距离S1/S2(图1B)和/或不同的宽度W1/W2,外延区138的顶面轮廓可以不同于外延区238的顶面轮廓。在一些实施例中,外延区138的顶面138A具有两个基本平坦的边缘部分138A1。外延区138的顶面138A也包括位于两个部分138A1之间的中心部分138A2,其中,部分138A2凹陷,低于部分138A1,从而形成凹槽139。在一些实施例中,部分138A2包括两个向相反方向倾斜的基本平直(平坦)的部分,其中,在图5A的截面图中,基本平直的部分形成直线29。部分138A2与平行于衬底20的(主)顶面的水平面形成角度α。在一些实施例中,角度α介于约5度至约45度的范围内。顶面部分138A2的最低点低于顶面部分138A1,两者的高度差为ΔT1,高度差ΔT1可以介于约1nm至约10nm的范围内。高度差ΔT1还可以是中心部分138A2的最低点与顶面138A的最高点之间的高度差。
虽然图5A示出了中心部分138A2的底部是两条直线29的接合点,但是在可选实施例中,顶面部分138A2的最低部分是基本平坦的表面。由凹陷的顶面部分138A2形成的凹槽139的纵向平行于栅叠件122的纵向,其中,图5B中示意性地示出了凹槽139,而图5B是图5A中结构的顶视图。
外延区238的顶面238A在中心处不包括凹槽,并且中心部分可以是基本平坦的。通过调节外延生长的工艺条件,可以产生并且扩大外延区138的顶面轮廓与外延区238的顶面轮廓之间的差异。例如,增大HCl的流速可以产生并且增大高度差ΔT1(图5A)。在一些示例性实施例中,HCl的流速介于约50sccm至约250sccm的范围内。DCS的流速可以介于约50sccm至约350sccm的范围内,而GeH4的流速可以介于约100sccm至约950sccm的范围内。然而,应该认识到,外延区138和238的顶面轮廓也受到图案的尺寸(诸如图1B中的S1、S2、W1和W2)、图案的图案密度以及其他因素的影响。因此,可以通过实验发现用于产生外延区138和238的期望的顶面轮廓的最佳工艺条件。
如图6所示,在形成SiGe区138和238之后,通过外延在外延区138和238上方分别形成保护层144和244。保护层144和244具有很低的锗百分比,该锗百分比低于外延区138和238的锗百分比。在一些实施例中,保护层144和244的锗百分比小于约15%。保护层144和244可以是其中不包括锗的纯硅层,或者是具有例如小于2%或小于1%的锗的基本纯硅层。因此,在整篇描述中,保护层144和244可选地被称为硅盖。保护层144和244可以在进行外延的同时而原位掺杂有p型杂质,或者不原位掺杂保护层144和244。在SiGe层138和238以及保护层144和244的外延生长期间未掺杂p型杂质或基本未掺杂p型杂质的实施例中,可以实施p型杂质注入以形成相应MOS器件的源极区和漏极区。
接着,参照图7,根据一些实施例,如果存在硬掩模28,则将其去除(参照图6),并且形成替代栅极以替代栅介质24和栅电极26(图6)。在可选实施例中,栅介质24和栅电极26不被替代栅极所代替。在形成替代栅极的实施例中,栅介质24和栅电极26(图6)用作去除的伪栅极。图7示出了包括替代栅极的示例性结构。形成工艺可以包括形成层间介电质(ILD)46、实施CMP以使ILD46的顶面与栅电极26(或硬掩模28,如果存在)的顶面平齐,以及去除伪栅极。然后,可以形成栅介电层和栅电极层以填充由于去除伪栅极而留下的开口,随后进行CMP以去除栅介电层和栅电极层的多余部分。剩余的替代栅极包括栅介质24’和栅电极26’。例如,栅介质24’可以包括k值大于约7.0的高k介电材料,而栅电极26’可以包括金属或金属合金。ILD46可以由介电材料(诸如,磷硅酸盐玻璃(PSG)、硼硅酸盐玻璃(BSG)以及硼磷硅酸盐玻璃(BPSG)等)形成。接着,形成接触开口48,从而露出下面的保护层144和244。
图8示出了源/漏极中硅化物区52的形成。可以通过沉积诸如钛、钴、镍、钨等的金属(有时称为硅化物金属)薄层(未示出)来形成硅化物区52。金属位于包括保护层144和244的露出表面的各器件上方。然后,实施退火以使金属与硅/锗反应。在反应之后,在硅和金属之间形成金属硅化物层。通过使用侵蚀金属但不侵蚀硅化物的蚀刻剂来选择性地去除未反应的金属。作为硅化的结果,源/漏极中硅化物区52延伸至保护层144和244,并且可以延伸至SiGe区138和/或238。可选地,保护层144和244的顶部受到硅化,而保护层144和244的底部没有受到硅化。在硅化之后,保护层144和244的一些剩余部分可能保持未受硅化,其中,保护层144和244的剩余部分与源/漏极中硅化物区52平齐并且位于源/漏极中硅化物区52的相对侧上。
图9示出了源/漏极中接触插塞54的形成,其中,通过在开口48内填充导电材料(诸如,钨、铜、铝、钛、钴以及硅等),并且实施CMP以使接触塞54的顶面与ILD46的顶面平齐,从而形成源极/漏极中的接触插塞54。因此,完成了器件区100和200中的MOS晶体管160和260的形成。
本发明的实施例具有一些优势特征。通常,由于小外延区和沟道设置较近,所以大外延区(应力源)比小外延区向相邻的MOS器件的沟道区施加较小的应力。另一方面,由于SiGe具有显著的小晶面,所以由大外延区施加的应力不能通过生长更多的SiGe而增大,并且过多的SiGe的形成将不合需要地减小接触插塞的着陆区(landing area)。在本发明的实施例中,通过形成大外延区的凹陷(中凹)的顶面轮廓,减少了SiGe应力源的小晶面,因此可以生长更多的SiGe以向相应的沟道区施加更大的应力。提高了器件性能,诸如,相应的MOS器件的导通电流。
根据一些实施例,一种集成电路结构包括位于半导体衬底上方的栅叠件以及延伸至半导体衬底内并且与栅叠件邻近的硅锗区。硅锗区具有顶面,同时顶面的中心部分从顶面的边缘部分凹陷从而形成凹槽。边缘部分位于中心部分的相对两侧。
根据其他实施例,一种集成电路结构包括半导体衬底以及第一和第二MOS晶体管。第一MOS晶体管包括位于半导体衬底上方的第一栅叠件以及延伸至半导体衬底内并且与第一栅叠件邻近的第一硅锗区。第一硅锗区具有第一顶面,同时第一顶面的中心部分从第一顶面的边缘部分凹陷从而形成凹槽。边缘部分位于中心部分的相对两侧。第二MOS晶体管包括位于半导体衬底上方的第二栅叠件以及延伸至半导体衬底内并且与第二栅叠件邻近的第二硅锗区。第二硅锗区具有第二顶面,其中,第二顶面不具有凹陷的中心部分。
根据又一些实施例,一种方法包括:在半导体衬底上方形成栅叠件;形成延伸至半导体衬底内的开口,其中,开口位于栅叠件的一侧上并且与栅叠件邻近。实施外延以在开口中生长硅锗区,其中,硅锗区具有顶面,并且顶面的中心部分凹陷而低于顶面的边缘部分从而形成凹槽。边缘部分位于中心部分的相对两侧。
尽管已经详细地描述了本实施例及其优势,但是应该理解,在不背离由所附权利要求限定的本发明的精神和范围的情况下,在此可以做出各种改变、替代和变化。此外,本申请的范围不旨在限于说明书中描述的工艺、机器、制造、物质组成、工具、方法和步骤的特定实施例。作为本领域的技术人员容易理解,通过本发明,现有的或今后开发的用于实施与在此所描述的相应实施例基本相同的功能或者实现基本相同的结构的工艺、机器、制造、物质组成、工具、方法或步骤可以被使用。因此,所附权利要求应该将这些工艺、机器、制造、物质组成、工具、方法或步骤包括在的它们范围内。此外,每个权利要求都构成单独的实施例,并且各个权利要求和实施例的结合都在本发明的范围内。
Claims (11)
1.一种集成电路结构,包括:
半导体衬底;
第一栅叠件,位于所述半导体衬底上方;以及
第一硅锗区,延伸至所述半导体衬底内并且与所述第一栅叠件邻近,其中,所述第一硅锗区包括第一顶面,并且所述第一顶面的中心部分从所述第一顶面的边缘部分凹陷从而形成凹槽,并且所述边缘部分位于所述中心部分的相对两侧,
不含锗的硅盖,位于所述第一硅锗区上方并且与所述第一顶面直接接触;
第二栅叠件,位于所述半导体衬底上方;
第二开口,延伸至所述半导体衬底内,其中,所述第二开口与所述第二栅叠件邻近;以及
第二硅锗区,位于所述第二开口中,其中,所述第二硅锗区包括第二顶面,并且所述第二顶面不具有凹陷的中心部分;
其中,所述第一顶面高于所述第一栅叠件与所述半导体衬底的顶面之间的界面;
所述第一硅锗区位于所述第一栅叠件和第三栅叠件之间,而在所述第一栅叠件和所述第三栅叠件之间没有附加的栅叠件,所述第二硅锗区位于所述第二栅叠件和第四栅叠件之间,而在所述第二栅叠件和所述第四栅叠件之间没有附加的栅叠件,并且所述第一栅叠件和所述第三栅叠件之间的第一距离大于所述第二栅叠件和所述第四栅叠件之间的第二距离。
2.根据权利要求1所述的集成电路结构,其中,所述第一硅锗区位于具有第一宽度的第一有源区中,而所述第二硅锗区位于具有小于所述第一宽度的第二宽度的第二有源区中,并且在平行于所述第一栅叠件和所述第二栅叠件的纵向的方向上分别测得所述第一宽度和所述第二宽度。
3.根据权利要求1所述的集成电路结构,其中,所述凹槽的深度介于1nm至10nm的范围内。
4.根据权利要求1所述的集成电路结构,其中,所述第一顶面的中心部分包括两个向相反方向倾斜的平坦的部分。
5.一种集成电路结构,包括:
半导体衬底;
第一金属氧化物半导体(MOS)晶体管,包括:
第一栅叠件,位于所述半导体衬底的上方;和
第一硅锗区,延伸至所述半导体衬底内并且与所述第一栅叠件邻近,其中,所述第一硅锗区包括第一顶面,并且所述第一顶面的中心部分从所述第一顶面的边缘部分凹陷从而形成凹槽,并且所述边缘部分位于所述中心部分的相对两侧,其中,所述第一顶面高于所述第一栅叠件与所述半导体衬底的顶面之间的界面;
不含锗的第一硅盖,位于所述第一硅锗区上方并且与所述第一顶面直接接触;
以及
第二金属氧化物半导体晶体管,包括:
第二栅叠件,位于所述半导体衬底的上方;和
第二硅锗区,延伸至所述半导体衬底内并且与所述第二栅叠件邻近,其中,所述第二硅锗区包括第二顶面,并且所述第二顶面不具有凹陷的中心部分;
其中,所述第一硅锗区位于所述第一栅叠件和第三栅叠件之间,而在所述第一栅叠件和所述第三栅叠件之间没有附加的栅叠件,所述第二硅锗区位于所述第二栅叠件和第四栅叠件之间,而在所述第二栅叠件和所述第四栅叠件之间没有附加的栅叠件,并且所述第一栅叠件和所述第三栅叠件之间的第一距离大于100nm,而所述第二栅叠件和所述第四栅叠件之间的第二距离小于100nm。
6.根据权利要求5所述的集成电路结构,还包括:
第二硅盖,位于所述第二顶面的上方并且与所述第二顶面接触。
7.根据权利要求5所述的集成电路结构,其中,所述凹槽的纵向平行于所述第一栅叠件的纵向。
8.根据权利要求5所述的集成电路结构,其中,所述凹槽的深度介于1nm至10nm的范围内。
9.根据权利要求5所述的集成电路结构,其中,所述第一顶面的中心部分包括平直而且倾斜的部分,并且所述平直而且倾斜的部分与所述半导体衬底的主顶面形成介于5度至45度的范围内的角度。
10.根据权利要求5所述的集成电路结构,其中,所述第一顶面高于所述第一栅叠件和所述半导体衬底的主顶面之间的界面,并且所述第二顶面高于所述第二栅叠件和所述半导体衬底的主顶面之间的界面。
11.根据权利要求5所述的集成电路结构,其中,所述第一硅锗区位于具有大于300nm的第一宽度的第一有源区中,而所述第二硅锗区位于具有小于300nm的第二宽度的第二有源区中,并且在平行于所述第一栅叠件和所述第二栅叠件的纵向的方向上分别测得所述第一宽度和所述第二宽度。
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