CN102208443B - 半导体元件与其形成方法 - Google Patents

半导体元件与其形成方法 Download PDF

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CN102208443B
CN102208443B CN201010260686XA CN201010260686A CN102208443B CN 102208443 B CN102208443 B CN 102208443B CN 201010260686X A CN201010260686X A CN 201010260686XA CN 201010260686 A CN201010260686 A CN 201010260686A CN 102208443 B CN102208443 B CN 102208443B
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CN102208443A (zh
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吴志强
许俊豪
张志豪
谢文兴
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

本发明提供一种具有区域性应力单元的半导体元件如PMOS元件或NMOS元件及其形成方法。首先，在栅极的相反两侧形成凹陷。之后沿着凹陷底部形成应力诱导区，再形成应力区于应力诱导区上。若应力诱导区的晶格结构大于应力区，将使沟道区具有拉伸应力并适用于NMOS元件。若应力诱导区的晶格结构小于应力区，将使沟道区具有压缩应力并适用于PMOS元件。本发明的实施例可适用于多种基板与半导体元件如平面晶体管及FinFET。

Description

半导体元件与其形成方法
技术领域
本发明涉及半导体元件，且更特别涉及具有埋入式应力单元的半导体元件及其制造方法。
背景技术
在过去几十年间，金属氧化物半导体晶体管(MOSFET)尺寸如栅极长度与栅极氧化物厚度持续缩小，以改善集成电路的速度、效能、密度、以及每单位功能的成本。为了进一步增加晶体管效能，MOSFET工艺在部分半导体基板中形成应力沟道区。应力沟道区可增加载子迁移率，这将增加n型沟道元件如NMOSFET与p型沟道元件如PMOSFET的效能。一般来说，NMOSFET的n型沟道区在源极至漏极的方向应具有拉伸应力，以提高电子迁移率；PMOSFET的p型沟道区在源极至漏极的方向应具有压缩应力，以提高空穴迁移率。目前已有多种方法是关于施加应力至晶体管的沟道区中。
一种方法是形成凹陷于基板的源极/漏极区中，以施加应力至沟道区中。举例来说，可在硅基板的源极/漏极区的凹槽上，外延成晶格结构大于硅的应力诱导层如SiGe层，以施加压缩应力至PMOS元件的沟道区。相同地，可在硅基板的源极/漏极区的凹槽上，外延成晶格结构小于硅的应力诱导层如SiC层，以施加拉伸应力至NMOS元件的沟道区。
然而上述其他材料如SiGe与SiC可能导致其他元件问题。举例来说，位于源极/漏极区的非硅材料将面临金属硅化与超窄结的挑战。PMOS采用的Ge层或SiGe层具有高比例锗会导致快速硼扩散，而NMOS采用的SiC层会导致掺质惰化的问题。上述问题将限制密集尺寸元件无法完整利用应力单元。
发明内容
本发明提供一种半导体元件，包括基板；栅极位于基板上；以及源极/漏极区位于栅极相反的两侧，源极/漏极区包括应力诱导区，与位于应力引发区上的应力区，应力区是半导体材料，且应力诱导区的材料不同于基板与应力区。
本发明也提供一种半导体元件的形成方法，包括提供基板；形成栅极于基板上；形成凹陷于栅极相反两侧的基板中；沿着凹陷底部形成应力诱导区；以及形成应力区于应力诱导区上。
本发明还提供一种半导体元件的形成方法，包括提供基板，其中基板具有鳍状物延伸自基板，以及绝缘区位于该鳍状物的相反两侧；使至少部分鳍状物凹陷至绝缘区上表面的下方；沿着凹陷后的鳍状物的上表面形成应力诱导区；以及形成应力鳍状物于应力诱导区上。
应力诱导区与其上的层状结构之间的晶格结构差异，将导致其上的层状结构具有压缩应力或拉伸应力。当上述结构应用于晶体管的源极/漏极区时，应力诱导区可产生沟道区中所需的应力，且源极/漏极区的上表面仍为硅层。
附图说明
图1是本发明一实施例中，具有较大晶格结构的应力诱导区的剖视图；
图2是本发明一实施例中，平衡后的应力诱导区的剖视图；
图3是本发明一实施例中，具有较小晶格结构的应力诱导区的剖视图；
图4-图8是本发明一实施例中，具有应力沟道区的半导体元件的形成方法；以及
图9-图13是本发明一实施例中，具有应力沟道区的半导体元件的形成方法。
其中，附图标记说明如下：
102、602、1102～应力诱导区；104、702～应力区；106～沟道区；108～源极区；110～漏极区；400、900～基板；402～绝缘区；404、904～栅极结构；410～栅极绝缘层；412～栅极；414～侧壁间隔物；502～凹陷；802、1302～金属硅化区；804、1304～源极/漏极区；902～鳍状物；1202～应力鳍状物。
具体实施方式
下述说明将讨论如何制造与使用本发明的多种实施例。然而必需理解的是，这些实施例提供多种可实施的发明内容，这些内容可应用于多种特定的方式。以下特定的实施例仅用以说明制造与使用的特定方式，并非用以局限本发明。
如同下列的详细说明，本发明实施例采用的埋入式应力诱导区的晶格结构与位于其上的层状结构的晶格结构不同。应力诱导区与其上的层状结构之间的晶格结构差异，将导致其上的层状结构具有压缩应力或拉伸应力。当上述结构应用于晶体管的源极/漏极区时，应力诱导区可产生沟道区中所需的应力，且源极/漏极区的上表面仍为硅层。
举例来说，图1是本发明一实例中应力诱导区102与其上的应力区104，且应力诱导区102的晶格结构大于应力区104。如此一来，将施加拉伸应力至源极区108与漏极区110之间的沟道区106。在此实例中，应力诱导区102位于源极区108与漏极区110中，而应力区104形成于应力诱导区102上。应力诱导区102的晶格结构大于应力区104的晶格结构。上述晶格结构差异将导致应力区104的晶格结构延伸，以匹配应力诱导区102的晶格结构，这会造成应力区104具有拉伸应力。源极区108与漏极区110的拉伸应力会使沟道区106具有拉伸应力，如图1的箭头所示。
应该理解的是图1显示的实例并未达到平衡状态，这是为了更清楚的表达应力方向。图2显示的实例是图1的实例中晶格结构达到平衡以后的结果。在此实例中，Ge是作为晶格结构大于Si的材料。
图1的实例中，沟道区106具有拉伸应力且适用于NMOS元件。图3则显示另一实例，其沟道区106具有压缩应力且较适用于PMOS元件。在此实例中，应力诱导区102的晶格结构小于其上的应力区104的晶格结构。上述晶格结构差异将导致应力区104的晶格结构压缩，以匹配应力诱导区102的晶格结构，这会造成应力区104具有压缩应力。源极区108与漏极区110的压缩应力会使沟道区106具有压缩应力，如图3的箭头所示。应该理解的是图3显示的实例并未达到平衡状态，这是为了更清楚的表达应力方向。
图4-图8显示一实施例中，具有应力沟道区的半导体元件的形成方法。首先如图4所示，一实施例的部分基板400具有绝缘区402形成其中。基板400可包含掺杂或未掺杂的基体硅，或绝缘层上半导体(SOI)的有源层。一般来说，SOI包括半导体材料层如硅形成于绝缘层上。举例来说，绝缘层可为氧化埋层(BOX)或氧化硅层。绝缘层提供于基板如硅基板或玻璃基板上。除了上述基板，也可采用其他基板如多层基板或组成渐变式基板。此外，基板可为锗基板、硅锗合金基板、III-V族基板、或类似基板。
绝缘区402如填充绝缘物的浅沟槽绝缘，可形成于基板400的部分区域中，以物理绝缘所需的MOSFET区。绝缘区402可包含化学气相沉积(CVD)法形成的氧化硅。此外，绝缘区402可采用其他绝缘结构如热生长的场氧化区(FOX)与类似结构，也可采用其他绝缘材料。
图4还显示一实施例的栅极结构404，其包含栅极绝缘层410、栅极412、与侧壁间隔物414形成并图案化于基板400上。栅极绝缘层410可由高介电常数材料如氧化硅、氮氧化硅、氮化硅、氧化物、含氮氧化物、上述的组合、或类似物所形成。在一实施例中，栅极绝缘层410的相对介电常数大于约4。其他实施例中，栅极绝缘层可采用氧化铝、氧化镧、氧化铪、氧化锆、氮氧化铪、或上述的组合。
在一实施例中，栅极绝缘层410包含氧化层，其形成方法可为任何氧化法如湿式或干式热氧化法，其氧化环境含有氧气、水气、一氧化氮、或上述的组合。除了氧化法外，也可采用CVD形成栅极绝缘层410，其前驱物为四乙氧硅烷(TEOS)与氧气。栅极绝缘层410的厚度介于约10至50
Figure BSA00000240724200042
之间。
栅极412可包含导电材料如金属(例如钽、钛、钼、钨、铂、铝、铪、或钌)、金属硅化物(例如钛硅化物、钴硅化物、镍硅化物、或钽硅化物)、金属氮化物(例如氮化钛或氮化钽)、掺杂多晶硅、其他导电材料、或上述的组合。在一实例中，先沉积非晶硅后进行再结晶，以形成多晶硅。在一实施例中，栅极为多晶硅，栅极412可由低压CVD(LPCVD)沉积掺杂或非掺杂的多晶硅所形成，其厚度介于约200
Figure BSA00000240724200043
至约1000
Figure BSA00000240724200044
之间。
图案化栅极绝缘层410与栅极412的方法可为公知的光刻技术。一般来说，光刻工艺先沉积光致抗蚀剂材料，接着以光掩模曝光后显影。在图案化光致抗蚀剂层后，接着蚀刻不需要的部分栅极介电材料与部分栅极材料，以形成栅极绝缘层410与栅极412如图4所示。在一实施例中，栅极材料为多晶硅而栅极介电材料为氧化物，蚀刻工艺可为干式或湿式的各向同性或各向异性蚀刻工艺。
图4也显示侧壁间隔物414。如本领域常见手段，形成侧壁间隔物414的方法为先形成栅极侧壁间隔物层(未图示)。在一实施例中，栅极侧壁间隔物层包括氧化物层上的氮化物层。在其他实施例中，栅极侧壁间隔物层可包含单层或两层以上的结构，每一层状材料包含氧化物、氮化硅、氮氧化硅(SiON)、及/或其他介电材料。栅极侧壁间隔物层的形成方法可为一般常见技术如等离子体增强式CVD(PECVD)、低压CVD(LPCVD)、次常压CVD(SACVD)、或类似技术。接着图案化栅极侧壁间隔物层以形成侧壁间隔物414，其中图案化步骤可为湿式或干式蚀刻。在移除水平部分的栅极侧壁间隔物层后，保留的的栅极侧壁间隔物层即为侧壁间隔物414。
如图5所示，在一实施例的栅极412相反两侧的基板中形成凹陷502。在后续的完整说明中，将沿着凹陷502底部外延生长应力诱导区，接着在应力诱导区上外延生长应力区。在一实施例中，凹陷502的深度需深到足以生长够厚的应力诱导区，使应力诱导区表面不受应力诱导区与其下的基板之间的晶格不匹配影响。如此一来，应力诱导区表面将不会产生错位。在这种结构中，应力诱导区将具有应力松弛的表面，其晶格结构将实质上类似于本身固有的晶格结构。
举例来说，一实施例的凹陷502可由蚀刻法形成，如HBr/O2、HBr/Cl2/O2、或SF6/Cl2等离子体，其凹陷深度介于约400
Figure BSA00000240724200051
至约3000
Figure BSA00000240724200052
之间。本领域普通技术人员应了解上述尺寸仅用以举例，而这些尺寸将随着不同的集成电路技术尺寸而改变。
如图6所示，一实施例的应力诱导区602沿着凹陷502的底部形成。在一实施例中，应力诱导区602的厚度需足以使应力诱导区602表面不受应力诱导区602与其下的基板400之间的晶格不匹配影响，使应力诱导区602表面不会产生错位且具有固有的应力松弛的晶格结构。如此一来，应力诱导区602的厚度将取决于其材料组成。
如图7所示，一实施例的应力区702形成于应力诱导区602上。应力区702的材料选择不同于应力诱导区602，因此两者之间为晶格不匹配。本领域普通技术人员应了解应力区702与应力诱导区602的材料选择取决于元件种类。举例来说，NMOS元件的应力诱导区602可由SiGe形成，而应力区702可由晶格结构小于SiGe的硅形成。SiGe组成的应力诱导区602的晶格结构将使应力区702具有拉伸应力，这会使沟道区也随之具有拉伸应力并提高沟道区的电子迁移率。SiGe组成的应力诱导区602可由选择性外延生长(SEG)工艺，如采用含硅气体如SiH4与含锗气体GeH4作为前驱物的CVD所形成。硅组成的应力区702可由SEG工艺，如采用含硅气体如SiH4作为前驱物的CVD所形成。
在形成PMOS元件的另一实施例之中，应力诱导区602可为碳化硅，而应力区702可为晶格结构大于碳化硅的硅。碳化硅组成的应力诱导区602的晶格结构将使应力区702具有压缩应力，这会使沟道区也随之具有压缩应力并提高沟道区的空穴迁移率。碳化硅组成的应力诱导区602可由选择性外延生长(SEG)工艺，如采用含硅气体如SiH4与含碳气体C2H4或C2H6作为前驱物的CVD所形成。硅组成的应力区702可由SEG工艺，如采用含硅气体如SiH4作为前驱物的CVD所形成。
值得注意的是，基板400、应力诱导区602、与应力区702可采用其他材料。举例来说，基板及/或应力区可由SiGe、Ge、III-V族材料、或类似物所组成。在此实例中，NMOS元件的应力诱导区602可由SiGe、Ge、或类似物等晶格结构大于应力区的材料所组成，而PMOS元件的应力诱导区602可由Si、SiC、或类似物等晶格结构小于应力区的材料所组成。
必需注意的是，虽然图示中应力区702的上表面接触栅极绝缘层410的下表面，但应力区702的上表面可高于或低于栅极绝缘层410的下表面。另一个必需注意的是，部分或全部的应力诱导区602与应力区702可由临场掺杂掺质于其中。举例来说，NMOS元件中的应力诱导区602及/或应力区702可掺杂n型掺质如砷或磷，而PMOS元件中的应力诱导区602及/或应力区702可掺杂p型掺质如硼。此外，应力诱导区602的掺杂型态可与应力区702的掺杂型态相反，以帮助控制短沟道效应并改善绝缘性。
本领域普通技术人员应理解，上述讨论的实施例可采用不同的材料于源极/漏极区中以产生应力。在这些实施例中，应力诱导区602埋置于应力区702下方。应力区702的材料可不同于实际上诱导出应力的材料(如应力诱导区602的材料)。如此一来，应用于源极/漏极区的材料如硅将可采用完整发展的技术于应力区702上，如金属硅化工艺与形成硅接点的技术。上述结构在不需改变后续工艺的前提下，即可借由改变应力诱导区602的材料与特性，以调整沟道区的应力。
如图8所示，是一实施例的源极/漏极区804与金属硅化区802。必需注意的是，一般以椭圆形表示源极/漏极区。本领域普通技术人员应了解源极/漏极的掺杂可为任何合适形状，包括采用间隔物、衬垫、及/或牺牲衬垫/间隔物。举例来说，在形成凹陷于基板400前可先形成淡掺杂漏极(LDD)，并在形成应力区的同时或之后形成重掺杂区，且重掺杂区的形成利用侧壁间隔物414及/或不同的侧壁间隔物及/或额外侧壁间隔物。在另一实施例中，LDD与重掺杂区可形成于凹陷的工艺之后，其形成方法可为临场注入、临场扩散、或其他类似方法。
如本领域普通技术人员所熟知，金属硅化区802的形成方法是毯覆性地沉积金属薄层如镍、铂、钴、或上述的组合。接着加热金属薄层使硅与接触的金属反应，形成金属硅化物层。接着以只攻击金属但不攻击金属硅化物的蚀刻剂选择性地移除未反应的金属。
必需注意的是，凹陷502的位置可不同于图示的位置。举例来说，凹陷502可偏离栅极412一段距离、对准栅极、或延伸至栅极412的下方。
之后可进行本领域已知的工艺以完成元件。举例来说，可形成一或多层的介电层与金属层，如适用于特定应用的后端工艺(BEOL)技术。
图9-图13显示一实施例中，FinFET元件中具有应力沟道区的半导体元件的形成方法。如图9所示，一实施例的部分基板900具有鳍状物902自一绝缘区904延伸至另一绝缘区904。基板900可包含掺杂或未掺杂的基体硅，或绝缘层上半导体(SOI)的有源层。此外，基板可为锗基板、硅锗合金基板、III-V族基板、或类似基板。除了上述基板，也可采用其他基板如多层基板或组成渐变式基板。绝缘区可为氧化硅层。
如图10所示，以各向异性蚀刻工艺使鳍状物920凹陷。在后续的完整说明中，部分鳍状物将被移除并置换为应力诱导区，接着在应力诱导区上再形成鳍状物。在一实施例中，鳍状物被蚀刻凹陷的深度需深到足以生长够厚的应力诱导区，使应力诱导区表面不受应力诱导区与其下的基板之间的晶格不匹配影响。如此一来，应力诱导区表面将不会产生错位。在这种结构中，应力诱导区将具有应力松弛的表面，其晶格结构将实质上类似于本身固有的晶格结构。举例来说，鳍状物902被蚀刻凹陷的试剂可采用HBr/O2、HBr/Cl2/O2、或SF6/Cl2等离子体，其蚀刻凹陷的深度介于约400
Figure BSA00000240724200071
至约3000
Figure BSA00000240724200072
之间。
如图11所示，形成应力诱导区1102。应力诱导区1102的形成材料及方法与前述图6的应力诱导区602的形成方法类似。
接着如图12所示，形成应力鳍状物1202于应力诱导区1102上。应力鳍状物1202的形成方法及方法与前述图7的应力区702类似。然而此实施例中，应力鳍状物1202的高度高于绝缘区904。在一实施例中，应力鳍状物1202的高度比绝缘区904高出约200
Figure BSA00000240724200081
至1000
Figure BSA00000240724200082
之间。
必需注意的是，形成应力鳍状物1202的工艺中可采用其他层。举例来说，可采用掩模层形成于绝缘区904上，以帮助固定应力鳍状物1202的形状，避免或减少应力鳍状物1202在工艺中延伸至绝缘区904的上表面。
如图13所示，是一实施例的源极/漏极区1304与金属硅化区1302。必需注意的是，一般以椭圆形表示源极/漏极区1304。本领域普通技术人员应了解源极/漏极的掺杂可为任何合适形状，包括采用间隔物、衬垫、及/或牺牲衬垫/间隔物。
必需注意的是，图9-图13中的实施例的鳍状物的源极/漏极区将被移除并置换为下层的应力诱导区1102。然而在其他实施例中，鳍状物的沟道区被蚀刻凹陷，但不蚀刻凹陷源极/漏极区。在此实施例中，图9-图12的工艺用以形成鳍状物的沟道区。此外，在又一实施例中，所有的鳍状物(沟道区与源极/漏极区)均被蚀刻凹陷。在此实施例中，图9-图13的工艺用以形成鳍状物的源极/漏极区，而图9-图12的工艺用以形成鳍状物的沟道区。可以理解的是，此实施例的鳍状物的沟道区被置换，且掺杂型态可依需要而有所不同。
之后可进行本领域已知的工艺以完成元件。其他工艺可包含形成栅极绝缘层、栅极、源极/漏极区、一或多层的介电层与金属层、后端工艺(BEOL)、或类似工艺。
虽然本发明已以多个优选实施例公开如上，然其并非用以限定本发明，任何本领域普通技术人员，在不脱离本发明的精神和范围内，当可作任意的更动与润饰，因此本发明的保护范围当视随附的权利要求所界定的保护范围为准。

Claims (5)

1.一种半导体元件，包括：
一基板；
一栅极位于该基板上；以及
一源极/漏极区位于该栅极相反的两侧，该源极/漏极区包括一应力诱导区，与位于该应力诱导区上的一应力区，该应力区是一半导体材料，且该应力诱导区的材料不同于该基板与该应力区；
其中，该半导体元件是一NMOS元件时，该应力诱导区的晶格结构大于该应力区的晶格结构；
其中，该半导体元件是一PMOS元件时，该应力诱导区的晶格结构小于该应力区的晶格结构；以及，
其中，该应力诱导区与该应力区的电性相反。
2.如权利要求1所述的半导体元件，其中该半导体元件是FinFET或平面晶体管。
3.一种半导体元件的形成方法，包括：
提供一基板；
形成一栅极于该基板上；
形成一凹陷于该栅极相反两侧的基板中；
沿着该凹陷底部形成一应力诱导区；以及
形成一应力区于该应力诱导区上；
其中，该半导体元件是一NMOS元件时，该应力诱导区的晶格结构大于该应力区的晶格结构；
其中，该半导体元件是一PMOS元件时，该应力诱导区的晶格结构小于该应力区的晶格结构；以及，
其中，该应力诱导区与该应力区的电性相反。
4.如权利要求3所述的半导体元件的形成方法，其中该应力诱导区的表面不受应力诱导区与该基板之间的晶格不匹配影响，且该应力诱导区的表面不具有错位。
5.一种半导体元件的形成方法，包括：
提供一基板，其中该基板具有一鳍状物延伸自一基板，以及绝缘区位于该鳍状物的相反两侧；
使至少部分该鳍状物凹陷至该绝缘区上表面的下方；
沿着该凹陷后的鳍状物的上表面形成一应力诱导区；以及
形成一应力鳍状物于该应力诱导区上；
其中，该半导体元件是一NMOS元件时，该应力诱导区的晶格结构大于该应力鳍状物的晶格结构；
其中，该半导体元件是一PMOS元件时，该应力诱导区的晶格结构小于该应力鳍状物的晶格结构；以及，
其中，该应力诱导区与该应力鳍状物分别以相反电性的掺质掺杂。
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TWI481032B (zh) 2015-04-11
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US9219152B2 (en) 2015-12-22
US8338259B2 (en) 2012-12-25

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