TWI481032B - 半導體元件與其形成方法 - Google Patents

半導體元件與其形成方法 Download PDF

Info

Publication number
TWI481032B
TWI481032B TW099130826A TW99130826A TWI481032B TW I481032 B TWI481032 B TW I481032B TW 099130826 A TW099130826 A TW 099130826A TW 99130826 A TW99130826 A TW 99130826A TW I481032 B TWI481032 B TW I481032B
Authority
TW
Taiwan
Prior art keywords
stress
region
substrate
gate
lattice structure
Prior art date
Application number
TW099130826A
Other languages
English (en)
Other versions
TW201133847A (en
Inventor
Zhiqiang Wu
Jeffrey Junhao Xu
Chih Hao Chang
Wen Hsing Hsieh
Original Assignee
Taiwan Semiconductor Mfg Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Taiwan Semiconductor Mfg Co Ltd filed Critical Taiwan Semiconductor Mfg Co Ltd
Publication of TW201133847A publication Critical patent/TW201133847A/zh
Application granted granted Critical
Publication of TWI481032B publication Critical patent/TWI481032B/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
    • H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1025—Channel region of field-effect devices
    • H01L29/1029—Channel region of field-effect devices of field-effect transistors
    • H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
    • H01L29/1054—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with a variation of the composition, e.g. channel with strained layer for increasing the mobility
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System
    • H01L29/161—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System including two or more of the elements provided for in group H01L29/16, e.g. alloys
    • H01L29/165—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System including two or more of the elements provided for in group H01L29/16, e.g. alloys in different semiconductor regions, e.g. heterojunctions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66636—Lateral single gate silicon transistors with source or drain recessed by etching or first recessed by etching and then refilled
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
    • H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
    • H01L29/7848—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate the means being located in the source/drain region, e.g. SiGe source and drain
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/665—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using self aligned silicidation, i.e. salicide

Description

半導體元件與其形成方法
本發明係關於半導體元件，且更特別關於具有埋入式應力單元的半導體元件及其製造方法。
在過去幾十年間，金氧半電晶體(MOSFET)尺寸如閘極長度與閘極氧化物厚度持續縮小，以改善積體電路的速度、效能、密度、以及每單位功能的成本。為了進一步增加電晶體效能，MOSFET製程在部份半導體基板中形成應力通道區。應力通道區可增加載子遷移率，這將增加n型通道元件如NMOSFET與p型通道元件如PMOSFET的效能。一般來說，NMOSFET的n型通道區在源極至汲極的方向應具有拉伸應力，以提高電子遷移率；PMOSFET的p型通道區在源極至汲極的方向應具有壓縮應力，以提高電洞遷移率。目前已有多種方法係關於施加應力至電晶體的通道區中。
一種方法係形成凹陷於基板的源極/汲極區中，以施加應力至通道區中。舉例來說，可在矽基板之源極/汲極區的凹槽上，磊晶成晶格結構大於矽的應力誘導層如SiGe層，以施加壓縮應力至PMOS元件的通道區。相同地，可在矽基板之源極/汲極區的凹槽上，磊晶成晶格結構小於矽的應力誘導層如SiC層，以施加拉伸應力至NMOS元件的通道區。
然而上述其他材料如SiGe與SiC可能導致其他元件問題。舉例來說，位於源極/汲極區的非矽材料將面臨金屬矽化與超窄接面的挑戰。PMOS採用的Ge層或SiGe層具有高比例鍺會導致快速硼擴散，而NMOS採用的SiC層會導致掺質惰化的問題。上述問題將限制密集尺寸元件無法完整利用應力單元。
本發明提供一種半導體元件，包括基板；閘極位於基板上；以及源極/汲極區位於閘極相反的兩側，源極/汲極區包括應力誘導區，與位於應力引發區上的應力區，應力區係半導體材料，且應力誘導區之材料不同於基板與應力區。
本發明亦提供一種半導體元件的形成方法，包括提供基板；形成閘極於基板上；形成凹陷於閘極相反兩側的基板中；沿著凹陷底部形成應力誘導區；以及形成應力區於應力誘導區上。
本發明更提供一種一種半導體元件的形成方法，包括提供基板，其中基板具有鰭狀物延伸自基板，以及絕緣區位於該鰭狀物的相反兩側；使至少部份鰭狀物凹陷至絕緣區上表面的下方；沿著凹陷後的鰭狀物之上表面形成應力誘導區；以及形成應力鰭狀物於應力誘導區上。
下述說明將討論如何製造與使用本發明的多種實施例。然而必需理解的是，這些實施例提供多種可實施的發明內容，該些內容可應用於多種特定的方式。以下特定的實施例僅用以說明製造與使用的特定方式，並非用以侷限本發明。
如同下列的詳細說明，本發明實施例採用的埋入式應力誘導區之晶格結構與位於其上的層狀結構之晶格結構不同。應力誘導區與其上的層狀結構之間的晶格結構差異，將導致其上的層狀結構具有壓縮應力或拉伸應力。當上述結構應用於電晶體之源極/汲極區時，應力誘導區可產生通道區中所需的應力，且源極/汲極區的上表面仍為矽層。
舉例來說，第1圖係本發明一實例中應力誘導區102與其上的應力區104，且應力誘導區102之晶格結構大於應力區104。如此一來，將施加拉伸應力至源極區108與汲極區110之間的通道區106。在此實例中，應力誘導區102係位於源極區108與汲極區110中，而應力區104係形成於應力誘導區102上。應力誘導區102之晶格結構大於應力區104之晶格結構。上述晶格結構差異將導致應力區104之晶格結構延伸，以匹配應力誘導區102之晶格結構，這會造成應力區104具有拉伸應力。源極區108與汲極區110的拉伸應力會使通道區106具有拉伸應力，如第1圖之箭頭所示。
應該理解的是第1圖顯示的實例並未達到平衡狀態，這是為了更清楚的表達應力方向。第2圖顯示的實例係第1圖的實例中晶格結構達到平衡以後的結果。在此實例中，Ge係作為晶格結構大於Si的材料。
第1圖之實例中，通道區106具有拉伸應力且適用於NMOS元件。第3圖則顯示另一實例，其通道區106具有壓縮應力且較適用於PMOS元件。在此實例中，應力誘導區102的晶格結構小於其上之應力區104的晶格結構。上述晶格結構差異將導致應力區104之晶格結構壓縮，以匹配應力誘導區102之晶格結構，這會造成應力區104具有壓縮應力。源極區108與汲極區110的壓縮應力會使通道區106具有壓縮應力，如第3圖所示。應該理解的是第3圖顯示的實例並未達到平衡狀態，這是為了更清楚的表達應力方向。
第4-8圖顯示一實施例中，具有應力通道區之半導體元件的形成方法。首先如第4圖所示，一實施例的部份基板400具有絕緣區402形成其中。基板400可包含掺雜或未掺雜之基體矽，或絕緣層上半導體(SOI)的主動層。一般來說，SOI包括半導體材料層如矽形成於絕緣層上。舉例來說，絕緣層可為氧化埋層(BOX)或氧化矽層。絕緣層係提供於基板如矽基板或玻璃基板上。除了上述基板，亦可採用其他基板如多層基板或組成漸變式基板。此外，基板可為鍺基板、矽鍺合金基板、III-V族基板、或類似基板。
絕緣區402如填充絕緣物的淺溝槽絕緣，可形成於基板400的部份區域中，以物理絕緣所需的MOSFET區。絕緣區402可包含化學氣相沉積(CVD)法形成的氧化矽。此外，絕緣區402可採用其他絕緣結構如熱成長的場氧化區(FOX)與類似結構，亦可採用其他絕緣材料。
第4圖更顯示一實施例之閘極結構404，其包含閘極絕緣層410、閘極412、與側壁間隔物414形成並圖案化於基板400上。閘極絕緣層410可由高介電常數材料如氧化矽、氮氧化矽、氮化矽、氧化物、含氮氧化物、上述之組合、或類似物所形成。在一實施例中，閘極絕緣層410之相對介電常數大於約4。其他實施例中，閘極絕緣層可採用氧化鋁、氧化鑭、氧化鉿、氧化鋯、氮氧化鉿、或上述之組合。
在一實施例中，閘極絕緣層410包含氧化層，其形成方法可為任何氧化法如濕式或乾式熱氧化法，其氧化環境含有氧氣、水氣、一氧化氮、或上述之組合。除了氧化法外，亦可採用CVD形成閘極絕緣層410，其前驅物為四乙氧矽烷(TEOS)與氧氣。閘極絕緣層410之厚度介於約10至50之間。
閘極412可包含導電材料如金屬(例如鉭、鈦、鉬、鎢、鉑、鋁、鉿、或釕)、金屬矽化物(例如鈦矽化物、鈷矽化物、鎳矽化物、或鉭矽化物)、金屬氮化物(例如氮化鈦或氮化鉭)、掺雜多晶矽、其他導電材料、或上述之組合。在一實例中，先沉積非晶矽後進行再結晶，以形成多晶矽。在一實施例中，閘極為多晶矽，閘極412可由低壓CVD(LPCVD)沉積掺雜或非掺雜之多晶矽所形成，其厚度介於約200至約1000之間。
圖案化閘極絕緣層410與閘極412的方法可為習知的微影技術。一般來說，微影製程先沉積光阻材料，接著以光罩曝光後顯影。在圖案化光阻層後，接著蝕刻不需要的部份閘極介電材料與部份閘極材料，以形成閘極絕緣層410與閘極412如第4圖所示。在一實施例中，閘極材料為多晶矽而閘極介電材料為氧化物，蝕刻製程可為乾式或濕式的等向或非等向蝕刻製程。
第4圖亦顯示側壁間隔物414。如本技藝常見手段，形成側壁間隔物414的方法為先形成閘極側壁間隔物層(未圖示)。在一實施例中，閘極側壁間隔物層包括氧化物層上的氮化物層。在其他實施例中，閘極側壁間隔物層可包含單層或兩層以上的結構，每一層狀材料包含氧化物、氮化矽、氮氧化矽(SiON)、及/或其他介電材料。閘極側壁間隔物層的形成方法可為一般常見技術如電漿增強式CVD(PECVD)、低壓CVD(LPCVD)、次常壓CVD(SACVD)、或類似技術。接著圖案化閘極側壁間隔物層以形成側壁間隔物414，其中圖案化步驟可為濕式或乾式蝕刻。在移除水平部份的閘極側壁間隔物層後，保留的的閘極側壁間隔物層即為側壁間隔物414。
如第5圖所示，在一實施例之閘極412相反兩側的基板中形成凹陷502。在後續的完整說明中，將沿著凹陷502底部磊晶成長應力誘導區，接著在應力誘導區上磊晶成長應力區。在一實施例中，凹陷502的深度需深到足以成長夠厚的應力誘導區，使應力誘導區表面不受應力誘導區與其下的基板之間的晶格不匹配影響。如此一來，應力誘導區表面將不會產生錯位。在這種結構中，應力誘導區將具有應力鬆弛的表面，其晶格結構將實質上類似於本身固有的晶格結構。
舉例來說，一實施例之凹陷502可由蝕刻法形成，如HBr/O2 、HBr/Cl2 /O2 、或SF6 /Cl2 電漿，其凹陷深度介於約400至約3000之間。本技藝人士應了解上述尺寸僅用以舉例，而該些尺寸將隨著不同的積體電路技術尺寸而改變。
如第6圖所示，一實施例之應力誘導區602係沿著凹陷502的底部形成。在一實施例中，應力誘導區602之厚度需足以使應力誘導區602表面不受應力誘導區602與其下的基板400之間的晶格不匹配影響，使應力誘導區602表面不會產生錯位且具有固有之應力鬆弛的晶格結構。如此一來，應力誘導區602的厚度將取決於其材料組成。
如第7圖所示，一實施例之應力區702係形成於應力誘導區602上。應力區702之材料選擇不同於應力誘導區602，因此兩者之間為晶格不匹配。本技藝人士應了解應力區702與應力誘導區602之材料選擇係取決於元件種類。舉例來說，NMOS元件之應力誘導區602可由SiGe形成，而應力區702可由晶格結構小於SiGe的矽形成。SiGe組成的應力誘導區602之晶格結構將使應力區702具有拉伸應力，這會使通道區亦隨之具有拉伸應力並提高通道區的電子遷移率。SiGe組成的應力誘導區602可由選擇性磊晶成長(SEG)製程，如採用含矽氣體如SiH4 與含鍺氣體GeH4 作為前驅物之CVD所形成。矽組成的應力區702可由SEG製程，如採用含矽氣體如SiH4 作為前驅物之CVD所形成。
在形成PMOS元件的另一實施例之中，應力誘導區602可為碳化矽，而應力區702可為晶格結構大於碳化矽的矽。碳化矽組成的應力誘導區602之晶格結構將使應力區702具有壓縮應力，這會使通道區亦隨之具有壓縮應力並提高通道區的電洞遷移率。碳化矽組成的應力誘導區602可由選擇性磊晶成長(SEG)製程，如採用含矽氣體如SiH4 與含碳氣體C2 H4 或C2 H6 作為前驅物之CVD所形成。矽組成的應力區702可由SEG製程，如採用含矽氣體如SiH4 作為前驅物之CVD所形成。
值得注意的是，基板400、應力誘導區602、與應力區702可採用其他材料。舉例來說，基板及/或應力區可由SiGe、Ge、III-V族材料、或類似物所組成。在此實例中，NMOS元件之應力誘導區602可由SiGe、Ge、或類似物等晶格結構大於應力區之材料所組成，而PMOS元件之應力誘導區602可由Si、SiC、或類似物等晶格結構小於應力區之材料所組成。
必需注意的是，雖然圖示中應力區702的上表面接觸閘極絕緣層410的下表面，但應力區702的上表面可高於或低於閘極絕緣層410之下表面。另一個必需注意的是，部份或全部的應力誘導區602與應力區702可由臨場掺雜掺質於其中。舉例來說，NMOS元件中的應力誘導區602及/或應力區702可掺雜n型掺質如砷或磷，而PMOS元件中的應力誘導區602及/或應力區702可掺雜p型掺質如硼。此外，應力誘導區602之掺雜型態可與應力區702之掺雜型態相反，以幫助控制短通道效應並改善絕緣性。
本技藝人士應理解，上述討論的實施例可採用不同的材料於源極/汲極區中以產生應力。在這些實施例中，應力誘導區602係埋置於應力區702下方。應力區702的材料可不同於實際上誘導出應力的材料(如應力誘導區602的材料)。如此一來，應用於源極/汲極區之材料如矽將可採用完整發展的技術於應力區702上，如金屬矽化製程與形成矽接點的技術。上述結構在不需改變後續製程的前提下，即可藉由改變應力誘導區602之材料與特性，以調整通道區的應力。
如第8圖所示，係一實施例之源極/汲極區804與金屬矽化區802。必需注意的是，一般以橢圓形表示源極/汲極區。本技藝人士應了解源極/汲極的掺雜可為任何合適形狀，包括採用間隔物、襯墊、及/或犧牲襯墊/間隔物。舉例來說，在形成凹陷於基板400前可先形成淡掺雜汲極(LDD)，並在形成應力區的同時或之後形成重掺雜區，且重掺雜區的形成利用側壁間隔物414及/或不同的側壁間隔物及/或額外側壁間隔物。在另一實施例中，LDD與重掺雜區可形成於凹陷的製程之後，其形成方法可為臨場佈植、臨場擴散、或其他類似方法。
如本技藝人士所熟知，金屬矽化區802的形成方法係毯覆性地沉積金屬薄層如鎳、鉑、鈷、或上述之組合。接著加熱金屬薄層使矽與接觸的金屬反應，形成金屬矽化物層。接著以只攻擊金屬但不攻擊金屬矽化物之蝕刻劑選擇性地移除未反應的金屬。
必需注意的是，凹陷502的位置可不同於圖示的位置。舉例來說，凹陷502可偏離閘極412一段距離、對準閘極、或延伸至閘極412的下方。
之後可進行本技藝已知的製程以完成元件。舉例來說，可形成一或多層的介電層與金屬層，如適用於特定應用的後端製程(BEOL)技術。
第9-13圖顯示一實施例中，FinFET元件中具有應力通道區之半導體元件的形成方法。如第9圖所示，一實施例之部份基板900具有鰭狀物902自一絕緣區904延伸至另一絕緣區904。基板900可包含掺雜或未掺雜之基體矽，或絕緣層上半導體(SOI)的主動層。此外，基板可為鍺基板、矽鍺合金基板、III-V族基板、或類似基板。除了上述基板，亦可採用其他基板如多層基板或組成漸變式基板。絕緣區可為氧化矽層。
如第10圖所示，以非等向蝕刻製程使鰭狀物920凹陷。在後續的完整說明中，部份鰭狀物將被移除並置換為應力誘導區，接著在應力誘導區上再形成鰭狀物。在一實施例中，鰭狀物被蝕刻凹陷的深度需深到足以成長夠厚的應力誘導區，使應力誘導區表面不受應力誘導區與其下的基板之間的晶格不匹配影響。如此一來，應力誘導區表面將不會產生錯位。在這種結構中，應力誘導區將具有應力鬆弛的表面，其晶格結構將實質上類似於本身固有的晶格結構。舉例來說，鰭狀物902被蝕刻凹陷的試劑可採用HBr/O2 、HBr/Cl2 /O2 、或SF6 /Cl2 電漿，其蝕刻凹陷的深度介於約400至約3000之間。
如第11圖所示，形成應力誘導區1102。應力誘導區1102的形成材料及方法與前述第6圖之應力誘導區602的形成方法類似。
接著如第12圖所示，形成應力鰭狀物1202於應力誘導區1102上。應力鰭狀物1202之形成方法及方法與前述第7圖之應力區702類似。然而此實施例中，應力鰭狀物1202之高度高於絕緣區904。在一實施例中，應力鰭狀物1202的高度比絕緣區904高出約200至1000之間。
必需注意的是，形成應力鰭狀物1202的製程中可採用其他層。舉例來說，可採用遮罩層形成於絕緣區904上，以幫助固定應力鰭狀物1202的形狀，避免或減少應力鰭狀物1202在製程中延伸至絕緣區904的上表面。
如第13圖所示，係一實施例之源極/汲極區1304與金屬矽化區1302。必需注意的是，一般以橢圓形表示源極/汲極區1304。本技藝人士應了解源極/汲極的掺雜可為任何合適形狀，包括採用間隔物、襯墊、及/或犧牲襯墊/間隔物。
必需注意的是，第9-13圖中的實施例之鰭狀物的源極/汲極區將被移除並置換為下層的應力誘導區1102。然而在其他實施例中，鰭狀物之通道區被蝕刻凹陷，但不蝕刻凹陷源極/汲極區。在此實施例中，第9-12圖之製程係用以形成鰭狀物的通道區。此外，在又一實施例中，所有的鰭狀物(通道區與源極/汲極區)均被蝕刻凹陷。在此實施例中，第9-13圖之製程係用以形成鰭狀物的源極/汲極區，而第9-12圖之製程係用以形成鰭狀物的通道區。可以理解的是，此實施例之鰭狀物的通道區被置換，且掺雜型態可依需要而有所不同。
之後可進行本技藝已知的製程以完成元件。其他製程可包含形成閘極絕緣層、閘極、源極/汲極區、一或多層的介電層與金屬層、後端製程(BEOL)、或類似製程。
雖然本發明已以數個較佳實施例揭露如上，然其並非用以限定本發明，任何熟習此技藝者，在不脫離本發明之精神和範圍內，當可作任意之更動與潤飾，因此本發明之保護範圍當視後附之申請專利範圍所界定者為準。
102、602、1102‧‧‧應力誘導區
104、702‧‧‧應力區
106‧‧‧通道區
108‧‧‧源極區
110‧‧‧汲極區
400、900‧‧‧基板
402‧‧‧絕緣區
404、904‧‧‧閘極結構
410‧‧‧閘極絕緣層
412‧‧‧閘極
414‧‧‧側壁間隔物
502‧‧‧凹陷
802、1302‧‧‧金屬矽化區
804、1304‧‧‧源極/汲極區
902‧‧‧鰭狀物
1202‧‧‧應力鰭狀物
第1圖係本發明一實施例中，具有較大晶格結構之應力誘導區的剖視圖；第2圖係本發明一實施例中，平衡後之應力誘導區的剖視圖；第3圖係本發明一實施例中，具有較小晶格結構之應力誘導區的剖視圖；第4-8圖係本發明一實施例中，具有應力通道區之半導體元件的形成方法；以及第9-13圖係本發明一實施例中，具有應力通道區之半導體元件的形成方法。
400．．．基板
402．．．絕緣區
404．．．閘極結構
410．．．閘極絕緣層
412．．．閘極
414．．．側壁間隔物
602．．．應力誘導區
702．．．應力區
802．．．金屬矽化區
804．．．源極/汲極區

Claims (4)

  1. 一種半導體元件的形成方法，包括：提供一基板，其中該基板具有一鰭狀物延伸自一基板，以及絕緣區位於該鰭狀物的相反兩側；使至少部份該鰭狀物凹陷至該絕緣區上表面的下方；沿著該凹陷後的鰭狀物之上表面形成一應力誘導區；以及形成一應力鰭狀物於該應力誘導區上。
  2. 如申請專利範圍第1項所述之半導體元件的形成方法，其中該應力誘導區之晶格結構大於該應力鰭狀物之晶格結構，且該半導體元件係一NMOS元件。
  3. 如申請專利範圍第1項所述之半導體元件的形成方法，其中該應力誘導區之晶格結構小於該應力鰭狀物之晶格結構，且該半導體元件係一PMOS元件。
  4. 如申請專利範圍第1項所述之半導體元件的形成方法，其中該應力誘導區與該應力鰭狀物分別以相反電性之掺質掺雜。
TW099130826A 2010-03-30 2010-09-13 半導體元件與其形成方法 TWI481032B (zh)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US12/750,160 US8338259B2 (en) 2010-03-30 2010-03-30 Semiconductor device with a buried stressor

Publications (2)

Publication Number Publication Date
TW201133847A TW201133847A (en) 2011-10-01
TWI481032B true TWI481032B (zh) 2015-04-11

Family

ID=44697189

Family Applications (1)

Application Number Title Priority Date Filing Date
TW099130826A TWI481032B (zh) 2010-03-30 2010-09-13 半導體元件與其形成方法

Country Status (4)

Country Link
US (2) US8338259B2 (zh)
KR (1) KR101231429B1 (zh)
CN (1) CN102208443B (zh)
TW (1) TWI481032B (zh)

Families Citing this family (40)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8497528B2 (en) * 2010-05-06 2013-07-30 Taiwan Semiconductor Manufacturing Company, Ltd. Method for fabricating a strained structure
US9761666B2 (en) * 2011-06-16 2017-09-12 Taiwan Semiconductor Manufacturing Company, Ltd. Strained channel field effect transistor
US8962400B2 (en) * 2011-07-07 2015-02-24 Taiwan Semiconductor Manufacturing Company, Ltd. In-situ doping of arsenic for source and drain epitaxy
US8563374B2 (en) * 2011-09-16 2013-10-22 GlobalFoundries, Inc. Strained semiconductor devices having asymmetrical heterojunction structures and methods for the fabrication thereof
KR101867999B1 (ko) * 2011-10-31 2018-06-18 삼성전자주식회사 Ｉｉｉ-ｖ족 물질층을 형성하는 방법, ｉｉｉ-ｖ족 물질층을 포함하는 반도체 소자 및 그 제조방법
CN107068753B (zh) * 2011-12-19 2020-09-04 英特尔公司 通过部分熔化升高的源极-漏极的晶体管的脉冲激光退火工艺
US8785285B2 (en) 2012-03-08 2014-07-22 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor devices and methods of manufacture thereof
US9728464B2 (en) 2012-07-27 2017-08-08 Intel Corporation Self-aligned 3-D epitaxial structures for MOS device fabrication
CN103579004B (zh) * 2012-08-10 2016-05-11 中国科学院微电子研究所 FinFET及其制造方法
CN109216181A (zh) * 2012-11-30 2019-01-15 中国科学院微电子研究所 鳍结构制造方法
EP2741320B1 (en) * 2012-12-05 2020-06-17 IMEC vzw Manufacturing method of a finfet device with dual-strained channels
US9209174B2 (en) * 2013-02-15 2015-12-08 Globalfoundries Inc. Circuit element including a layer of a stress-creating material providing a variable stress and method for the formation thereof
US8823060B1 (en) * 2013-02-20 2014-09-02 Taiwan Semiconductor Manufacturing Co., Ltd. Method for inducing strain in FinFET channels
US9034715B2 (en) * 2013-03-12 2015-05-19 International Business Machines Corporation Method and structure for dielectric isolation in a fin field effect transistor
US9214555B2 (en) 2013-03-12 2015-12-15 Taiwan Semiconductor Manufacturing Co., Ltd. Barrier layer for FinFET channels
US10147793B2 (en) * 2013-07-30 2018-12-04 Samsung Electronics Co., Ltd. FinFET devices including recessed source/drain regions having optimized depths
US10396201B2 (en) 2013-09-26 2019-08-27 Intel Corporation Methods of forming dislocation enhanced strain in NMOS structures
US9276113B2 (en) 2014-03-10 2016-03-01 International Business Corporation Structure and method to make strained FinFET with improved junction capacitance and low leakage
US9184179B2 (en) 2014-03-21 2015-11-10 International Business Machines Corporation Thin channel-on-insulator MOSFET device with n+ epitaxy substrate and embedded stressor
US9824889B2 (en) * 2014-04-21 2017-11-21 Applied Materials, Inc. CVD silicon monolayer formation method and gate oxide ALD formation on III-V materials
US9601377B2 (en) 2014-10-17 2017-03-21 Taiwan Semiconductor Manufacturing Company, Ltd. FinFET formation process and structure
US9324623B1 (en) 2014-11-26 2016-04-26 Samsung Electronics Co., Ltd. Method of manufacturing semiconductor device having active fins
US9306038B1 (en) 2014-12-12 2016-04-05 International Business Machines Corporation Shallow extension junction
US9991384B2 (en) * 2015-01-15 2018-06-05 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device including fin structures and manufacturing method thereof
US9362400B1 (en) 2015-03-06 2016-06-07 International Business Machines Corporation Semiconductor device including dielectrically isolated finFETs and buried stressor
KR102351659B1 (ko) * 2015-04-03 2022-01-17 삼성전자주식회사 전계 효과 트랜지스터를 포함하는 반도체 소자
KR102395071B1 (ko) 2015-05-14 2022-05-10 삼성전자주식회사 전계 효과 트랜지스터를 포함하는 반도체 소자
US9520394B1 (en) * 2015-05-21 2016-12-13 International Business Machines Corporation Contact structure and extension formation for III-V nFET
US9685553B2 (en) * 2015-06-22 2017-06-20 Globalfoundries Inc. Generating tensile strain in bulk finFET channel
US10249502B2 (en) 2016-01-22 2019-04-02 International Business Machines Corporation Low resistance source drain contact formation with trench metastable alloys and laser annealing
CA3016157A1 (en) 2016-03-08 2017-09-14 Kerdea Technologies, Inc. Resistive based combustion sensing method and apparatus
US9978833B2 (en) 2016-03-11 2018-05-22 Samsung Electronics Co., Ltd. Methods for varied strain on nano-scale field effect transistor devices
US10304957B2 (en) * 2016-09-13 2019-05-28 Qualcomm Incorporated FinFET with reduced series total resistance
CN108122850B (zh) * 2016-11-28 2020-06-09 中芯国际集成电路制造(上海)有限公司 半导体结构及其形成方法
US20190088766A1 (en) * 2017-09-21 2019-03-21 Globalfoundries Inc. Methods of forming epi semiconductor material in source/drain regions of a transistor device formed on an soi substrate
KR20190110845A (ko) * 2018-03-21 2019-10-01 삼성전자주식회사 반도체 소자
US10720530B2 (en) 2018-09-27 2020-07-21 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and methods of forming same
US11088281B2 (en) * 2018-10-31 2021-08-10 Taiwan Semiconductor Manufacturing Company Limited Semiconductor arrangement and method of manufacture
US20220051945A1 (en) * 2020-08-13 2022-02-17 Taiwan Semiconductor Manufacturing Co., Ltd. Embedded Stressors in Epitaxy Source/Drain Regions
US11393915B2 (en) 2020-12-09 2022-07-19 Globalfoundries U.S. Inc. Epi semiconductor structures with increased epi volume in source/drain regions of a transistor device formed on an SOI substrate

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050095795A1 (en) * 2003-07-07 2005-05-05 Yong-Hoon Son MOS transistors having recesses with elevated source/drain regions and methods of fabricating such transistors
US20080265256A1 (en) * 2007-04-27 2008-10-30 Chun-Chieh Lin MOS devices with improved source/drain regions with SiGe
US20100038679A1 (en) * 2008-08-14 2010-02-18 International Business Machines Corporation Finfet with longitudinal stress in a channel

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7994020B2 (en) * 2008-07-21 2011-08-09 Advanced Micro Devices, Inc. Method of forming finned semiconductor devices with trench isolation
US7736982B2 (en) * 2008-10-14 2010-06-15 United Microelectronics Corp. Method for forming a semiconductor device
US20100109045A1 (en) * 2008-10-30 2010-05-06 Chartered Semiconductor Manufacturing Ltd. Integrated circuit system employing stress-engineered layers
DE102008063427B4 (de) * 2008-12-31 2013-02-28 Advanced Micro Devices, Inc. Verfahren zum selektiven Herstellen eines Transistors mit einem eingebetteten verformungsinduzierenden Material mit einer graduell geformten Gestaltung

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050095795A1 (en) * 2003-07-07 2005-05-05 Yong-Hoon Son MOS transistors having recesses with elevated source/drain regions and methods of fabricating such transistors
US20080265256A1 (en) * 2007-04-27 2008-10-30 Chun-Chieh Lin MOS devices with improved source/drain regions with SiGe
US20100038679A1 (en) * 2008-08-14 2010-02-18 International Business Machines Corporation Finfet with longitudinal stress in a channel

Also Published As

Publication number Publication date
US20110241084A1 (en) 2011-10-06
TW201133847A (en) 2011-10-01
US20130043507A1 (en) 2013-02-21
KR20110109775A (ko) 2011-10-06
KR101231429B1 (ko) 2013-02-07
CN102208443B (zh) 2013-10-30
CN102208443A (zh) 2011-10-05
US8338259B2 (en) 2012-12-25
US9219152B2 (en) 2015-12-22

Similar Documents

Publication Publication Date Title
TWI481032B (zh) 半導體元件與其形成方法
US9331200B1 (en) Semiconductor device and method for fabricating the same
US7494884B2 (en) SiGe selective growth without a hard mask
TWI545761B (zh) 半導體元件與其形成方法及ｐ型金氧半電晶體
CN104851912B (zh) 晶体管的应变引发方案
US8022488B2 (en) High-performance FETs with embedded stressors
US7554110B2 (en) MOS devices with partial stressor channel
US7678634B2 (en) Local stress engineering for CMOS devices
US9711417B2 (en) Fin field effect transistor including a strained epitaxial semiconductor shell
US20070020861A1 (en) Method to engineer etch profiles in Si substrate for advanced semiconductor devices
JP2007250665A (ja) 半導体装置及びその製造方法
CN101295733A (zh) 半导体元件
JP2013534052A (ja) 埋め込みストレッサ要素を含む半導体構造およびその製造方法
US9812571B2 (en) Tensile strained high percentage silicon germanium alloy FinFETs
US9054188B2 (en) Curved wafer processing on method and apparatus
US9397190B2 (en) Fabrication method of semiconductor structure
JP5076367B2 (ja) 半導体装置およびその製造方法
US9847393B2 (en) Semiconductor device
US9761693B2 (en) Method for fabricating semiconductor device
US9768262B2 (en) Embedded carbon-doped germanium as stressor for germanium nFET devices
CN104037224A (zh) 设计的用于n型MOSFET的源极/漏极区