CN104299971B - 具有不均匀p型杂质分布的mos器件 - Google Patents

具有不均匀p型杂质分布的mos器件 Download PDF

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Publication number
CN104299971B
CN104299971B CN201310452596.4A CN201310452596A CN104299971B CN 104299971 B CN104299971 B CN 104299971B CN 201310452596 A CN201310452596 A CN 201310452596A CN 104299971 B CN104299971 B CN 104299971B
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type impurity
silicon germanium
impurity concentration
germanium regions
regions
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CN104299971A (zh
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宋学昌
郭紫微
李昆穆
李资良
李启弘
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

本发明提供了具有不均匀P型杂质分布的MOS器件，其中，一种集成电路结构包括半导体衬底、位于半导体衬底之上的栅极堆叠件和延伸至半导体衬底中的开口，其中，开口与栅极堆叠件相邻。硅锗区被设置在开口中，其中，硅锗区具有第一p型杂质浓度。基本上不含锗的硅罩覆盖硅锗区。硅罩具有高于第一p型杂质浓度的第二p型杂质浓度。

Description

具有不均匀P型杂质分布的MOS器件
技术领域
本发明总的来说涉及集成电路，更具体地，涉及具有不均匀P型杂质分布的MOS器件。
背景技术
金属氧化物半导体（MOS）器件是集成电路的关键元件。MOS器件的性能影响其所在整个集成电路的性能。因此，研究提升MOS器件性能的方法。
发明内容
根据本发明的一个方面，提供了一种集成电路结构，包括：半导体衬底；位于半导体衬底之上的栅极堆叠件；延伸至半导体衬底中的开口，其中，开口邻近栅极堆叠件；位于开口中的硅锗区，硅锗区具有第一p型杂质浓度；以及位于硅锗区之上的基本上不含锗的硅罩，硅罩具有大于第一p型杂质浓度的第二p型杂质浓度。
优选地，硅锗区的一部分与硅罩相接触，且硅锗区的一部分在包含硅锗区和硅罩的金属氧化物半导体（MOS）器件的所有源极和漏极区中具有最高的p型杂质浓度。
优选地，该集成电路结构还包括延伸到硅罩中的硅化物区，硅罩包括位于硅化物区的侧面并与硅化物区在同一水平面上的第一部分。
优选地，硅化物区具有高于第一p型杂质浓度的第三p型杂质浓度。
优选地，该集成电路结构还包括延伸到硅罩和硅锗区中的硅化物区。
优选地，从硅罩的顶部到硅锗区的底部，p型杂质浓度逐渐降低。
优选地，硅锗区还包括上部和下部，且上部的p型杂质浓度高于下部的p型杂质浓度。
根据本发明的另一方面，提供了一种集成电路结构，包括：半导体衬底；位于半导体衬底之上的栅极堆叠件，其中，栅极堆叠件包含在金属氧化物半导体（MOS）器件之中；延伸至半导体衬底中的MOS器件的源极/漏极区，其中，源极/漏极区包括第一硅锗区和位于第一硅锗区之上的第二硅锗区，第一硅锗区具有第一锗百分比，第二硅锗区具有大于第一锗百分比的第二锗百分比；以及位于第二硅锗区之上并与第二硅锗区接触的硅罩，硅罩在源极/漏极区中具有最高的p型杂质浓度。
优选地，最高的p型杂质浓度高于约1E21/cm3。
优选地，硅罩基本上不含锗。
优选地，该集成电路结构还包括延伸至硅罩中的硅化物区，硅罩包括位于硅化物区的侧面并与硅化物区在同一水平面上的第一部分。
优选地，硅化物区具有的p型杂质浓度高于第二硅锗区的p型杂质浓度。
优选地，第二硅锗区的p型杂质浓度高于第一硅锗区的p型杂质浓度。
根据本发明的又一方面，提供了一种方法，包括：在半导体衬底上方形成栅极堆叠件；形成延伸至半导体衬底中的开口，开口位于栅极堆叠件的侧面；执行第一外延以在开口中生长第一硅锗区，其中，在第一外延期间，第一硅锗区被原位掺杂至第一p型杂质浓度；以及执行第二外延以在第一硅锗区之上生长基本上不含锗的硅罩，其中，在第二外延期间，硅罩被原位掺杂至高于第一p型杂质浓度的第二p型杂质浓度。
优选地，该方法还包括：在第一外延之前，执行第三外延以在第一硅锗区下方生长第二硅锗区，第二硅锗区比第一硅锗区具有更高的锗百分比，其中，在第三外延期间，第二硅锗区被原位掺杂至低于第一p型杂质浓度的第三p型杂质浓度。
优选地，该方法还包括：在第一外延之前，执行第三外延以在第一硅锗区下方生长第二硅锗区，其中，在第三外延期间，基本上没有掺杂p型杂质。
优选地，第二p型杂质浓度与第一p型杂质浓度的比值大于10。
优选地，在第二外延期间，没有锗被引入到硅罩中。
优选地，该方法还包括：在形成硅罩后，在栅极堆叠件和硅罩上方形成层间电介质（ILD）；在ILD中形成接触开口，其中，硅罩暴露于接触开口；在形成接触开口后，对硅罩执行硅化；以及以导电材料填充接触开口。
优选地，在硅化之后，硅罩的一部分仍未被硅化，并且在硅化期间，第一硅锗区的一部分被硅化。
附图说明
为了更好地理解实施例及其优点，现在将结合附图所进行的以下描述作为参考，其中：
图1至图10是根据一些示例实施例的制造金属氧化物半导体（MOS）器件的中间阶段的截面图；以及
图11示意性示出了根据一些可选示例实施例的MOS器件中的p型杂质的示例性分布。
具体实施方式
下面，详细讨论本发明优选实施例的制造和使用。然而，应该理解，本发明提供了许多可以在各种具体环境中实现的可应用的概念。所讨论的具体实施例仅仅示出制造和使用本发明的具体方式，而不用于限制本公开的范围。
在过去几十年里，半导体器件（如金属氧化物半导体（MOS）器件）尺寸的减小及其固有部件的减少使得集成电路的速度、性能、集成度和每单位功能成本得到持续改善。根据MOS器件的设计和其中一个固有特性，调整MOS器件的源极和漏极之间的栅极下面的沟道区的长度改变与沟道区相关的电阻，从而影响MOS器件的性能。更具体地，假设其他参数维持相对稳定，缩短沟道区的长度会降低MOS器件的源极-漏极电阻，当向MOS器件的栅极施加足够的电压时，可增加源极与漏极之间的电流流动。
为进一步增强MOS器件的性能，可将应力引入到MOS器件的沟道区中以提高载流子迁移率。通常，期望在n型MOS（“NMOS”）器件的沟道区中沿源极至漏极方向引入拉应力，而在p型MOS（“PMOS”）器件的沟道区中沿源极至漏极方向引入压应力。
向PMOS器件的沟道区施加压应力的可用方法为在源极和漏极区中生长SiGe应激源。这种方法通常包括以下步骤：在半导体衬底上形成栅极堆叠件；在栅极堆叠件的侧壁上形成间隔件；沿着栅极间隔件在硅衬底中形成凹槽；在凹槽中外延生长SiGe应激源；以及退火。由于SiGe相较于硅具有较大晶格常数，因此SiGe在退火后会膨胀从而向位于源极SiGe应激源和漏极SiGe应激源之间的沟道区施加压应力。
根据各个示例实施例提供了一种形成金属氧化物半导体（MOS）器件的工艺。附图中示出了形成MOS器件的中间阶段。说明书中论述了实施例的变型。纵观各个视图和所示实施例，相同附图编号用于标示出相同元件。
图1示出了衬底20，其为晶圆10的一部分。衬底20可以是诸如硅衬底的块状半导体衬底，或者可具有诸如绝缘体上硅（SOI）结构的复合结构。可选地，衬底20也可包括含有III族、IV族和/或V族元素的其他半导体材料，这些半导体材料可包括硅锗、硅碳和/或III-V族化合物半导体材料。
栅极堆叠件22在衬底20之上形成，且包括栅极介电质24和栅电极26。栅极介电质24可包括氧化硅和/或具有高k值（如高于7）的高k材料。栅电极26可包括常用的导电材料，如掺杂多晶硅、金属、金属硅化物、金属氮化物及它们的组合。栅极堆叠件22还可包括硬掩膜28，硬掩膜28可例如含有氮化硅，然而还可使用诸如硅碳、氮氧化硅等的其他材料。
如图2所示，可例如通过在衬底20中注入p型杂质（如硼和/或铟）形成轻掺杂漏/源极（LDD）区30。栅极堆叠件22和硬掩膜28充当注入掩膜，使得LDD区30的内边缘分别与栅极堆叠件22的边缘基本齐平。LDD注入可使用范围在约1keV和约10keV之间的能量和范围在约1x1013/cm2和约1x1016/cm2之间的剂量实施。然而，应该理解，在整个说明书中列举的值仅仅是示例，并可变更为不同值。LDD可以是倾斜注入（倾斜角范围在0度与30度之间）或垂直注入。另外，还可例如通过在衬底20中注入n型杂质（如砷、磷等）而形成口袋区32。口袋注入可使用范围在约20keV和约80keV之间的能量和范围在约1x1012/cm2和约1x1014/cm2之间的剂量实施。口袋注入可以是倾斜的，其中倾斜角大于LDD注入的倾斜角。在一些实施例中，口袋注入的倾斜角在大约15度和约45度之间。
参见图3，栅极间隔件34形成在栅极介电质24和栅电极26的侧壁上。在一些实施例中，每个栅极间隔件34均包括氧化硅层（未示出）和位于氧化硅层上方的氮化硅层，其中氧化硅层的厚度可在大约15埃和大约50埃之间，而氮化硅层的厚度可在大约50埃和大约200埃之间。在另一些实施例中，栅极间隔件34包括一个或多个层，每层均包括氧化硅、氮化硅、氮氧化硅和/或其他介电材料。可用的形成方法包括等离子体增强化学汽相沉积（PECVD）、低压化学汽相沉积（LPCVD）、次常压化学汽相沉积（SACVD）及其他沉积方法。
仍然如图3所示，执行各向同性蚀刻以在衬底20中形成开口36。各向同性蚀刻可为干蚀刻，其中蚀刻气体可从CF4、Cl2、NF3、SF6及它们的组合中选择。例如，开口36的深度D1可在约150埃和约500埃之间。
接下来，如图4所示，执行湿蚀刻以扩展开口36。可例如使用羟化四甲铵（TMAH）、氢氧化钾（KOH）溶液等来执行湿蚀刻。在一些示例性实施例中，TMAH溶液的浓度在大约1%和大约30%之间的范围内。在湿蚀刻过程中，TMAH的温度可在大约20℃和大约100℃之间。在湿蚀刻之后，在开口36中形成小平面（facet），其包括衬底20的（111）平面。在一些示例实施例中，在湿蚀刻之后，开口36的深度D2可例如在大约300埃和大约800埃之间的范围内。
图5示出了外延层38的形成。在外延之前，可例如使用以基于HF的气体或基于SiCoNi的气体进行预清洁。预清洁可去除由于开口36中暴露表面的自然氧化而形成的任何不期望的氧化硅。在一些实施例中，可执行高温烘烤。在可选实施例中，可跳过烘烤步骤。高温烘烤在有无HCl气体的情况下均可实施。烘烤温度可在大约700℃和大约900℃之间的范围内。烘烤气压可在大约10托和大约200托之间的范围内。烘烤时间可例如在大约30秒和大约4分钟之间的范围内。高温烘烤也可去除衬底20的暴露表面（其位于开口36中）上的自然氧化物。
如图5所示，诸如硅锗（SiGe）的半导体材料通过选择性外延生长（SEG）而在开口36中外延生长，从而形成外延层38。因此，在整个说明书中，外延层38也被称为SiGe层38。工艺气体可包括H2、N2、二氯硅烷（DCS）、SiH4、GeH4等等。外延温度可在大约600℃与大约900℃之间的范围内。在一些实施例中，加入蚀刻气体以促进在衬底20的暴露表面上而非诸如栅极间隔件34和硬掩模28的介电质上的选择性生长。工艺气体的气压可在大约10托和大约200托之间的范围内。由此产生的SiGe层38的厚度T1可例如在大约100埃和大约400埃之间的范围内。
在外延期间，当生长进行时可掺杂期望的p型杂质。例如，当掺杂硼时，B2H6可包含在工艺气体中。在一些实施例中，外延层38中的p型杂质（如硼）的杂质浓度可低于1E19/cm3。在其他实施例中，p型杂质的杂质浓度可在大约1E18/cm3和大约1E20/cm3之间的范围内。在可选实施例中，在层38的外延期间，没有原位掺杂p型杂质或基本上没有掺杂杂质（例如，p型杂质浓度低于1014/cm3）。外延层38可具有例如在大约10%和大约30%之间的第一锗原子百分比，然而还可使用不同的锗百分比。
参见图6，外延层42通过外延进行生长。外延层42相较于外延层38具有不同的组分（包含的元素及元素的百分比）。在一些实施例中，外延层42是SiGe层，其具有的锗原子百分比高于外延层38中的锗原子百分比。例如，外延层42具有大约30%和大约60%之间的第二锗原子百分比。除调整含硅气体与含锗气体的比率之外，形成外延层42的工艺条件与形成外延层38的工艺条件类似。在一些实施例中，外延层42的顶面42A高于衬底20的顶面20A。外延层38和42结合形成MOS器件的部分源极区或漏极区（以及源极或漏极应激源），MOS器件还包括一个栅极堆叠件22作为其栅极。
另外，在外延期间，在外延进行时可原位掺杂p型杂质。外延层42中的p型杂质浓度C42可高于外延层38中的p型杂质浓度。例如，p型杂质浓度C42可在大约1E20/cm3和大约8E20/cm3之间。另外，根据一些实施例，比值C42/C38可大于10，其中C42和C38分别是外延层42和38的p型杂质浓度（它们为原位掺杂而未进行额外的热处理）。
外延层42还包括具有不同p型杂质浓度的下层和上层，其中下层和上层中均具有基本均匀的原位掺杂p型杂质浓度。图6示意性示出了虚线43以标记外延层42的上层与下层之间的界面。另外，上层中的锗百分比C42A高于下层中的锗百分比C42B。在一些实施例中，p型杂质浓度比值C42A/C42B大于约5。
在一些实施例中，在外延层38和42的每一个之中，锗百分比均基本均匀。在可选实施例中，外延层38和42中的一个或两个都具有逐渐连续变化的锗百分比。在对应的外延期间，含锗前体（如GeH4）的流速可逐渐连续地改变。在这些实施例中，在锗百分比逐渐改变的层中，其下部的锗百分比低于上层的锗百分比。
如图7所示，在形成外延层42之后，通过外延形成覆盖层44。覆盖层44相较于外延层42具有不同的组分（包括其中包含的元素及元素的百分比）。覆盖层44可为不包含锗的纯硅层，或者为锗含量例如低于2%或1%的基本纯的硅层。因此，在整个说明书中，覆盖层44可选地被称为硅罩。覆盖层44也可为SiGe层，其中覆盖层44的锗浓度低于外延层42的锗浓度。
在覆盖层44的外延生长期间，在进行外延生长时可原位掺杂p型杂质（如硼）。在一些实施例中，覆盖层44中的p型杂质浓度高于外延层42和38中的p型杂质浓度。覆盖层44在相应MOS器件的外延层38和42和/或源极/漏极区的所有部分中具有最高的硼浓度，在一些示例实施例中，该最高浓度可高于约1E21/cm3。覆盖层44中的p型杂质浓度C44与外延层42中的p型杂质浓度C42的比值大于约5。比值C44/C42（其可为掺杂值或为随后热处理后的值）还可在大约5和大约15之间。在一些实施例中，p型杂质浓度C44大于约1E21/cm3，并可在大约1E21/cm3和大约8E21/cm3之间。外延层38、42和44的生长可在同一腔室中不破坏真空的条件下原位执行。
接下来，去除硬掩膜28，由此产生的结构在图8中示出。图8也示出了层间介电质（ILD）46的形成，其由诸如磷硅酸盐玻璃（PSG）、硼硅酸盐玻璃（BSG）、掺硼磷硅酸盐玻璃（BPSG）等的介电材料形成。可执行CMP以平整化ILD46的顶面。接下来，形成接触开口48（包括栅极接触开口48A和源极/漏极接触开口48B），暴露下面的栅电极26和覆盖层44。
图9示出了栅极硅化物区50和源级/漏极硅化物区52的形成。硅化物区50和52可通过在包括覆盖层44和栅电极26的暴露表面的器件上沉积金属硅化物的薄层来形成，其中金属硅化物如钛、钴、镍、钨等的硅化物。然后加热晶圆10，这会在金属与硅接触的地方引发硅化反应。在反应之后，硅与金属之间形成金属硅化物层。未反应的金属通过使用侵蚀金属但不侵蚀硅化物的蚀刻剂选择性地去除。由于硅化，源级/漏极硅化物区52延伸进覆盖层44，并且可以延伸进外延层42。可选地，覆盖层44的顶部被硅化，而覆盖层44的底部未被硅化。在硅化之后，覆盖层44的一部分44A仍未被硅化，其中部分44A与源级/漏极硅化物区52平齐且位于源级/漏极硅化物区52的相对侧。
图10示出了源极/漏极接触插塞54和栅极接触插塞56的形成，其通过下面步骤形成：将诸如钨、铜、铝、钛、钴、硅、锗等的导电材料填充到开口48内；然后执行CMP以使接触插塞54和56的顶面与ILD46的顶面齐平。MOS晶体管60因此形成，其包括外延层38、42，并可能包括作为源极和极漏区的覆盖层44的剩余部分。
图11示意性示出了MOS器件60的源极区和漏极区中的硼分布，其中该分布代表沿图10中箭头62的路径的硼浓度。硼浓度反映了在接下来的热处理（诸如形成上覆金属层）之后由硼在互连结构中的扩散产生的浓度。还示出了各个区38、42、44和52。X轴表示从箭头62的顶端开始测量的深度。Y轴表示硼的示意性浓度。由于图11是示意性的，因此并未标记X轴和Y轴的值。如图11所示，硼浓度在层/区44和52的顶部最高。外延层42的硼浓度低于硅罩和硅化物区52的硼浓度。外延层38的硼浓度低于外延层42的硼浓度。另外，区域38、42和44/52的斜率分别被示出为斜率68、66和64，其中斜率64大于斜率66，斜率66大于斜率68，其中斜率之间的差别是由原位掺杂的p型杂质的扩散引起的。
在本发明的实施例中，在p型杂质浓度在源级/漏极区的上部较高而在源级/漏极区的下部较低的情况下，从外延区到下面的衬底的扩散最小。因此，改善了所得MOS器件的短沟道效应（SCE）。另外，由于源级/漏极区的顶部具有增加的p型杂质浓度，因此降低了源级/漏极区中的电阻。
根据一些实施例，一种集成电路结构包括半导体衬底、位于半导体衬底之上的栅极堆叠件和延伸到半导体衬底中的开口，开口与栅极堆叠件相邻。硅锗区布置在开口中，其中硅锗区具有第一p型杂质浓度。基本上不含锗的硅罩上覆于硅锗区。硅罩具有大于第一p型杂质浓度的第二p型杂质浓度。
根据其他实施例，一种集成电路结构包括半导体衬底和位于半导体衬底之上的栅极堆叠件。MOS器件中包含栅极堆叠件。MOS器件的源级/漏极区延伸到半导体衬底中。源级/漏极区包括第一硅锗区和位于第一硅锗区之上的第二硅锗区。第一硅锗区具有第一锗百分比，而第二硅锗区具有大于第一锗百分比的第二锗百分比。硅罩上覆于第二硅锗区并与其相接触。硅罩在源级/漏极区中具有最高的p型杂质浓度。
根据其他实施例，一种方法包括在半导体衬底之上形成栅极堆叠件并形成延伸至半导体衬底中的开口。开口位于栅极堆叠件的侧面。该方法进一步包括实施第一外延以在开口中生长第一硅锗区，在第一外延期间，第一硅锗区被原位掺杂至第一p型杂质浓度。然后实施第二外延以在第一硅锗区之上生长基本上不含锗的硅罩。在第二外延期间，硅罩被原位掺杂至高于第一p型杂质浓度的第二p型杂质浓度。
尽管已经详细地描述了本发明及其优势，但应该理解，可以在不背离所附权利要求限定的本发明主旨和范围的情况下，做各种不同的改变，替换和更改。而且，本申请的范围并不仅限于本说明书中描述的工艺、机器、制造、材料组分、装置、方法和步骤的特定实施例。作为本领域普通技术人员应理解，通过本发明，现有的或今后开发的用于执行与根据本发明所采用的所述相应实施例基本相同的功能或获得基本相同结果的工艺、机器、制造，材料组分、装置、方法或步骤根据本发明可以被使用。因此，所附权利要求应该包括在这样的工艺、机器、制造、材料组分、装置、方法或步骤的范围内。此外，每条权利要求构成单独的实施例，并且多个权利要求和实施例的组合在本发明的范围内。

Claims (19)

1.一种集成电路结构，包括：
半导体衬底；
位于所述半导体衬底之上的栅极堆叠件；
延伸至所述半导体衬底中的开口，其中，所述开口邻近所述栅极堆叠件；
位于所述开口中的第一硅锗区，所述第一硅锗区具有第一p型杂质浓度；以及
位于所述第一硅锗区之上的不含锗的硅罩，所述硅罩具有大于所述第一p型杂质浓度的第二p型杂质浓度，
第二硅锗区，直接位于所述第一硅锗区的下方，并且具有低于所述第一p型杂质浓度的第三p型杂质浓度。
2.根据权利要求1所述的集成电路结构，其中，所述第一硅锗区的一部分与所述硅罩相接触，且所述第一硅锗区的所述一部分在包含所述第一硅锗区和所述硅罩的金属氧化物半导体(MOS)器件的所有源极和漏极区中具有最高的p型杂质浓度。
3.根据权利要求1所述的集成电路结构，还包括延伸到所述硅罩中的硅化物区，所述硅罩包括位于所述硅化物区的侧面并与所述硅化物区在同一水平面上的第一部分。
4.根据权利要求3所述的集成电路结构，其中，所述硅化物区具有高于所述第一p型杂质浓度的第三p型杂质浓度。
5.根据权利要求1所述的集成电路结构，还包括延伸到所述硅罩和所述第一硅锗区中的硅化物区。
6.根据权利要求1所述的集成电路结构，其中，从所述硅罩的顶部到所述第一硅锗区的底部，p型杂质浓度逐渐降低。
7.根据权利要求1所述的集成电路结构，其中，所述第一硅锗区还包括上部和下部，且所述上部的p型杂质浓度高于所述下部的p型杂质浓度。
8.一种集成电路结构，包括：
半导体衬底；
位于所述半导体衬底之上的栅极堆叠件，其中，所述栅极堆叠件包含在金属氧化物半导体(MOS)器件之中；
延伸至所述半导体衬底中的所述MOS器件的源极/漏极区，其中，所述源极/漏极区包括：
第一硅锗区，所述第一硅锗区具有第一锗百分比；和
位于所述第一硅锗区之上的第二硅锗区，所述第二硅锗区具有大于所述第一锗百分比的第二锗百分比；以及
位于所述第二硅锗区之上并与所述第二硅锗区接触的硅罩，所述硅罩在所述源极/漏极区中具有最高的p型杂质浓度，
其中，从所述硅罩的顶部到所述第一硅锗区的底部，p型杂质浓度逐渐降低。
9.根据权利要求8所述的集成电路结构，其中所述最高的p型杂质浓度高于1E21/cm3。
10.根据权利要求8所述的集成电路结构，其中，所述硅罩不含锗。
11.根据权利要求8所述的集成电路结构，还包括延伸至所述硅罩中的硅化物区，所述硅罩包括位于所述硅化物区的侧面并与所述硅化物区在同一水平面上的第一部分。
12.根据权利要求11所述的集成电路结构，其中，所述硅化物区具有的p型杂质浓度高于所述第二硅锗区的p型杂质浓度。
13.根据权利要求8所述的集成电路结构，其中，所述第二硅锗区的p型杂质浓度高于所述第一硅锗区的p型杂质浓度。
14.一种形成集成电路结构的方法，包括：
在半导体衬底上方形成栅极堆叠件；
形成延伸至所述半导体衬底中的开口，所述开口位于所述栅极堆叠件的侧面；
执行第一外延以在所述开口中生长第一硅锗区，其中，在所述第一外延期间，所述第一硅锗区被原位掺杂至第一p型杂质浓度；以及
执行第二外延以在所述第一硅锗区之上生长不含锗的硅罩，其中，在所述第二外延期间，所述硅罩被原位掺杂至高于所述第一p型杂质浓度的第二p型杂质浓度，
其中，所述方法还包括：
在所述第一外延之前，执行第三外延以在所述第一硅锗区下方直接生长第二硅锗区，所述第二硅锗区比所述第一硅锗区具有更高的锗百分比，其中，在所述第三外延期间，所述第二硅锗区被原位掺杂至低于所述第一p型杂质浓度的第三p型杂质浓度。
15.根据权利要求14所述的方法，还包括：
在所述第一外延之前，执行第三外延以在所述第一硅锗区下方生长第二硅锗区，其中，在所述第三外延期间，没有掺杂p型杂质。
16.根据权利要求14所述的方法，其中，所述第二p型杂质浓度与所述第一p型杂质浓度的比值大于10。
17.根据权利要求14所述的方法，其中，在所述第二外延期间，没有锗被引入到所述硅罩中。
18.根据权利要求14所述的方法，还包括：
在形成所述硅罩后，在所述栅极堆叠件和所述硅罩上方形成层间电介质(ILD)；
在所述ILD中形成接触开口，其中，所述硅罩暴露于所述接触开口；
在形成所述接触开口后，对所述硅罩执行硅化；以及
以导电材料填充所述接触开口。
19.根据权利要求18所述的方法，其中，在所述硅化之后，所述硅罩的一部分仍未被硅化，并且在所述硅化期间，所述第一硅锗区的一部分被硅化。
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