CN102543752A - 半导体装置及其制造方法 - Google Patents

半导体装置及其制造方法 Download PDF

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CN102543752A
CN102543752A CN2011104184299A CN201110418429A CN102543752A CN 102543752 A CN102543752 A CN 102543752A CN 2011104184299 A CN2011104184299 A CN 2011104184299A CN 201110418429 A CN201110418429 A CN 201110418429A CN 102543752 A CN102543752 A CN 102543752A
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sige alloy
strain inducing
inducing sige
germanium
carbon
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S·克隆霍尔兹
G·比尔宁克
I·奥斯特麦
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GlobalFoundries Inc
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Abstract

本发明提供一种半导体装置及其制造方法。该方法包含在半导体区域中形成横向邻接在晶体管的栅极电极结构的孔穴。该栅极电极结构是设置在第一硅锗合金的沟道区域上。应变诱导硅锗合金是形成在该孔穴中且与该第一硅锗合金接触。该应变诱导硅锗合金包含碳且具有与该第一硅锗合金不同的组成。

Description

半导体装置及其制造方法
技术领域
本发明一般是关于半导体装置及用于制造半导体装置的方法，尤其是关于具有效能被强化的晶体管的半导体装置以及用于制造此半导体装置的方法，该效能强化通过在漏极及源极区域中使用应变诱导硅锗合金以加强在该晶体管的沟道区域中的电荷载体沟道迁移率而达成。
背景技术
现今大多数的集成电路(IC)通过使用多个互连场效晶体管(FET)来实施，亦称作金属氧化物半导体场效晶体管(MOSFET)，或简称MOS晶体管。FET包含作为控制电极的栅极电极结构和电流能流过其间的漏极及源极区域。施加至栅极电极结构的控制电压控制电流通过源极及漏极电极间的沟道区域。
FET的栅极通常由转移电导(gm)所定义，且与晶体管沟道区域中的主要载体的迁移率成比例。MOS晶体管的电流携带能力与转移电导乘上沟道区域的宽度再除以沟道的长度成比例(gmW/l)。FET通常制造在具有(100)结晶表面方位的硅衬底上，其常见于硅技术。对此以及其它许多方位，电洞的迁移率，即P沟道FET(PFET)中的主要载体，能通过将压缩纵向应力施加至沟道区域而增加。通过将膨胀材料，例如以选择性外延生长工艺形成的假晶硅锗，嵌入在硅衬底中在晶体管沟道区域的末端处(在晶体管沟道的末端处的外延锗化硅在此亦称作「eSiGe」)，而能将压缩纵向应力施加至FET的沟道区域。硅锗结晶的晶格常数大于硅结晶的晶格常数，且因此嵌入的硅锗导致硅基(silicon matrix)的变形(deformation)，因而压缩沟道区域中的材料。
用来形成晶体管沟道区域的材料还影响沟道区域的电荷载体沟道迁移率。已发现硅锗的各种合金为适合的材料用来形成晶体管沟道区域(沟道硅锗在此还称作「cSiGe」)，且特别用来形成PFET装置的沟道区域。然而，两个不同的硅锗层，即eSiGe及cSiGe，一般会有不同的对应晶格结构及晶格含量而有不同的组成。在此两个层接口处，在栅极电极结构的横向下方，由于不同的晶格结构或含量，会发生差排(dislocation)或晶格分离。此些差排导致漏电流。再者，此些差排会于通常在制造半导体装置的后期步骤期间使用的热处理及退火工艺期间还扩大。
据此，需要提供半导体装置及制造半导体装置的方法，其中场效晶体管具有增强的电荷载体沟道迁移率及减少的漏电流。再者，其它所需的特征及特性，将因后续的实施方式及附加权利要求和附加图式及前述的技术领域及背景技术而变得显而易见。
发明内容
在此提供一种半导体装置及制造半导体装置的方法。依据例示性实施例，提供制造半导体装置的方法。该方法包含在半导体区域中形成横向邻接在晶体管的栅极电极结构的孔穴。该栅极电极结构是设置在第一硅锗合金的沟道区域上。应变诱导硅锗合金是形成在该孔穴中且与该第一硅锗合金接触。该应变诱导硅锗合金包含碳且具有与该第一硅锗合金不同的组成。
依据另一个例示性实施例，提供一种制造半导体装置的方法。该方法包含在形成在P型晶体管的主动区域中的孔穴中形成应变诱导硅锗合金而使该应变诱导硅锗合金与定义出该P型晶体管的沟道区域的第一硅锗合金接触。该第一硅锗合金具有与包含碳的该应变诱导硅锗合金不同的组成。漏极及源极区域是至少部分地形成在该应变诱导硅锗合金中。
依据另一个例示性实施例，提供一种半导体装置。半导体装置包含含硅半导体区域。沟道区域是由形成在该含硅半导体区域中的第一硅锗合金所形成的。栅极电极结构是形成在该沟道区域上。漏极及源极区域是形成在该含硅半导体区域中邻接在该沟道区域。应变诱导硅锗合金包含碳且是至少部分地形成在该漏极及源极区域中。该应变诱导硅锗合金与该第一硅锗合金接触且具有与该第一硅锗合金不同的组成。金属硅化物是形成在该应变诱导硅锗合金中及至少部分地在该漏极及源极区域中。
附图说明
以上搭配附加图式来叙述本发明的实施例，其中类似的组件符号代表类似的组件，且其中：
图1至6是依据例示性实施例示意性地描绘在其制造的阶段期间的半导体装置的截面视图。
具体实施方式
以下实施方式仅在本质上为例示性的且并非意图来限制本发明或本发明的应用及使用。再者，并非意图以在前面的背景技术或后面的实施方式中表达的任何理论来限制。
考虑在此的各种实施例是关于半导体装置及用于制造半导体装置的方法。在半导体装置的制造的中间阶段期间，在半导体区域中形成横向地邻接在晶体管的栅极电极结构的孔穴。栅极电极结构是设置在由沟道硅锗合金层(cSiGe)所形成的沟道区域上。应变诱导硅者合金层(eSiGe)接着形成在孔穴中且与cSiGe层接触。eSiGe层含有相对低总量的碳且具有与cSiGe层不同的组成，据此，eSiGe及cSiGe层很可能具有不同的对应晶格结构及晶格内容物。在例示性实施例中，eSiGe层的碳含量大约为0.05至0.2原子百分比，且更佳为大约0.1原子百分比。发明人已发现到，通过在eSiGe层中具有相对低总量的碳，减少或最小化且更佳地消除eSiGe及cSiGe层间的差排，而几乎不影响通过eSiGe层施加至沟道的压缩应变。不受理论限制，相信出现在eSiGe层中的一些碳是置换地排列在硅锗结晶结构的横向侧，取代一些硅且在两个层间的接口处局部地充分松弛应变以减少差排。碳的其它主要部分被认为是排列在硅锗结晶结构的接口侧上以捕捉或阻挡差排。因此，由于eSiGe层在沟道中产生压缩应变，晶体管较佳地强化电荷载体沟道迁移率，又，由于eSiGe及cSiGe层间的差排的消除，晶体管较佳地减少漏电流。
参照图1，提供依据例示性实施例的于中间制造阶段的半导体装置10的示意性截面图。半导体装置10包含衬底12。在衬底12上方为半导体层14，其可代表包含在结晶状态中的高分数的硅的含硅半导体材料。如图所示，埋入式绝缘层16位于衬底12及半导体层14间，且层12、14及16的组合代表绝缘体上硅(SOI)。在其它例子中，半导体层14可形成在衬底12的结晶半导体材料上，藉此提供「块体」结构。应体会到，若认为有利的话，SOI结构及块体结构可同时使用在装置10不同的的装置区域中。
在例示性实施例中，隔离结构18设置在半导体层14中。隔离结构18定义对应的主动区域20及22，其欲被看作是形成在其中的及或当需要来形成晶体管组件时接收适当的掺质的半导体区域。在一个实施例中，主动区域20及22对应于晶体管24及晶体管26的主动区域，其分别代表N沟道晶体管及P沟道晶体管。
如图所示，晶体管24及26包含对应的栅极电极结构28及30。栅极电极结构28及30可包含相同或不同的电极材料或材料32，例如硅、硅锗，含金属材料等，接着是氧化物层33及盖层34。氧化物层33可为二氧化硅等，盖层34可为氮化硅等。栅极电极结构28及30亦包含栅极绝缘层36，其将电极材料32与晶体管24及26的沟道区域38及40分开。再者，晶体管24的栅极电极结构28被间隔件层42所封装，其亦覆盖主动区域20。另一方面，晶体管26的栅极电极结构30的电极材料32被盖层34及侧壁间隔件44所封装，其可为氮化硅等。侧壁间隔件44的宽度46实质地定义欲形成在主动区域22中的孔穴的横向偏移。在例示性实施例中，晶体管26的沟道区域40是由具有电子特性的沟道锗化硅(cSiGe)形成，其至少可局部地基于应变诱导机制而强化。如图所示，沟道区域40是硅锗层48的部分，其横跨主动区域22的实质上表面部分。较佳地，沟道区域40的cSiGe层具有大约20至大约40原子百分比的锗浓度，且更佳地，从大约28至大约32原子百分比。
如图1所示的半导体装置10可基于以下工艺而形成。在形成隔离结构18之后，包含光刻、蚀刻、沉积、平坦化技术等，可例如通过离子植入来建立主动区域20及22的基本掺杂。接着，形成硅锗层48，包含光刻技术、蚀刻、选择性外延生长、平坦化技术等。之后，可通过形成及基于光刻及蚀刻技术来图案化适当的层堆积而形成包含氧化物层33及盖层34的栅极电极结构28及30。接下来，可沉积间隔件层42，以及可形成蚀刻屏蔽50，例如光阻屏蔽，以当曝露关于晶体管26的层42时，遮盖关于晶体管24的间隔件层42。此后，可实施各向异性蚀刻工艺以蚀刻间隔件层42的曝露部分，藉此形成侧壁间隔件44以及曝露盖层34。
参照图2，提供依据例示性实施例的在进一步进阶制造阶段中的半导体装置10的示意性描绘。实施蚀刻工艺52以形成孔穴54。在一个实施例中，蚀刻屏蔽50覆盖晶体管24及周围区域而让晶体管26及周围硅锗层48曝露。蚀刻工艺52可代表用于形成侧壁间隔件44及盖层34以及依序地蚀刻穿过硅锗层48的曝露的部分且进一步进入主动区域22以形成孔穴54的蚀刻顺序。应体认到，孔穴54可形成在栅极电极结构30的两侧，而在其它例子中，若欲提供关于外延锗化硅(eSiGe)(显示在图3中)的非对称晶体管结构，可遮蔽此些侧的一者。应进一步体认到，可基于以等离子辅助蚀刻而完成的为基础的实质上的各向异性蚀刻反应来形成孔穴54，而在其它例子中，可通过湿式化学蚀刻化学性质来形成孔穴54，其可具有结晶各异向性蚀刻反应，或基于等离子辅助及湿式化学蚀刻化学性质的组合。在例示性实施例中，硅锗层48中被侧壁间隔件44及包含盖层34的栅极电极结构30所保护并在蚀刻工艺52之后仍保留的部分，定义沟道区域40。
参照图3，提供依据例示性实施例的在进一步进阶制造阶段中的半导体装置10的示意性描绘。如图所示，装置10曝露在选择性外延生长工艺56以在孔穴54内形成硅锗层58。在一个实施例中，可基于含硅及锗的前驱气体以及适当的工艺参数来建立选择性外延生长工艺56以在孔穴54内获得硅锗合金的选择性沉积而避免依序地在例如为隔离结构18、盖层34、间隔件层42及侧壁间隔件44的介电表面上沉积材料。于此实施例中，在后续的工艺中通过离子植入60来将碳导入硅锗层58并据此形成含碳的eSiGe层62。在另外的实施例中，选择性外延生长工艺56包含合适的前驱气体及适当的工艺参数以获得具有碳的硅锗合金的选择性沉积来形成含碳的eSiGe层62。在另一个实施例中，eSiGe层62的碳内容物较佳地由大约0.05至大约0.2原子百分比形成且更佳地为大约0.1原子百分比。
结果，在沉积有效地作为应变诱导硅锗层的eSiGe层62之后，可实质地通过eSiGe层62的锗含量及始于沟道区域40的横向偏移来决定在沟道区域40及其下方的主动区域22中的压缩应变组件64。在例示性实施例中，eSiGe层62的锗浓度低于沟道区域40的cSiGe合金的锗浓度。较佳地，eSiGe层62的锗浓度大约为22至24原子百分比。在至少一个实施例中，通过后续的退火来增加且更完全地实现压缩应变组件64，且其热处理工艺在后面的制造阶段期间可有许多次，其可实施来达成各种目的，包含活化eSiGe层62中的原子锗物种以将锗定位至硅锗合金中的晶格点。
如上所述，因为eSiGe层62具有不同于沟道区域40的cSiGe层的组成，eSiGe及cSiGe层62及40类似地具有不同的对应晶格结构及晶格含量。发明人已发现到，通过在eSiGe层62中具有相对低总量的碳，减少及/或最小化且更佳地消除eSiGe及cSiGe层62及40间的差排，几乎不会影响通过应变诱导eSiGe层62而施加至沟道区域40的压缩应变组件64。
参照图4，提供依据例示性实施例的在进一步进阶制造阶段中的半导体装置10的示意性描绘。如图所示，可形成蚀刻屏蔽66(例如光阻屏蔽)，以覆盖晶体管26及eSiGe层62的上表面，而曝露晶体管24上方的间隔件层42。之后，可实施各向异性蚀刻工艺以蚀刻间隔件层42的曝露部份，据此形成侧壁间隔件68及曝露晶体管24的盖层34。
参照图5，提供依据例示性实施例的在进一步进阶制造阶段中的半导体装置10的示意性描绘。如图所示，可在晶体管24及26的侧壁间隔件68及44上形成牺牲氧化物间隔件70。举例而言，通过将氧化物层(例如二氧化硅)沉积在侧壁间隔件68及44上且接着各异向性地蚀刻氧化物层而形成牺牲氧化物间隔件70。牺牲氧化物间隔件70可作为用于在后续制造阶段期间移除盖层34的蚀刻屏蔽。
参照图6，依据一个或更多个例示性实施例而基于以下工艺来形成的半导体装置10。在形成如先前所述的eSiGe层62及牺牲氧化物间隔件70之后，可移除牺牲氧化物间隔件70、盖层34及氧化物层33，且可通过基于良好建立的技术的适当的植入工艺而继续进一步的处理。再者，可依据工艺及装置需求而进一步定义至少在植入顺序的各种制造阶段作为植入屏蔽的侧壁间隔件44及68以建立用于漏极及源极区域72的所需的纵向和横向掺质轮廓(profile)。此后，可实施一个或更多个退火工艺以活化掺质。接下来，举例而言，装置10可准备来沉积耐火金属(例如钴、镍、钛、钽、铂、钯、铑及其混合物)，其可基于良好建立的清洗方法而完成。之后，可沉积耐火金属的层且依序地实施一个或更多个热处理以初始化化学反应而形成金属硅化物74。应体认到，在此些后面的制造阶段期间，包含退火及热处理工艺期间，eSiGe层62中含有的碳内容物将作用来减少或消除eSiGe及cSiGe层62及40间的差排。
据此，已叙述半导体装置及用来制造半导体装置的方法。各种实施例包含半导体装置的制造的中间阶段的期间，在半导体区域中形成横向地邻接在晶体管的栅极电极结构的孔穴。栅极电极结构是设置在由沟道硅锗合金层(即cSiGe)所形成的沟道区域上。应变诱导硅锗合金层(即eSiGe)接着形成在孔穴中且与沟道区域接触。eSiGe层含有相对低总量的碳且其组成浓度与cSiGe层不同，据此，eSiGe及cSiGe层很可能具有不同的对应晶格结构及晶格内容物。已发现到eSiGe层中的相对低总量的碳减少或消除两个硅锗层间的因为其晶格结构及晶格内容物中的差异而发生的差排。再者，已发现到eSiGe层中的相对低总量的碳几乎不影响施加至沟道区域的压缩应变。因此，由于在沟道中eSiGe层产生的压缩应变，晶体管较佳地强化电荷载体沟道迁移率，又，由于eSiGe及cSiGe层间的差排的减少或消除，晶体管较佳地减少漏电流。
虽然已在前述实施方式中表达至少一个例示性实施例，应体认到存在着大量的变形。亦应体认到，例示性实施例仅是例子，而非意图以任何方式来限制本发明的范畴、适用性或结构。更确切地说，前述实施方式提供方便的路线图给本发明所属技术领域具有通常知识者来实施本发明的例示性实施例，其被认为在叙述于例示性实施例中的组件的功能及配置中可做出各种变化，而不背离定义于附加权利要求中的本发明的范畴及其等效。

Claims (20)

1.一种制造半导体装置的方法，包括：
在半导体区域中形成横向邻接在晶体管的栅极电极结构的孔穴，其中该栅极电极结构是设置在第一硅锗合金的沟道区域上；以及
在该孔穴中形成与该第一硅锗合金接触的应变诱导硅锗合金，该应变诱导硅锗合金包括碳且具有与该第一硅锗合金不同的组成。
2.根据权利要求1所述的方法，其中，形成该应变诱导硅锗合金包括形成具有从大约0.05至大约0.2原子百分比的碳含量的该应变诱导硅锗合金。
3.根据权利要求2所述的方法，其中，形成该应变诱导硅锗合金包括形成具有大约0.1原子百分比的碳含量的该应变诱导硅锗合金。
4.根据权利要求1所述的方法，其中，形成该应变诱导硅锗合金包括实施选择性外延生长工艺以在该孔穴中生长硅锗层。
5.根据权利要求4所述的方法，其中，形成该应变诱导硅锗合金包括于该外延生长工艺期间在原位置以碳掺杂该硅锗层而定义出该应变诱导硅锗合金。
6.根据权利要求4所述的方法，其中，形成该应变诱导硅锗合金进一步包括通过实施离子植入工艺以将该碳导入该硅锗层。
7.根据权利要求1所述的方法，其中，该第一硅锗合金具有第一锗浓度，且该应变诱导硅锗合金具有低于该第一锗浓度的第二锗浓度。
8.根据权利要求7所述的方法，其中，该第一锗浓度大约为28至32原子百分比。
9.根据权利要求7所述的方法，其中，该第二锗浓度大约为19至26原子百分比。
10.根据权利要求1所述的方法，进一步包括至少部分地在该应变诱导硅锗合金中形成漏极及源极区域。
11.根据权利要求10所述的方法，进一步包括在该应变诱导硅锗合金中及至少部分地在该漏极及源极区域中形成金属硅化物。
12.根据权利要求11所述的方法，其中，形成金属硅化物包括在该应变诱导硅锗合金的上表面上沉积金属及实施热处理以初始化该金属及在该应变诱导硅锗合金中的硅的化学反应，该金属是选自由钴、镍、钛、钽、铂、钯、铑及其混合物所组成的群组。
13.一种制造半导体装置的方法，包括：
在形成在P型晶体管的主动区域中的孔穴中形成应变诱导硅锗合金而使该应变诱导硅锗合金与定义出该P型晶体管的沟道区域的第一硅锗合金接触，该第一硅锗合金具有与包括碳的该应变诱导硅锗合金不同的组成；以及
至少部分地在该应变诱导硅锗合金中形成漏极及源极区域。
14.根据权利要求13所述的方法，其中，该应变诱导硅锗合金具有从大约0.05至大约0.2原子百分比的碳含量。
15.根据权利要求13所述的方法，进一步包括在该应变诱导硅锗合金中及至少部分地在该漏极及源极区域中形成金属硅化物，该金属硅化物是由选自由钴、镍、钛、钽、铂、钯、铑及其混合物所组成的群组的金属所形成。
16.根据权利要求13所述的方法，其中，形成该应变诱导硅锗合金包括实施选择性外延生长工艺以在该孔穴中生长硅锗层。
17.根据权利要求16所述的方法，其中，当由该外延生长工艺形成时以该碳掺杂该硅锗层而定义出该应变诱导硅锗合金。
18.根据权利要求16所述的方法，其中，形成该应变诱导硅锗合金进一步包括通过实施离子植入工艺以将该碳导入该硅锗层。
19.一种半导体装置，包括：
含硅半导体区域；
由形成在该含硅半导体区域中的第一硅锗合金所形成的沟道区域；
形成在该沟道区域上的栅极电极结构；
形成在该含硅半导体区域中邻接在该沟道区域的漏极及源极区域；
至少部分地形成在该漏极及源极区域中包括碳的应变诱导硅锗合金，该应变诱导硅锗合金与该第一硅锗合金接触且具有与该第一硅锗合金不同的组成；以及
形成在该应变诱导硅锗合金中及至少部分地在该漏极及源极区域中的金属硅化物。
20.根据权利要求19所述的装置，其中，该应变诱导硅锗合金具有从大约0.05至大约0.2原子百分比的碳含量。
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US20120153350A1 (en) 2012-06-21
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