CN102074461B - 半导体装置及其制造方法 - Google Patents

半导体装置及其制造方法 Download PDF

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CN102074461B
CN102074461B CN201010518047.9A CN201010518047A CN102074461B CN 102074461 B CN102074461 B CN 102074461B CN 201010518047 A CN201010518047 A CN 201010518047A CN 102074461 B CN102074461 B CN 102074461B
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crystal plane
groove
mentioned
plane direction
substrate
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CN102074461A (zh
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许俊豪
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

本发明提供一种半导体装置及其制造方法，上述半导体装置的制造方法包括提供一半导体基板；于上述半导体基板中形成一沟槽，其中上述沟槽的一底面具有一第一结晶面方向，且上述沟槽的一侧面具有一第二结晶面方向；进行一外延工艺，于上述沟槽中生长一半导体材料，其中上述外延工艺利用一蚀刻成分，且其中上述第一结晶面方向上的一第一生长速率不同于上述第二结晶面方向的一第二生长速率。本发明可改善元件性能。

Description

半导体装置及其制造方法
技术领域
本发明涉及一种半导体装置及其制造方法，特别涉及一种于基板沟槽中形成外延层的半导体装置及其制造方法。
背景技术
当例如一金属氧化物半导体场效应晶体管(以下简称MOSFET)的一半导体装置在历经许多工艺节点的尺寸微缩时，使用高介电常数(high-k)栅极介电层和金属栅极以形成栅极堆叠结构。可使用利用硅锗或碳化硅外延薄膜以增强载子迁移率。另外，沟道后置积集工艺(channel-last integration schemes)也会要求低镕化温度的例如砷化铟或锑化铟的三-五族高迁移率沟道材料，以避免形成源/漏极的高温度预算(high thermal budget)的影响。然而，形成这些应力结构和沟道后置晶体管的现行工艺无法在各方面令人满意。举例来说，硅的n型沟道应力结构被有问题的碳化硅薄膜限制且的p型沟道应力结构尚未找到解决方式。可以了解的是，利用公知外延生长工艺形成的沟道后置晶体管的外延层面临更多的挑战。
因此，在此技术领域中，有需要一种半导体装置及其制造方法，以克服公知技术的缺点。
发明内容
有鉴于此，本发明一实施例提供一种半导体装置的制造方法，上述半导体装置的制造方法包括提供一半导体基板；于上述半导体基板中形成一沟槽，其中上述沟槽的一底面具有一第一结晶面方向，且上述沟槽的一侧面具有一第二结晶面方向；进行一外延工艺，于上述沟槽中生长一半导体材料，其中上述外延工艺利用一蚀刻成分，且其中上述第一结晶面方向上的一第一生长速率不同于上述第二结晶面方向的一第二生长速率。
本发明另一实施例提供一种半导体装置，包括一半导体基板以及一晶体管；上述晶体管包括一栅极结构，设置于上述半导体基板上方以及具有一应力薄膜结构的源极和漏极应力物。
本发明又另一实施例提供一种半导体装置的制造方法，上述半导体装置的制造方法包括提供一半导体基板；于上述半导体基板中形成一沟槽，其中上述沟槽的一第一表面具有一第一结晶面方向，且上述沟槽的一第二表面具有一第二结晶面方向；进行一外延生长工艺，于上述沟槽中生长一半导体材料，其中上述外延生长工艺包含一蚀刻成分，且其中上述第一结晶面方向上的一第一生长速率不同于上述第二结晶面方向的一第二生长速率，以使上述蚀刻成分禁止于上述第一结晶面方向和上述第二结晶面方向上的其中之一生长。
本发明可改善元件性能。
附图说明
图1为依据本发明不同实施例的使用一由下而上生长工艺于一基板沟槽中形成一外延层的方法的流程图。
图2A至图2C为依据图1的方法形成的本发明一实施例的外延层的工艺剖面图。
图3为依据本发明不同实施例的具有应力结构的半导体装置的制造方法的流程图。
图4A至图4F为依据图3的半导体装置的制造方法形成的本发明一实施例的半导体装置的工艺剖面图。
图5A至图5D为本发明另一实施例的半导体装置的工艺剖面图。
其中，附图标记说明如下：
50、200～方法；
52、54、56、202、204、206、208、210、212～步骤；
202～半导体基板；
120～蚀刻成分；
104～沟槽；
106、422～底面；
108、424～侧面；
110～由下而上生长工艺；
300、400～半导体装置；
302～基板；
304、406～浅沟槽隔绝结构；
306～栅极介电质；
308～栅极；
310～硬掩模层；
314、314a～氧化层；
316、316a～氮化层；
320～图案化光致抗蚀剂层；
324、328、332、360、410～蚀刻工艺；
330、409～间隙壁；
340、420～凹陷；
342～深度；
350、430～外延工艺；
355、440～纯锗结晶结构；
357～底部；
359～压缩应力；
404～鳍状物；
408～栅极结构。
具体实施方式
以下以各实施例详细说明并伴随着附图说明的范例，做为本发明的参考依据。在附图或说明书描述中，相似或相同的部分皆使用相同的图号。且在附图中，实施例的形状或是厚度可扩大，并以简化或是方便标示。再者，附图中各元件的部分将以分别描述说明之，值得注意的是，图中未示出或描述的元件，为所属技术领域中普通技术人员所知的形式。
请参考图1，其显示依据本发明不同实施例的使用一由下而上生长工艺于一基板沟槽中形成一外延层的方法50的流程图。方法50起始于步骤52，提供一半导体基板。接着进行方法50的步骤54，于半导体基板中形成一沟槽，其中上述沟槽的一底面具有一第一结晶面方向，且上述沟槽的一侧面具有一第二结晶面方向。接着进行方法50的步骤56，使用一由下而上生长工艺(bottom-up growth process)，于上述沟槽中形成一外延层。上述由下而上生长工艺包括一外延生长工艺，其包含一蚀刻成分。上述第一结晶面方向上的一生长速率不同于上述第二结晶面方向的一生长速率。
请参考图2A至图2C，其显示依据图1的方法50形成的本发明一实施例的结晶结构的工艺剖面图。在一实施例中，于例如硅的基板沟槽中生长一晶体。上述晶体可与基板相同或不同。在不同实施例中，上述晶体可包括硅、硅锗、锗、碳化硅或其他适合的半导体材料。在图2A中，提供一半导体基板102，其包括结晶结构的一硅基板或其他半导体基板，例如锗或三-五族化合物半导体。在另一实施例中，半导体基板102可包括一外延(epi)层。可利用蚀刻工艺或其他适合工艺于半导体基板102中形成一沟槽104。沟槽104可包括具有一结晶面方向(例如[100])的一底面106和具有一结晶面方向(例如[110]或[111])的一侧面108。值得注意的是，上述特定的结晶面方向仅做为实施例，然而也可使用其他的结晶面方向。
在图2B中，可进行一由下而上生长工艺(bottom-up growth process)110，以于基板的沟槽104中生长一外延(epi)层。因此，上述下而上生长工艺可使用一或多个前驱物。在生长锗(Ge)外延层的实施例中，可使用气体流量介于5sccm至10sccm之间的GeH4和气体流量介于10sccm至30sccm之间的例如氯化氢(HCl)的蚀刻成分。在一些实施例中，蚀刻成分120可包括例如Cl2、BCl3、BiCl3或BiBr3的其他含氯气体或含溴气体。在其他实施例中，蚀刻成分120也可使用例如NF3或HF的含氟气体。然而，含氟气体可能会蚀刻浅沟槽隔绝氧化物和其他介电质(SiO2、SiN)硬掩模。于使外延(epi)层稳定生长的一温度下进行上述由下而上生长工艺110。在生长锗(Ge)外延层的实施例中，工艺温度可约介于450℃至550℃之间，且气体总压力介于20托尔(torr)至760托尔(torr)之间。应注意的是，例如氯化氢(HCl)的蚀刻成分对温度敏感且因此可调整温度以达成下述的想要的蚀刻效应。另外，可以了解的是，对不同类型的晶体材料的实施例可使用不同的条件范围。
由于例如硅的基板102的不同的结晶面方向，所以底面106的生长速率不同于侧面108的生长速率。在一实施例中，可以得知锗在[100]结晶面方向(底面106)上的生长速度比在[110]结晶面方向(侧面108)上的生长速度快三倍。另外，可预期锗在[111]结晶面方向上的生长速度比比在[110]结晶面方向上的生长速度慢。因此，包含蚀刻成分120的由下而上生长工艺110可通过防止锗于沟槽104的侧面108生长，以促进锗由下而上生长。举例来说，锗从沟槽104的底面106的生长速度高于从沟槽104的侧面108的生长速度。蚀刻成分120同时移除沉积于侧面108和底面106的锗。然而，因为锗从沟槽104的底面106的生长速度大于从沟槽104的侧面108的生长速度，所以净效应为锗会大体上由下而上生长。
在图2C中，持续进行由下而上生长工艺110直到外延层到达想要的厚度为止。值得注意的是，如果大体上基板和外延层之间的晶格不匹配程度大时，在底部会有一些错位缺陷。因此，因为基板和外延层之间的晶格不匹配，在沟槽的底部130的外延层结晶的一部分会包括错位缺陷。在硅沟槽中生长锗为一常见的实施例。然而，在一些其他实施例中，当基板和外延层之间的晶格不匹配程度小时，例如在锗沟槽中生长砷化锗，在底部不会有错位缺陷。
另外，位于像锗结晶的具有晶格不匹配程度大的外延层之处的底部130上方的上部140，其大体上没有错位缺陷。此外，可以了解的是，因为通过蚀刻成分120禁止晶格不匹配程度大的外延层于侧面生长，所以侧面108不会表现出错位缺陷。因此，由下而上生长工艺110会捕捉错位缺陷，如果沟槽的底部130有任何的错位缺陷的话，且可在例如硅沟槽的基板上部140形成例如锗结构的一大体上无错位缺陷的纯单晶体。因此，因为锗结晶的无缺陷外延层具有比基板或晶体管沟道大或小的晶格常数，上述基板或晶体管沟道具有或不具有一理想的压缩或拉伸应力，所以像锗结晶的无缺陷外延层可用做为基板102中的一压缩或拉伸应力的压力源。
虽然上述使用的纯锗晶体仅为一实施例，也可应用由下而上生长工艺来生长其他类型晶体结构，例如用于N型金属氧化物半导体晶体管(NMOS)元件压力源的碳化硅(SiC)、或可于硅或锗沟槽中生长例如砷化镓(GaAs)或锑化铟(InSb)的三-五族化合物半导体以做为沟道材料。就生长碳化硅(SiC)而言，蚀刻成分可相同于用于生长锗的蚀刻成分。就生长三-五族化合物半导体而言，蚀刻成分可包括包括含氯气体或含溴气体。
另外，可以了解的是，可调整其他工艺参数以调整于不同结晶面上的生长速率。举例来说，温度、压力、蚀刻气体流量、乘载气体流量、沉积气体流量或上述组合可用以调整生长速率。此外，由下而上生长工艺可与例如互补式金属氧化物半导体晶体管(CMOS)的现行工艺完全相容且可易于与例如互补式金属氧化物半导体晶体管(CMOS)的现行工艺结合。
请参考图3，其显示依据本发明不同实施例的制造半导体装置的方法200的流程图。方法200起始于步骤202，提供一半导体基板。接着进行方法200的步骤204，于上述半导体基板上形成一栅极结构。接着进行方法200的步骤206，分别于上述栅极结构的侧壁上形成间隙壁。接着进行方法200的步骤208，于上述栅极结构的每一侧的基板中形成一凹陷。接着进行方法200的步骤210，利用由下而上生长工艺和蚀刻成分，外延生长一半导体材料以填充上述凹陷。接着进行方法200的步骤212，半导体装置制造完成。后续描述显示依据图3的方法200制造本发明不同实施例的半导体装置。
图4A至图4F为依据图3的半导体装置的制造方法200形成的本发明一实施例的半导体装置300的工艺剖面图。可以了解的是，为了清楚且易于了解本实施例的发明概念，简化图4A至图4F。在图4A中，半导体装置300可包括一基板302。基板302可包括一硅基板。在另一实施例中，基板302可包括一外延层。举例来说，基板302可包括位于一块状半导体上的一外延层。基板302可更包括例如p型井或n型井的掺杂区。此外，基板302可包括例如一埋藏介电层的绝缘层上覆硅(SOI)结构。在其他实施例中，基板302可包括例如埋藏一氧化层(BOX)的埋藏介电层，其可利用包括例如氧注入隔离法(SIMOX)、晶片接合(wafer bonding)、选择外延生长法(SEG)或其他适当方法的一方法形成。半导体装置300可包括定义于基板302中的有源区。
为了隔绝不同的有源区，可于半导体基板中形成多个浅沟槽隔绝结构(STI)304。形成上述浅沟槽隔绝结构(STI)304的方式包括于基板中蚀刻一沟槽，利用例如氧化硅、氮化硅或氮氧化硅的绝缘材料填充上述沟槽。填充后的上述沟槽可为例如一热氧化衬垫层和填充沟槽的氮化硅的一多层结构。在一实施例中，可利用一工艺依序形成浅沟槽隔绝结构(STI)304，例如：生长一垫氧化物、形成一低压化学气相沉积(LPCVD)氮化层、利用光致抗蚀剂和掩模图案化一浅沟槽隔绝结构开口、于基板中蚀刻一沟槽、选择性生长一热氧化沟槽衬垫物以改善沟槽的介面、利用化学气相沉积(CVD)氧化物填充上述沟槽、利用化学机械研磨平坦化工艺以回蚀刻上述化学气相沉积(CVD)氧化物，且利用氮化物剥除法(nitride stripping)以留下浅沟槽隔绝结构(STI)。
可于有源区中形成一个或多个操作元件。上述操作元件可包括n型和p型金属氧化物半导体场效应晶体管(以下简称为NMOS和PMOS元件)。可由NMOS和PMOS元件构成上述操作元件。可利用CMOS工艺形成上述NMOS和PMOS元件。另外，可以了解的是，可于图3的方法200之前、之中或之后提供额外的步骤，且可仅于说明书中简洁地描述其他工艺。每一个NMOS和PMOS元件可包括形成于半导体基板302上的一栅极结构。上述栅极结构可包括一栅极介电质306和一栅极308。上述栅极介电质306可包括氧化硅、氮化硅、高介电常数(high k)介电材料或其他适合的材料。上述高介电常数介电层可包括例如HfOx的二元或三元高介常数材料薄膜。在其他实施例中，上述高介电常数介电层可选择性包括例如LaO、AlO、ZrO、TiO、Ta2O5、Y2O3、SrTiO3(STO)、BaTiO3(BTO)、BaZrO、HfZrO、HfLaO、HfSiO、LaSiO、AlSiO、HfTaO、HfTiO、(Ba，Sr)TiO3(BST)、Al2O3、Si3N4、氮氧化硅或其他适当材料的其他高介电常数介电材料。可利用原子层沉积(ALD)法、化学气相沉积(CVD)法、物理气相沉积(PVD)法、热氧化法、紫外线臭氧氧化法或上述方式组合形成上述栅极介电质。
上述栅极308可包括多晶硅层。举例来说，可使用硅烷(SiH4)做为化学气相沉积(CVD)工艺中一化学气体，以形成多晶硅层。上述多晶硅层的厚度可介于
Figure BSA00000316715400071
至
Figure BSA00000316715400072
之间。上述栅极可更包括一硬掩模层310，形成于栅极308上。上述硬掩模层可包括氧化硅。在其他实施例中，上述硬掩模层可选择性包括氮化硅、氮氧化硅、碳化硅及/或其他适合的介电材料，且可利用例如物理气相沉积(PVD)法或化学气相沉积(CVD)法的方法形成上述硬掩模层。上述硬掩模层310的厚度可介于
Figure BSA00000316715400073
至
Figure BSA00000316715400074
之间。
半导体装置300可包括形成于栅极结构的每一个侧面上的偏移间隙壁(offset spacer)312。上述偏移间隙壁312可包括氮化硅或氮化硅。可利用化学气相沉积(CVD)法、物理气相沉积(PVD)法、原子层沉积(ALD)法、等离子体增强型化学气相沉积(PECVD)法或其他适合工艺形成上述偏移间隙壁312。可进行一注入工艺以于基板302中形成轻掺杂源/漏极(LDD)区(图未显示)。对PMOS元件而言，上述注入工艺可使用p型掺质(例如硼或铟)，且对NMOS元件而言，上述注入工艺可使用n型掺质(例如磷或砷)。
半导体装置300可更包括形成于基板302和栅极结构上方的一氧化层314。可利用化学气相沉积(CVD)法、原子层沉积(ALD)法、物理气相沉积(PVD)法或其他适合工艺形成上述氧化层314。氧化层314的厚度可介于2nm至2nm之间。半导体装置300可更包括形成氧化层314上方的氮化层316。可利用化学气相沉积(CVD)法、原子层沉积(ALD)法、物理气相沉积(PVD)法或其他适合工艺形成上述氮化层316。氮化层316的厚度可介于10nm至15nm之间。可蚀刻氧化层314和氮化层316以形成间隙壁，其用以形成如下所述的源极和漏极应力物。因此，氧化层314和氮化层316的厚度取决于源极和漏极应力物与PMOS元件的一沟道区相隔的距离。
形成一图案化光致抗蚀剂层320以保护NMOS元件。一实施例的光刻工艺可包括光致抗蚀剂涂布、软烤、掩模对准、曝光、曝光后烘烤、光致抗蚀剂显影和硬烤的工艺步骤。可更利用其他适合工艺进行上述光刻曝光工艺或以其他适合工艺取代上述光刻曝光工艺，上述其他适合工艺例如为无光掩模光刻工艺、电子束写入工艺、离子束写入工艺或分子拓印工艺(molecularimprint)。
在图4B中，可进行一蚀刻工艺324，以移除位于基板302正上方的部分氮化层316。在本实施例中，蚀刻工艺324可包括使用CHxFy/O2 orSF6/CHxFy/He(其中x＝1至3，且y＝4-x)的一气体组合或其他气体组合的一干蚀刻工艺。上述干蚀刻工艺提供方向性蚀刻(例如异向性蚀刻)，以使氮化层316a的一些部分在进行蚀刻工艺324之后残留于栅极结构的侧壁上。
在图4C中，进行一蚀刻工艺328，以移除位于基板302正上方的氧化层314。在本实施例中，蚀刻工艺328可包括使用CF4/Cl2/HBr/He的一气体组合或其他气体组合的一干蚀刻工艺。因此，进行蚀刻工艺328之后，残留于PMOS元件的栅极结构的侧壁上的一部分氧化层314a氮化层316a因而形成间隙壁330。
在图4D中，进行一蚀刻工艺332，以于基板302中蚀刻一凹陷340。蚀刻工艺332可包括使用HBr/Cl2/O2/He的一气体组合的一干蚀刻工艺，且气体压力可约介于1mT至1000mT之间，功率可介于50W至1000W之间，偏压介于100V至500V之间，且HBr的气体流量可介于10sccm至500sccm之间，Cl2的气体流量可介于0sccm至500sccm之间，O2的气体流量可介于0sccm至100sccm之间，且He的气体流量可介于0sccm至1000sccm之间。上述干蚀刻工艺移除未被保护或暴露出来的一部分基板302。因为方向性蚀刻/异向性蚀刻，因此凹陷340具有垂直的侧壁且对齐于间隙壁330。上述凹陷340可具有一深度342，其可介于
Figure BSA00000316715400091
至
Figure BSA00000316715400092
之间。
在图4E中，进行一外延工艺350，以于凹陷340中沉积一半导体材料。于进行外延工艺350之前移除保护NMOS元件的图案化光致抗蚀剂层320。可使用氢氟酸(HF)或其他适当溶液进行一预清洁工艺，以清洁凹陷340。在本实施例中，外延工艺350类似于如图2A至图2C所述的由下而上生长工艺110。因此，于凹陷340中生长一纯锗结晶结构355，以形成源极和漏极应力物。可以了解的是，有一些错位缺陷会被纯锗结晶结构355的底部357，然而这些错位缺陷应该不会反过来影响PMOS元件的性能。另外，在一些实施例中，可沉积纯锗结晶结构355，以使其凸起于基板302的表面一距离。
如前所述，用于源极和漏极应力物的现行硅锗结构被其可产生应力的数量限制。硅锗结构中的锗浓度决定可产生应力的数量，且因此增加上述锗浓度将会增加应力的大小。然而，只能增加上述锗浓度到一定程度，以达到应力硅锗结构的足够结晶厚度。在此，在本实施例中，可形成无缺陷的纯锗结晶结构，以做为源极和漏极应力物或高迁移率沟道。就其本身而论，纯锗结晶结构355会产生一明显数量的压缩应力(例如4GPa或大于4GPa)359，以增强空穴迁移率且改善位于硅或硅锗基板上的PMOS元件性能。因此，因为锗源极和漏极应力物本身会提供大于4GPa的压缩沟道应力以达到最大的硅空穴迁移率，所以不再需要例如接触蚀刻停止层(CESL)的其他类型应力物。在本实施例中，外延工艺350可以原位掺杂(in-situ doped)锗和例如硼或铟的p型掺质，以形成PMOS元件的源极和漏极区。
在图4F中，进行一蚀刻工艺360，以移除NMOS元件上的氮化层316和PMOS元件上的氮化层316a。上述蚀刻工艺360包含用磷酸(H3PO4)或其他适当蚀刻剂的湿蚀刻工艺。可选择上述湿蚀刻工艺，以达到慢的蚀刻速率，以保护多晶硅。接着进行以下简述工艺以完成半导体装置300的制造方法。举例来说，利用例如磷或砷的n型离子注入工艺以形成NMOS元件的源/漏极区。在另一实施例中，可利用上述由下而上生长工艺，于硅基板沟槽中沉积碳化硅(SiC)，以形成NMOS元件的源/漏极区。另外，可于凸起的源/漏极物上形成硅化物，以降低接触电阻。可利用包括沉积一金属层、将上述金属层退火使能够与硅反应以形成硅化物且移除未反应的金属层的一工艺，于源/漏极上形成硅化物。
可于基板上形成一层间介电质(ILD)，再对基板进行一化学机械研磨(CMP)工艺以平坦化基板。在一实施例中，在最终装置中，栅极308残留有多晶硅。在另一实施例中，在栅极后置工艺(gate last process)或栅极取代工艺(gate replacement process)中，移除多晶硅且以一金属取代在栅极后置工艺(gate last process)中，持续层间介电层(ILD layer)上的化学机械研磨(CMP)工艺直到暴露出多晶硅表面，且进行一蚀刻工艺以移除多晶硅因而形成沟槽。以一适当功函数材料(例如p型功函数材料或n型功函数材料)上述填充在PMOS和NMOS元件中的上述沟槽。于基板上形成一多层内连线(MLI)以电性连接不同元件以形成一集成电路。上述多层内连线(MLI)包括例如常用的介层孔或接触插塞的垂直内连线，和例如金属线的水平内连线。可用包括铜、钨和硅化物的各种导电材料形成上述各种内连线。在一实施例中，可使用镶嵌工艺以形成铜内连线结构。
请参考图5A至图5D，其为本发明另一实施例的半导体装置400的工艺剖面图。半导体装置400包括鳍状场效应晶体管(FinFET)元件。可以了解的是，为了清楚且更了解本实施例的发明概念，简化图5A至图5D，且一些常用的元件和工艺在此不做叙述。在图5A中，半导体装置400可包括一基板(图未显示)。基板可包括结晶硅。半导体装置400可包括从基板延伸的多个鳍状物404。虽然附图中只显示一个鳍状物，但可以了解的是，可依特定实施例改变鳍状物的数量。鳍状物404可包括硅。可利用例如光刻工艺和蚀刻工艺的适当工艺形成鳍状物404。举例来说，上述光刻工艺可包括于基板上形成一光致抗蚀剂层、将上述光致抗蚀剂层曝光以成为一图案、进行曝光后烘烤工艺、且将光致抗蚀剂显影以形成包括光致抗蚀剂的一掩模元件。然后使用上述掩模元件以从上述基板蚀刻上述鳍状物404。可利用反应式离子蚀刻法(RIE)及/或其他适当工艺蚀刻上述鳍状物404。浅沟槽隔绝(STI)结构406围绕上述鳍状物404且将每一个鳍状物与其他鳍状物彼此隔绝。浅沟槽隔绝(STI)结构406可包括任何适当绝缘材料。
在其他实施例中，基板可包括一绝缘层上覆硅(SOI)基板。可利用氧注入隔离法(SIMOX)、晶片接合(wafer bonding)及/或其他适当工艺形成上述绝缘层上覆硅(SOI)基板。硅层可包括一绝缘层上覆硅(SOI)基板上的一硅层(例如位于一绝缘层上)。举例来说，可利用蚀刻基板上的一硅层形成上述鳍状物。
半导体装置400包括形成于部分上述鳍状物404上方的多重栅极结构408。栅极结构408包覆环绕上述鳍状物404，以允许形成于上述鳍状物两侧边的沟道的栅极控制。栅极结构408可包括类似于图4A所述的一栅极介电质、一栅极和一硬掩模。可于栅极结构408的侧壁上形成间隙壁409。
在图5B中，进行一蚀刻工艺410，以移除鳍状物404的暴露部分。在本实施例中，蚀刻工艺410类似于图4D所述的蚀刻工艺332。因此，进行蚀刻工艺410之后，形成一凹陷420。凹陷420可具有具有一第一结晶面方向(例如[100])的一底面422，和具有一第二结晶面方向(例如[110])的一侧面424。可以了解的是，浅沟槽隔绝(STI)结构406形成于凹陷420的其他侧面。
在图5C中，进行一外延工艺430，以于凹陷420中沉积一半导体材料。在本实施例中，外延工艺430类似于图2A至图2C所述的由下而上生长工艺110。锗在第一结晶面方向(底面422)上的生长速度大于在第二结晶面方向(侧面424)上的生长速度。如上所述，在外延工艺430期间，蚀刻成分控制和禁止侧面424上的生长。此外，蚀刻成分可移除可能沉积于浅沟槽隔绝(STI)结构406侧面的锗。因此，于凹陷420中大体上由下而上生长一纯锗结晶结构440。持续由下而上生长工艺往上生长至浅沟槽隔绝(STI)结构406的表面。在图5D中，持续由下而上生长工艺至超过浅沟槽隔绝(STI)结构406的表面，且完成形成具有一理想高度的纯锗结晶结构440。锗源极和漏极应力物的纯锗结晶结构440增强空穴迁移率，上述空穴迁移率改善元件性能。
虽然本发明已以实施例公开如上，然其并非用以限定本发明，任何本领域普通技术人员，在不脱离本发明的精神和范围内，当可作些许的更动与润饰，因此本发明的保护范围当视随附的权利要求所界定的保护范围为准。

Claims (6)

1.一种半导体装置的制造方法，包括下列步骤：
提供一半导体基板；
于该半导体基板中形成一沟槽，其中该沟槽的一底面具有一第一结晶面方向，且该沟槽的一侧面具有一第二结晶面方向；以及
进行一外延工艺，于该沟槽中生长一半导体材料，其中该外延工艺利用一蚀刻成分，且其中该第一结晶面方向上的一第一生长速率不同于该第二结晶面方向的一第二生长速率，其中在该外延工艺期间，该蚀刻成分禁止于该第二结晶面方向上的生长，以在该沟槽的该底面上方的一上部形成无错位缺陷的一纯单晶体，且该纯单晶体具有比基板或晶体管沟道大或小的晶格常数。
2.如权利要求1所述的半导体装置的制造方法，其中该半导体材料包括硅或锗的其中之一，且其中该半导体基板包括硅或锗的其中之一。
3.如权利要求1所述的半导体装置的制造方法，其中该蚀刻成分包括含氯气体或含溴气体的其中之一。
4.如权利要求1所述的半导体装置的制造方法，其中该第一结晶面方向包括[100]，且其中该第二结晶面方向包括[110]或[111]的其中之一。
5.如权利要求1所述的半导体装置的制造方法，其中该第一生长速率大于该第二生长速率。
6.一种半导体装置的制造方法，包括下列步骤：
提供一半导体基板；
于该半导体基板中形成一沟槽，其中该沟槽的一第一表面具有一第一结晶面方向，且该沟槽的一第二表面具有一第二结晶面方向；以及
进行一外延生长工艺，于该沟槽中生长一半导体材料，其中该外延生长工艺包含一蚀刻成分，且其中该第一结晶面方向上的一第一生长速率不同于该第二结晶面方向的一第二生长速率，其中在该外延工艺期间，该蚀刻成分禁止于该第二结晶面方向上生长，以在该沟槽的该第一表面上方的一上部形成无错位缺陷的一纯单晶体，且该纯单晶体具有比基板或晶体管沟道大或小的晶格常数。
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