CN104752504B - 半导体器件结构及其制造方法 - Google Patents
半导体器件结构及其制造方法 Download PDFInfo
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- CN104752504B CN104752504B CN201410332365.4A CN201410332365A CN104752504B CN 104752504 B CN104752504 B CN 104752504B CN 201410332365 A CN201410332365 A CN 201410332365A CN 104752504 B CN104752504 B CN 104752504B
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- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/22—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
- H01L21/225—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities using diffusion into or out of a solid from or into a solid phase, e.g. a doped oxide layer
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- H01L21/2252—Diffusion into or out of group IV semiconductors using predeposition of impurities into the semiconductor surface, e.g. from a gaseous phase
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- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
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- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
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- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
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- H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
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- H01L29/1075—Substrate region of field-effect devices of field-effect transistors
- H01L29/1079—Substrate region of field-effect devices of field-effect transistors with insulated gate
- H01L29/1083—Substrate region of field-effect devices of field-effect transistors with insulated gate with an inactive supplementary region, e.g. for preventing punch-through, improving capacity effect or leakage current
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Abstract
本发明提供了半导体器件及其形成方法。本发明提供了用于形成半导体器件结构的实施例。该半导体器件结构包括衬底和形成在衬底上的栅叠层结构。该半导体器件结构还包括形成在栅叠层结构的侧壁上的栅极间隔件。该半导体器件结构还包括形成在衬底中的隔离结构和邻近隔离结构形成的源极/漏极应激源结构。源极/漏极应激源结构包括沿着(311)和(111)晶体取向形成的覆盖层。
Description
技术领域
本发明一般地涉及半导体技术领域,更具体地,涉及半导体器件及其形成方法。
背景技术
半导体器件用于各种电子应用中,诸如个人计算机、手机、数码相机和其他电子设备。通常通过工艺步骤来制造半导体器件:在半导体衬底上方顺序沉积绝缘或介电层、导电层和半导体材料层,以及使用光刻图案化各个材料层以在其上形成电路部件和元件。通常在单个半导体晶圆上制造多个集成电路,并且通过沿着划线在集成电路之间进行切割来分割晶圆上的独立管芯。例如,独立管芯通常分别封装在多芯片模块或其他类型的封装件中。
半导体工业通过持续减小最小部件尺寸来不断地改进各个电子部件(例如,晶体管、二极管、电阻器、电容器等)的集成密度,从而允许更多的部件集成到给定区域中。在一些应用中,这些较小的电子部件还需要利用比以往的封装件更小面积的较小封装件。
通常形成具有应激源区的MOSFET以增强MOSFET的性能。已实现了针对源极和漏极部件的形状、配置和材料的各种技术以进一步提高晶体管器件性能。尽管现有方法足以满足其预期目的,但它们并非在所有方面都完全符合要求。
发明内容
为了解决现有技术中所存在的缺陷,根据本发明的一方面,提供了一种半导体器件结构,包括:衬底;栅叠层结构,形成在所述衬底上;栅极间隔件,形成在所述栅叠层结构的侧壁上;隔离结构,形成在所述衬底中;以及源极/漏极应激源结构,形成为邻近所述隔离结构,其中,所述源极/漏极应激源结构包括沿着(311)晶体取向和(111)晶体取向形成的覆盖层。
在该半导体器件结构中,所述源极/漏极应激源结构进一步包括:形成在所述衬底和所述覆盖层之间的应激源层。
在该半导体器件结构中,所述覆盖层包括SiGe、Si、SiC或SiGeSn。
在该半导体器件结构中,所述覆盖层的一部分位于所述衬底的顶面之下。
在该半导体器件结构中,所述应激源层的一部分沿着所述(311)晶体取向和所述(111)晶体取向生长。
在该半导体器件结构中,所述覆盖层的厚度在约10nm至约30nm的范围内。
在该半导体器件结构中,所述半导体器件结构位于晶圆的边缘区处。
该半导体器件结构进一步包括:形成在所述源极/漏极应激源结构上的金属硅化物层。
该半导体器件结构进一步包括:形成在所述金属硅化物层上的接触件结构,其中,所述源极/漏极应激源结构通过所述金属硅化物层连接至所述接触件结构。
根据本方面的又一方面,提供了一种半导体器件结构,包括:衬底;栅叠层结构,形成在所述衬底上;栅极间隔件,形成在所述栅叠层结构的侧壁上;掺杂区,形成在所述衬底中;隔离结构,形成在所述衬底中;以及源极/漏极应激源结构,形成在所述掺杂区和所述隔离结构之间,其中,所述源极/漏极应激源结构包括:形成在所述衬底中的应激源层;以及形成在所述应激源层之上的覆盖层,并且所述覆盖层从所述掺杂区至所述隔离结构向下倾斜。
在该半导体器件结构中,第一刻面具有第一厚度,而第二刻面具有第二厚度,并且所述第一厚度基本上等于所述第二厚度。
在该半导体器件结构中,所述覆盖层的一部分位于所述衬底的顶面之下。
在该半导体器件结构中,所述应激源层和所述覆盖层之间的边界沿着(311)晶体取向和(111)晶体取向生长。
根据本发明的又一方面,提供了一种用于形成半导体器件结构的方法,包括:提供晶圆,所述晶圆具有中心部分和边缘部分;在所述中心部分和所述边缘部分上形成半导体器件结构,在所述中心部分和所述边缘部分上形成所述半导体器件结构包括:在所述晶圆的所述边缘部分中形成隔离结构;在所述晶圆的所述边缘部分上形成栅叠层结构;在所述栅叠层结构的侧壁上形成栅极间隔件;掺杂所述栅极间隔件下方的所述晶圆以形成掺杂区;以及在所述掺杂区和所述隔离结构之间生长源极/漏极应激源结构,所述源极/漏极应激源结构包括沿着所述(311)晶体取向和所述(111)晶体取向形成的覆盖层。
在该方法中,生长所述源极/漏极应激源结构包括:蚀刻所述晶圆以在所述晶圆中形成凹槽;在所述凹槽中生长应激源层;以及在所述应激源层上生长覆盖层。
在该方法中,在所述凹槽中生长所述应激源层包括:通过选择性外延工艺在所述凹槽中生长SiGe应激源层。
在该方法中,控制所述选择性外延工艺以满足方程式(I):边缘-E/D=HCl源的流速/Si源和Ge源的流速的总和---(I),其中,所述边缘-E/D在约0.2至约0.8的范围内。
在该方法中,所述Si源和所述Ge源的流速的总和在约100sccm至约400sccm的范围内。
在该方法中,在约500℃至约850℃的范围内的温度以及约1托至约760托的范围内的压力的条件下,实施所述选择性外延工艺。
在该方法中,在所述应激源层上形成所述覆盖层包括:在所述应激源层上沿着所述(311)晶体取向和所述(111)晶体取向形成所述覆盖层。
附图说明
为了更加完全地理解本发明及其优势,现在将结合附图所进行的以下描述作为参考。
图1A至图1E示出根据本发明的一些实施例形成半导体器件结构的各个阶段的截面图。
图2示出了根据本发明的一些实施例处于外延工艺期间的晶圆的俯视图。
具体实施方式
下面详细讨论本发明的各个实施例的制造和使用。然而,应该理解,可以在各种具体环境中实现各个实施例。所讨论的具体实施例仅是说明性的,而不限制本发明的范围。
应该理解,为实施本发明的不同部件,以下公开内容提供了许多不同的实施例或示例。以下描述元件和布置的特定示例以简化本发明。当然,这些仅仅是实例而不旨在限制。此外,在以下描述中,在第二工艺之前实施第一工艺可包括在第一工艺之后立即实施第二工艺的实施例,并且也可以包括在第一工艺和第二工艺之间可以实施额外的工艺的实施例。为了简单和清楚起见,可以以不同的比例任意地绘制各个部件。此外,在描述中,在第二部件上方或者上形成第一部件可以包括以直接接触或间接接触的方式形成第一部件和第二部件的实施例。
描述了实施例的一些变型例。在各个视图和整个说明性实施例中,相同参考标号用于标示相同的元件。应该理解,对于该方法的其他实施例,在该方法之前、期间和之后可以提供额外的操作,并且可以替换或删除一些描述的操作。
提供了形成半导体器件结构的实施例。图1A至图1E示出了根据本发明的一些实施例形成半导体器件结构100的各个阶段的截面图。
参照图1A,提供了衬底102。衬底102可由硅或其他半导体材料制成。可选地或另外地,衬底102可包括诸如锗的其他元素半导体材料。在一些实施例中,衬底102由诸如碳化硅、砷化镓、砷化铟或磷化铟的化合物半导体制成。在一些实施例中,衬底102由诸如硅锗、碳化硅锗、砷磷化镓或磷化铟镓的合金半导体制成。在一些实施例中,衬底102包括外延层。例如,衬底102具有位于块状半导体上方的外延层。
衬底102还可包括诸如浅沟道隔离(STI)部件或局部硅氧化(LOCOS)部件的隔离结构104。隔离结构104可限定并隔离各个集成电路器件。
如图1A所示,包括栅极介电层112和栅电极层114的栅叠层结构110形成在衬底102上。
栅极介电层112形成在衬底102上。栅极介电层112可由氧化硅、氮氧化硅或高介电常数材料(高k材料)制成。高介电常数材料可包括二氧化铪(HfO2)、氧化铪硅(HfSiO)、氮氧化铪硅(HfSiON)、氧化铪钽(HfTaO)、氧化铪钛(HfTiO)、氧化铪锆(HfZrO)或其他合适的高k介电材料。高k材料还可包括金属氧化物、金属氮化物、金属硅酸盐、过渡金属氧化物、过渡金属氮化物、过渡金属硅酸盐、金属氮氧化物、金属铝酸盐、硅酸锆、铝酸锆、氧化硅、氮化硅、氮氧化硅、氧化锆、氧化钛、氧化铝、二氧化铪-氧化铝(HfO2—Al2O3)合金或其他合适的材料。栅极介电层112可通过任何合适的工艺形成,诸如原子层沉积(ALD)、化学汽相沉积(CVD)、物理汽相沉积(PVD)、远程等离子体CVD(RPCVD)、等离子体增强的CVD(PECVD)、有机金属CVD(MOCVD)、溅射、电镀或其他合适的工艺。
此后,在栅极介电层112上形成由诸如多晶硅、金属或金属硅化物的材料所制成的栅电极层114。在一些实施例中,栅电极层114由用作伪栅极的多晶硅层制成,伪栅极在随后的栅极替换工艺中被替换。在一些实施例中,使用CVD工艺形成栅电极层114。
栅极间隔件116形成在栅叠层结构110的相对侧壁上。在一些实施例中,在半导体衬底102上方沉积介电层,并实施蚀刻工艺去除介电层的一部分以形成栅极间隔件116。栅极间隔件116由氧化硅、氮化硅、氮氧化硅和/或介电材料制成。栅极间隔件116可包括一层或多层。
此外,在衬底102上形成另一栅叠层结构150。栅叠层结构150包括栅极介电层152和栅电极层154。在栅叠层结构150的侧壁上形成栅极间隔件156。
根据本发明的一些实施例,如图1A所示,在形成栅极间隔件116和156之后,在半导体衬底102中形成掺杂区122、162。掺杂区122、162与栅极间隔件116、156的内侧对准。在一些实施例中,掺杂区122、162掺杂有诸如砷(As)、磷(P)或锑(Sb)的n型掺杂剂。在一些其他实施例中,掺杂区122、162掺杂有诸如硼(B)或二氟化硼(BF2)的p型掺杂剂。在一些实施例中,掺杂区122、162掺杂有浓度在约1×1012atom/cm2至约1×1015atom/cm2的范围内的砷(As)。掺杂区122、162具有梯度掺杂剂浓度,并且掺杂剂浓度从掺杂区122、162的内侧向外侧减小。
在一些实施例中,实施离子注入(IMP)工艺(未示出)以形成掺杂区122、162。在一些实施例中,在约10keV至约80keV的范围内的能量的条件下进行离子注入(IMP)工艺。
此后,根据本发明的一些实施例,如图1A所示,实施干法蚀刻工艺(未示出)以去除半导体衬底102的部分并形成凹槽130和130’。在一些实施例中,干法蚀刻工艺包括等离子体蚀刻工艺。凹槽130形成在栅叠层结构110和隔离结构104之间,并且凹槽130’形成在栅叠层结构110和栅叠层结构150之间。
在一些实施例中,用于干法蚀刻工艺的蚀刻气体包括氦气(He)、氩气(Ar)、氯气(Cl2)、氧气(O2)、HBr、N2、CF4和CH3F。在一些实施例中,氯气(Cl2)与氦气(He)的比率介于约0.1至约10的范围内。
如图1A所示,凹槽130、130’具有圆角形状。在一些实施例中,凹槽130的深度X1在约50nm至约90nm的范围内。
在一些实施例中,在干法蚀刻工艺之后实施湿法蚀刻工艺(未示出)以扩大凹槽130,从而形成扩大的凹槽(未示出)。在一些实施例中,湿法蚀刻工艺包括蚀刻溶液,该蚀刻溶液包括TMAH(四甲基氢氧化铵)、NH4OH、KOH(氢氧化钾)、HF(氢氟酸)或其他适用的蚀刻溶液。
根据本发明的一些实施例,如图1B所示,在形成凹槽130和130’之后,在凹槽130中形成应激源层142。应激源层142使半导体器件100的沟道区产生应变。对于n型MOS(NMOS)器件,应激源层142使沟道区产生拉伸应变。对于p型MOS(PMOS)器件,应激源层142使沟道区产生压缩应变。
如图1B所示,应激源层142具有五边形形状。在一些实施例中,应激源层142具有第一刻面142A、第二刻面142B、第三刻面142C、第四刻面142D和第五刻面142E。此外,在凹槽130’中形成应激源层172,并且该应激源层172也具有五边形形状。
在一些实施例中,应激源层142和172由SiGe制成。在一些实施例中,通过外延生长或外延(epi)工艺形成应激源层142。该epi工艺可包括选择性外延生长(SEG)工艺、CVD沉积技术(例如,汽相外延生长(VPE)和/或超高真空CVD(UHV-CVD))、分子束外延或其他合适的epi工艺。该epi工艺可使用气体前体和/或液体前体,其可与半导体衬底102的合成物相互作用。
应该注意,由氧化物制成的隔离结构104的表面自由能(surface free energy)高于由硅制成的衬底102的表面自由能。为了平衡隔离结构104的表面自由能,邻近隔离结构104的应激源层142具有密堆积结构(close-packed structure)。在一些实施例中,应激源层142沿着(311)和(111)晶体取向生长。例如,沿着(311)晶体取向生长第一刻面142A,并且沿着(111)晶体取向生长第二刻面142B。
在一些实施例中,在栅叠层结构110和栅叠层结构150之间形成应激源层172。与应激源层142相比,应激源层172更远离隔离结构104,并因此应激源层172成形为不具有密堆积结构。在一些实施例中,应激源层172沿着(111)和(100)晶体取向生长。
根据本发明的一些实施例,如图1C所示,在形成应激源层142之后,在应激源层142上形成覆盖层144。覆盖层144设置为降低应激源层142的薄层电阻以提供优越的接触特性。由应激源层142和覆盖层144构造源极/漏极应激源结构140。
覆盖层144是含硅层。在一些实施例中,覆盖层144由SiGe、Si、SiC或SiGeSn制成。覆盖层144中位于应激源层142上方的部分上升至衬底102的顶面之上。覆盖层144中位于应激源层142上方的一部分位于衬底102的顶面之下。覆盖层144还沿着(311)和(111)晶体取向生长。例如,覆盖层144具有第一刻面144A和第二刻面144B。沿着(311)晶体取向生长第一刻面144A,并且沿着(111)晶体取向生长第二刻面144B。在一些实施例中,通过选择性外延生长(SEG)工艺形成覆盖层144。
此外,像覆盖层144一样,在应激源层172上形成覆盖层174。位于应激源层172上方的覆盖层174上升至衬底102的顶面之上。由应激源层172和覆盖层174构造源极/漏极应激源结构170。在一些实施例中,覆盖层174由SiGe、Si、SiC或SiGeSn制成。在一些实施例中,通过选择性外延生长(SEG)工艺形成覆盖层174。
应该注意,覆盖层144形成在应激源层142上方,并因此沿着应激源层142的生长方向生长覆盖层144。沿着(311)和(111)晶体取向生长应激源层142和覆盖层144之间的边界。由于应激源层142具有密堆积结构,所以覆盖层144也具有密堆积结构。换句话说,覆盖层144遵循应激源层142的形状。此外,为了形成密堆积结构,用于形成覆盖层144的刻面生长速率慢于用于形成覆盖层174的刻面生长速率。因此,如图1C所示,覆盖层144从掺杂区122至隔离结构104向下倾斜,并且覆盖层144的一部分位于衬底102的顶面之下。
此外,为了形成密堆积结构,用于形成覆盖层144的原子必须提供有足够的量或者可形成薄覆盖层。例如,如果用于形成覆盖层144的硅源不足,则覆盖层144太薄以致于不能在其上方形成金属硅化物层(之后形成,如图1D所示)。结果,形成质量低劣的金属硅化物层和接触件结构。因此,可能发生源于高接触电阻的短路和电流泄漏问题。
为了解决短路和电流泄漏问题,在一些实施例中,良好控制在外延工艺期间用于形成覆盖层144的硅源以形成较厚的覆盖层144。这种控制方法将在图2中进行详细描述。在一些实施例中,覆盖层144的厚度T1在约10nm至约30nm的范围内。
根据本发明的一些实施例,如图1D所示,在形成覆盖层144之后,在覆盖层144上形成金属硅化物层146。例如,在覆盖层144上沉积金属薄膜,以与覆盖层144的露出的硅表面直接接触。可以实施诸如PVD工艺、CVD工艺、电镀工艺、化学镀工艺等的任何合适的工艺以形成金属薄膜。此后,实施加热操作以使沉积的金属薄膜与露出的硅表面之间发生反应,因此形成金属硅化物层146。然后,例如通过使用蚀刻工艺去除沉积的金属薄膜的未反应部分。尤其是在较小的几何结构中,金属硅化物层146具有比非硅化物区域更低的电阻。
根据本发明的一些实施例,如图1E所示,在形成金属硅化物层146之后,在衬底102上形成层间介电(ILD)层147,并且在ILD层147中形成接触件结构148。例如,在ILD层147中形成开口(未示出),并且将导电材料填充到开口以形成接触件结构148。接触件结构148与金属硅化物层146直接接触。接触件结构148由诸如铜或铜合金的导电材料制成。结果,形成半导体器件结构100。
此后,衬底102可以继续进行其他工艺以形成诸如金属间介电(IMD)层或互连结构的其他器件。本发明的实施例的优势在于,通过在形成覆盖层144期间控制硅源来获得源极/漏极应激源结构140中邻近隔离结构104的较厚的覆盖层144。因此,通过形成较厚的覆盖层144来提高金属硅化物层146的质量。此外,进一步提高了接触件结构148的质量。此外,扩大了用于形成接触件结构148的开口的工艺窗口。
图2示出了根据本发明的一些实施例处于外延工艺期间的晶圆的俯视图。在一些实施例中,外延工艺是选择性外延生长(SEG)工艺。
参照图2,提供晶圆10。晶圆10具有中心区10C和边缘区10E。在晶圆10的中心区10C和边缘区10E上形成有多个半导体器件结构100(在图1E中示出)。
一些源气体包括硅源气体或锗源气体。在一些实施例中,用于形成覆盖层144的硅源气体包括:单硅烷(SiH4)、乙硅烷(Si2H6)、二氯硅烷(DCS,SiH2Cl2)、六氯乙硅烷(HCD)、双(乙基甲胺)硅烷(BEMAS)、双(二乙胺)硅烷(BDEAS)、双(二甲胺)硅烷(BDMAS)、三(二甲胺)硅烷(Tris-DMAS)、四(二甲胺)硅烷(TDMAS)、三(乙基甲胺)硅烷(Tris-EMAS)、二乙胺硅烷(DEAS)、双(四丁胺)硅烷(BTBAS)或者二异丙胺硅烷(DIPAS)。锗源气体为诸如锗烷(GeH4)。此外,在选择性外延工艺期间还使用反应源气体、蚀刻气体(诸如HCl)和载气(诸如氢气(H2))。
如图2所示,将多个主要气体供给部22a、22b和22c供应至中心区10C,并且将多个边缘气体供给部32a、32b和32c供应至边缘区10E。在一些实施例中,主要气体供给部22a、22b和22c分别引入单硅烷(SiH4)、锗烷(GeH4)和HCl。在一些其他实施例中,边缘气体供给部32a、32b和32c分别引入单硅烷(SiH4)、锗烷(GeH4)和HCl。
在一些实施例中,与载气一起供应源气体。载气在中心区10C处的流速高于在边缘区10E处的流速。在一些实施例中,载气在中心区10C处的流速在约10slm至约50slm的范围内。在一些实施例中,载气在边缘区10E处的流速在约200sccm至约2000sccm的范围内。
在一些实施例中,使晶圆10绕轴A1旋转。由于晶圆10被转动,从主要气体供给部22a、22b和22c所供应的源气体可从中心区10C扩散至边缘区10E。因此,源气体在边缘区10E处的浓度小于在中心区10C处的浓度。源气体的不均匀的浓度可以在边缘区10E处引起缺陷。为了弥补该缺陷,如图2中的箭头50所示,将边缘气体供给部32a、32b和32c独立地供应至边缘区10E。
此外,由于在边缘区10E处不能足够地供应源气体,半导体器件100的短路和电流泄漏问题在边缘区10E上比在中心区10C上更严重。如上所述,在选择性外延工艺期间用于形成覆盖层144的硅源气体得以良好地控制以形成较厚的覆盖层144。因此,控制在边缘区10E处的用于形成覆盖层144和/或应激源层142的选择性外延生长(SEG)工艺以满足方程式(I):
边缘-E/D=HCl源的流速/Si源和Ge源的流速的总和---(I),
在一些实施例中,边缘-E/D值在约0.2至约0.8的范围内。如果边缘-E/D值太大,则没有足够的源气体供应至晶圆10,并因此获得较薄的覆盖层144。相反,如果边缘-E/D值太小,则可能发生严重的选择性损失并导致低劣的外延层质量。
在一些实施例中,边缘区10E处的用于形成应激源层142的源气体在约100sccm至约400sccm的范围内。在一些其他实施例中,边缘区10E处的用于形成覆盖层144的源气体在约50sccm至约200sccm的范围内。
在一些实施例中,在约500℃至约850℃的范围内的温度下实施用于形成应激源层142和/或覆盖层144的选择性外延工艺。在一些其他实施例中,在约1托至约760托的范围内的压力下实施用于形成应激源层142和/或覆盖层144的选择性外延工艺。
边缘区10E处的覆盖层144的厚度通过边缘-E/D值得以良好地控制。尤其是在边缘区10E处,供应足够的源气体以与覆盖层144的刻面生长速率相匹配。因此,覆盖层144的厚度足以形成高质量的金属硅化物层146和接触件结构148。
提供了用于形成半导体器件的实施例。在栅叠层结构和隔离结构之间形成源极/漏极应激源结构。源极/漏极应激源结构具有应激源层和覆盖层。覆盖层具有足以形成高质量的金属硅化物层和接触件结构的厚度。因此,解决了短路和电流泄漏问题。此外,较大的工艺窗口可用于形成接触件结构。
在一些实施例中,提供了一种半导体器件结构。该半导体器件结构包括衬底和形成在衬底上的栅叠层结构。该半导体器件结构还包括形成在栅叠层结构的侧壁上的栅极间隔件。该半导体器件结构还包括形成在衬底中的隔离结构和邻近隔离结构所形成的源极/漏极应激源结构。源极/漏极应激源结构包括沿着(311)和(111)晶体取向形成的覆盖层。
在一些实施例中,提供了一种半导体器件结构。该半导体器件结构包括衬底和形成在衬底上的栅叠层结构。该半导体器件结构还包括形成在栅叠层结构的侧壁上的栅极间隔件和形成在衬底中的掺杂区。该半导体器件结构还包括形成在衬底中的隔离结构以及形成在掺杂区和隔离结构之间的源极/漏极应激源结构。源极/漏极应激源结构包括形成在衬底中的应激源层和形成在应激源层之上的覆盖层。覆盖层从掺杂区至隔离结构向下倾斜。
在一些实施例中,提供了一种用于形成半导体器件结构的方法。该方法包括提供晶圆,并且该晶圆具有中心部分和边缘部分。该方法还包括在中心部分和边缘部分上形成半导体器件结构,该形成步骤包括:在晶圆的边缘部分中形成隔离结构;在晶圆的边缘部分上形成栅叠层结构;在栅叠层结构的侧壁上形成栅极间隔件;掺杂栅极间隔件之下的晶圆以形成掺杂区;以及在掺杂区和隔离结构之间生长源极/漏极应激源结构。源极/漏极应激源结构包括沿着(311)和(111)晶体取向形成的覆盖层。
尽管已经详细地描述了本发明的实施例及其优势,但是应该理解,在不背离由所附权利要求限定的本发明的精神和范围的情况下,在此可以做出各种改变、替代和变化。例如,本领域普通技术人员将容易理解,在本发明的范围内的情况下,在此描述的许多部件、功能、工艺和材料可以改变。此外,本申请的范围不旨在限于说明书中描述的工艺、机器、制造、材料组分、装置、方法和步骤的特定实施例。本领域的技术人员将容易从本发明的公开内容理解,根据本发明,现有的或今后开发的用于执行与根据本发明所采用的所述相应实施例基本相同的功能或获得基本相同结果的工艺、机器、制造、材料组分、装置、方法或步骤根据本发明可以被使用。因此,所附权利要求应该包括在这样的工艺、机器、制造、材料组分、装置、方法或步骤的范围内。此外,每条权利要求构成单独的实施例,并且多个权利要求和实施例的组合在本发明的范围内。
Claims (16)
1.一种半导体器件结构,包括:
衬底;
栅叠层结构,形成在所述衬底上;
栅极间隔件,形成在所述栅叠层结构的侧壁上;
隔离结构,形成在所述衬底中;以及
源极/漏极应激源结构,形成为邻近所述隔离结构,其中,所述源极/漏极应激源结构包括沿着(311)晶体取向和(111)晶体取向形成的覆盖层;
其中,所述源极/漏极应激源结构进一步包括:形成在所述衬底和所述覆盖层之间的应激源层,所述应激源层包括沿着所述(311)晶体取向生长的第一刻面、沿着所述(111)晶体取向生长的第二刻面、以及沿着所述(111)晶体取向生长的第四刻面。
2.根据权利要求1所述的半导体器件结构,其中,所述覆盖层包括SiGe、Si、SiC或SiGeSn。
3.根据权利要求1所述的半导体器件结构,其中,所述覆盖层的一部分位于所述衬底的顶面之下。
4.根据权利要求1所述的半导体器件结构,其中,所述覆盖层的厚度在10nm至30nm的范围内。
5.根据权利要求1所述的半导体器件结构,其中,所述半导体器件结构位于晶圆的边缘区处。
6.根据权利要求1所述的半导体器件结构,进一步包括:
形成在所述源极/漏极应激源结构上的金属硅化物层。
7.根据权利要求6所述的半导体器件结构,进一步包括:
形成在所述金属硅化物层上的接触件结构,其中,所述源极/漏极应激源结构通过所述金属硅化物层连接至所述接触件结构。
8.一种半导体器件结构,包括:
衬底;
栅叠层结构,形成在所述衬底上;
栅极间隔件,形成在所述栅叠层结构的侧壁上;
掺杂区,形成在所述衬底中;
隔离结构,形成在所述衬底中;以及
源极/漏极应激源结构,形成在所述掺杂区和所述隔离结构之间,其中,所述源极/漏极应激源结构包括:
形成在所述衬底中的应激源层;以及
形成在所述应激源层之上的覆盖层,并且所述覆盖层从所述掺杂区至所述隔离结构向下倾斜,所述覆盖层为沿着(311)晶体取向和(111)晶体取向形成;
其中,所述应激源层包括沿着(311)晶体取向生长的第一刻面、沿着所述(111)晶体取向生长的第二刻面、以及沿着所述(111)晶体取向生长的第四刻面。
9.根据权利要求8所述的半导体器件结构,其中,第一刻面具有第一厚度,而第二刻面具有第二厚度,并且所述第一厚度等于所述第二厚度。
10.根据权利要求8所述的半导体器件结构,其中,所述覆盖层的一部分位于所述衬底的顶面之下。
11.一种用于形成半导体器件结构的方法,包括:
提供晶圆,所述晶圆具有中心部分和边缘部分;
在所述中心部分和所述边缘部分上形成半导体器件结构,在所述中心部分和所述边缘部分上形成所述半导体器件结构包括:
在所述晶圆的所述边缘部分中形成隔离结构;
在所述晶圆的所述边缘部分上形成栅叠层结构;
在所述栅叠层结构的侧壁上形成栅极间隔件;
掺杂所述栅极间隔件下方的所述晶圆以形成掺杂区;以及
在所述掺杂区和所述隔离结构之间生长源极/漏极应激源结构,所述源极/漏极应激源结构包括沿着(311)晶体取向和(111)晶体取向形成的覆盖层;
所述源极/漏极应激源结构进一步包括:形成在衬底和所述覆盖层之间的应激源层,所述应激源层包括沿着所述(311)晶体取向生长的第一刻面、沿着所述(111)晶体取向生长的第二刻面、以及沿着所述(111)晶体取向生长的第四刻面。
12.根据权利要求11所述的方法,其中,生长所述源极/漏极应激源结构包括:
蚀刻所述晶圆以在所述晶圆中形成凹槽;
在所述凹槽中生长应激源层;以及
在所述应激源层上生长覆盖层。
13.根据权利要求12所述的方法,其中,在所述凹槽中生长所述应激源层包括:
通过选择性外延工艺在所述凹槽中生长SiGe应激源层。
14.根据权利要求13所述的方法,其中,控制所述选择性外延工艺以满足方程式(I):
边缘-E/D=HCl源的流速/Si源和Ge源的流速的总和---(I),
其中,所述边缘-E/D在0.2至0.8的范围内。
15.根据权利要求14所述的方法,其中,所述Si源和所述Ge源的流速的总和在100sccm至400sccm的范围内。
16.根据权利要求13所述的方法,其中,在500℃至850℃的范围内的温度以及1托至760托的范围内的压力的条件下,实施所述选择性外延工艺。
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