TWI509699B - 通道上工程應變之應變源 - Google Patents
通道上工程應變之應變源 Download PDFInfo
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- TWI509699B TWI509699B TW097133445A TW97133445A TWI509699B TW I509699 B TWI509699 B TW I509699B TW 097133445 A TW097133445 A TW 097133445A TW 97133445 A TW97133445 A TW 97133445A TW I509699 B TWI509699 B TW I509699B
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- Prior art keywords
- semiconductor material
- layer
- semiconductor
- epitaxial
- recess
- Prior art date
Links
- 239000000463 material Substances 0.000 claims description 189
- 239000004065 semiconductor Substances 0.000 claims description 133
- 238000000151 deposition Methods 0.000 claims description 100
- 238000000034 method Methods 0.000 claims description 86
- 230000008021 deposition Effects 0.000 claims description 70
- 229910052732 germanium Inorganic materials 0.000 claims description 69
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 claims description 68
- 239000000758 substrate Substances 0.000 claims description 66
- 229910052799 carbon Inorganic materials 0.000 claims description 55
- 239000012535 impurity Substances 0.000 claims description 51
- 239000013078 crystal Substances 0.000 claims description 43
- 239000002019 doping agent Substances 0.000 claims description 40
- 239000000945 filler Substances 0.000 claims description 37
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 claims description 36
- KJTLSVCANCCWHF-UHFFFAOYSA-N Ruthenium Chemical compound [Ru] KJTLSVCANCCWHF-UHFFFAOYSA-N 0.000 claims description 34
- 229910052707 ruthenium Inorganic materials 0.000 claims description 33
- 238000000137 annealing Methods 0.000 claims description 16
- 229910052715 tantalum Inorganic materials 0.000 claims description 13
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 claims description 13
- 238000005229 chemical vapour deposition Methods 0.000 claims description 7
- 229910052684 Cerium Inorganic materials 0.000 claims description 6
- GWXLDORMOJMVQZ-UHFFFAOYSA-N cerium Chemical compound [Ce] GWXLDORMOJMVQZ-UHFFFAOYSA-N 0.000 claims description 6
- 238000011049 filling Methods 0.000 claims description 5
- 230000001939 inductive effect Effects 0.000 claims description 5
- 238000000407 epitaxy Methods 0.000 claims description 4
- 229910052797 bismuth Inorganic materials 0.000 claims description 2
- JCXGWMGPZLAOME-UHFFFAOYSA-N bismuth atom Chemical compound [Bi] JCXGWMGPZLAOME-UHFFFAOYSA-N 0.000 claims description 2
- 239000007833 carbon precursor Substances 0.000 claims description 2
- 238000010438 heat treatment Methods 0.000 claims description 2
- 239000001307 helium Substances 0.000 claims description 2
- 229910052734 helium Inorganic materials 0.000 claims description 2
- SWQJXJOGLNCZEY-UHFFFAOYSA-N helium atom Chemical compound [He] SWQJXJOGLNCZEY-UHFFFAOYSA-N 0.000 claims description 2
- 229910052746 lanthanum Inorganic materials 0.000 claims description 2
- FZLIPJUXYLNCLC-UHFFFAOYSA-N lanthanum atom Chemical compound [La] FZLIPJUXYLNCLC-UHFFFAOYSA-N 0.000 claims description 2
- 125000006850 spacer group Chemical group 0.000 claims 5
- 229910052762 osmium Inorganic materials 0.000 claims 2
- SYQBFIAQOQZEGI-UHFFFAOYSA-N osmium atom Chemical compound [Os] SYQBFIAQOQZEGI-UHFFFAOYSA-N 0.000 claims 2
- BGJSXRVXTHVRSN-UHFFFAOYSA-N 1,3,5-trioxane Chemical compound C1OCOCO1 BGJSXRVXTHVRSN-UHFFFAOYSA-N 0.000 claims 1
- 229910052787 antimony Inorganic materials 0.000 claims 1
- WATWJIUSRGPENY-UHFFFAOYSA-N antimony atom Chemical compound [Sb] WATWJIUSRGPENY-UHFFFAOYSA-N 0.000 claims 1
- 125000005626 carbonium group Chemical group 0.000 claims 1
- 239000010410 layer Substances 0.000 description 146
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 44
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- 238000011065 in-situ storage Methods 0.000 description 7
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 6
- 229910052785 arsenic Inorganic materials 0.000 description 6
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- 229910052727 yttrium Inorganic materials 0.000 description 4
- VWQVUPCCIRVNHF-UHFFFAOYSA-N yttrium atom Chemical compound [Y] VWQVUPCCIRVNHF-UHFFFAOYSA-N 0.000 description 4
- YMWUJEATGCHHMB-UHFFFAOYSA-N Dichloromethane Chemical compound ClCCl YMWUJEATGCHHMB-UHFFFAOYSA-N 0.000 description 3
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- 229910052738 indium Inorganic materials 0.000 description 3
- 229910052758 niobium Inorganic materials 0.000 description 3
- 239000010955 niobium Substances 0.000 description 3
- GUCVJGMIXFAOAE-UHFFFAOYSA-N niobium atom Chemical compound [Nb] GUCVJGMIXFAOAE-UHFFFAOYSA-N 0.000 description 3
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- 239000000126 substance Substances 0.000 description 3
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- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 2
- 229910001339 C alloy Inorganic materials 0.000 description 2
- ZAMOUSCENKQFHK-UHFFFAOYSA-N Chlorine atom Chemical compound [Cl] ZAMOUSCENKQFHK-UHFFFAOYSA-N 0.000 description 2
- YCKRFDGAMUMZLT-UHFFFAOYSA-N Fluorine atom Chemical compound [F] YCKRFDGAMUMZLT-UHFFFAOYSA-N 0.000 description 2
- XYFCBTPGUUZFHI-UHFFFAOYSA-N Phosphine Chemical compound P XYFCBTPGUUZFHI-UHFFFAOYSA-N 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 2
- 229910052796 boron Inorganic materials 0.000 description 2
- 229910052801 chlorine Inorganic materials 0.000 description 2
- 150000001875 compounds Chemical class 0.000 description 2
- DIOQZVSQGTUSAI-UHFFFAOYSA-N decane Chemical compound CCCCCCCCCC DIOQZVSQGTUSAI-UHFFFAOYSA-N 0.000 description 2
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- 230000000694 effects Effects 0.000 description 2
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- 229910052731 fluorine Inorganic materials 0.000 description 2
- 239000011737 fluorine Substances 0.000 description 2
- 229910052735 hafnium Inorganic materials 0.000 description 2
- VBJZVLUMGGDVMO-UHFFFAOYSA-N hafnium atom Chemical compound [Hf] VBJZVLUMGGDVMO-UHFFFAOYSA-N 0.000 description 2
- 150000004820 halides Chemical class 0.000 description 2
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 2
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- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical compound [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 description 2
- YZCKVEUIGOORGS-OUBTZVSYSA-N Deuterium Chemical compound [2H] YZCKVEUIGOORGS-OUBTZVSYSA-N 0.000 description 1
- 229910052691 Erbium Inorganic materials 0.000 description 1
- 229910001257 Nb alloy Inorganic materials 0.000 description 1
- 229910001362 Ta alloys Inorganic materials 0.000 description 1
- 238000002441 X-ray diffraction Methods 0.000 description 1
- XLGLWCXGMHFINE-UHFFFAOYSA-N [SiH3][AsH2].[AsH3]=S Chemical compound [SiH3][AsH2].[AsH3]=S XLGLWCXGMHFINE-UHFFFAOYSA-N 0.000 description 1
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 1
- 239000000654 additive Substances 0.000 description 1
- 230000000996 additive effect Effects 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- 229910021417 amorphous silicon Inorganic materials 0.000 description 1
- RBFQJDQYXXHULB-UHFFFAOYSA-N arsane Chemical compound [AsH3] RBFQJDQYXXHULB-UHFFFAOYSA-N 0.000 description 1
- 229910052792 caesium Inorganic materials 0.000 description 1
- TVFDJXOCXUVLDH-UHFFFAOYSA-N caesium atom Chemical compound [Cs] TVFDJXOCXUVLDH-UHFFFAOYSA-N 0.000 description 1
- 239000012159 carrier gas Substances 0.000 description 1
- 229910000420 cerium oxide Inorganic materials 0.000 description 1
- 238000012512 characterization method Methods 0.000 description 1
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- 238000006243 chemical reaction Methods 0.000 description 1
- 238000007906 compression Methods 0.000 description 1
- 230000006835 compression Effects 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000002425 crystallisation Methods 0.000 description 1
- 230000008025 crystallization Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000002950 deficient Effects 0.000 description 1
- 230000001627 detrimental effect Effects 0.000 description 1
- 229910052805 deuterium Inorganic materials 0.000 description 1
- 229910003460 diamond Inorganic materials 0.000 description 1
- 239000010432 diamond Substances 0.000 description 1
- ZOCHARZZJNPSEU-UHFFFAOYSA-N diboron Chemical compound B#B ZOCHARZZJNPSEU-UHFFFAOYSA-N 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 230000002708 enhancing effect Effects 0.000 description 1
- UYAHIZSMUZPPFV-UHFFFAOYSA-N erbium Chemical compound [Er] UYAHIZSMUZPPFV-UHFFFAOYSA-N 0.000 description 1
- 229910052733 gallium Inorganic materials 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 238000009499 grossing Methods 0.000 description 1
- 229910000449 hafnium oxide Inorganic materials 0.000 description 1
- WIHZLLGSGQNAGK-UHFFFAOYSA-N hafnium(4+);oxygen(2-) Chemical compound [O-2].[O-2].[Hf+4] WIHZLLGSGQNAGK-UHFFFAOYSA-N 0.000 description 1
- 150000004678 hydrides Chemical class 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 230000000977 initiatory effect Effects 0.000 description 1
- 229910001507 metal halide Inorganic materials 0.000 description 1
- 150000005309 metal halides Chemical class 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 238000001000 micrograph Methods 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- BMMGVYCKOGBVEV-UHFFFAOYSA-N oxo(oxoceriooxy)cerium Chemical compound [Ce]=O.O=[Ce]=O BMMGVYCKOGBVEV-UHFFFAOYSA-N 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 229910000073 phosphorus hydride Inorganic materials 0.000 description 1
- 239000004033 plastic Substances 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 238000001004 secondary ion mass spectrometry Methods 0.000 description 1
- SMOJNZMNQIIIPK-UHFFFAOYSA-N silylphosphane Chemical compound P[SiH3] SMOJNZMNQIIIPK-UHFFFAOYSA-N 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- FAQYAMRNWDIXMY-UHFFFAOYSA-N trichloroborane Chemical compound ClB(Cl)Cl FAQYAMRNWDIXMY-UHFFFAOYSA-N 0.000 description 1
- IBEFSUTVZWZJEL-UHFFFAOYSA-N trimethylindium Chemical compound C[In](C)C IBEFSUTVZWZJEL-UHFFFAOYSA-N 0.000 description 1
- VEDJZFSRVVQBIL-UHFFFAOYSA-N trisilane Chemical compound [SiH3][SiH2][SiH3] VEDJZFSRVVQBIL-UHFFFAOYSA-N 0.000 description 1
- 239000012808 vapor phase Substances 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0843—Source or drain regions of field-effect devices
- H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02367—Substrates
- H01L21/0237—Materials
- H01L21/02373—Group 14 semiconducting materials
- H01L21/02381—Silicon, silicon germanium, germanium
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02436—Intermediate layers between substrates and deposited layers
- H01L21/02439—Materials
- H01L21/02441—Group 14 semiconducting materials
- H01L21/02447—Silicon carbide
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02436—Intermediate layers between substrates and deposited layers
- H01L21/02439—Materials
- H01L21/02441—Group 14 semiconducting materials
- H01L21/0245—Silicon, silicon germanium, germanium
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02521—Materials
- H01L21/02524—Group 14 semiconducting materials
- H01L21/02529—Silicon carbide
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02521—Materials
- H01L21/02524—Group 14 semiconducting materials
- H01L21/02532—Silicon, silicon germanium, germanium
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02612—Formation types
- H01L21/02617—Deposition types
- H01L21/02636—Selective deposition, e.g. simultaneous growth of mono- and non-monocrystalline semiconductor materials
- H01L21/02639—Preparation of substrate for selective deposition
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
- H01L29/161—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table including two or more of the elements provided for in group H01L29/16, e.g. alloys
- H01L29/165—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table including two or more of the elements provided for in group H01L29/16, e.g. alloys in different semiconductor regions, e.g. heterojunctions
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66636—Lateral single gate silicon transistors with source or drain recessed by etching or first recessed by etching and then refilled
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- H—ELECTRICITY
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
- H01L29/7848—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate the means being located in the source/drain region, e.g. SiGe source and drain
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T428/00—Stock material or miscellaneous articles
- Y10T428/24—Structurally defined web or sheet [e.g., overall dimension, etc.]
- Y10T428/24479—Structurally defined web or sheet [e.g., overall dimension, etc.] including variation in thickness
- Y10T428/24612—Composite web or sheet
- Y10T428/2462—Composite web or sheet with partial filling of valleys on outer surface
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Materials Engineering (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Description
本發明大體上是關於在半導體處理中沈積含矽材料,且更具體言之是關於在半導體基板之凹入源極以及汲極區中磊晶沈積含矽材料。
在形成積體電路時,通常在選定位置中,諸如場隔離區域(field isolation region)中的主動區台(active area mesa)中,或甚至更具體言之在經界定之源極以及汲極區域上需要磊晶層(epitaxial layer)。雖然非磊晶材料(其可為非晶形或多晶的)可在沈積之後選擇性地自場隔離區域上移除,但通常認為較有效的是同時提供化學氣相沈積(chemical vapor deposition,CVD)以及蝕刻化學劑,且調諧條件以在絕緣區域上產生零淨沈積(zero net deposition)並在暴露之半導體窗上產生淨磊晶沈積(net epitaxial deposition)。此過程(稱為選擇性磊晶CVD)利用典型半導體沈積過程在絕緣體(諸如氧化矽或氮化矽)上之緩慢晶核形成。此選擇性磊晶CVD亦利用非晶形以及多晶材料本質上對蝕刻劑之較大的易感性(與磊晶層之易感性相比)。
需要半導體層之選擇性磊晶形成的許多情形之實例包括用於產生應變之許多方案。材料經受應變之程度影響諸如矽、摻碳矽、鍺以及矽鍺合金之半導體材料之電學性質。舉例而言,半導體材料在拉伸應變下可展現增強之電子遷
移率(electron mobility),其對於NMOS元件特定需要;以及在壓縮應變下可展現增強之電洞遷移率(hole mobility),其對於PMOS元件特定需要。增強半導體材料之效能之方法具有顯著的重要性且在多種半導體處理應用中具有潛在的應用。半導體處理通常用於積體電路之製造(其需要特別嚴格的品質需求)中以及多種其他領域中。舉例而言,半導體處理技術亦用於使用多種技術之平板顯示器之製造中以及微機電系統(microelectromechanical system,MEMS)之製造中。
用於在含矽以及含鍺之材料中誘發應變之許多方法已聚焦於利用各種結晶材料(crystalline material)之間的晶格常數(lattice constant)的差異。舉例而言,結晶鍺之晶格常數為5.65,結晶矽之晶格常數為5.431,且金剛石碳之晶格常數為3.567。異質磊晶涉及將特定結晶材料之薄層沈積於一不同之結晶材料上,使得所沈積層採用下伏晶體材料之晶格常數。舉例而言,藉由使用此方法,應變矽鍺(silicon germanium)層可藉由異質磊晶沈積於單晶矽基板上而形成。因為鍺原子稍大於矽原子,且所沈積異質磊晶矽鍺約束於其下方之矽的較小晶格常數,所以矽鍺經受壓縮應變且經受壓縮應變之程度隨鍺含量而變。通常矽鍺層之能帶隙隨矽鍺中之鍺含量增加而自純矽的1.12 eV單調降低至純鍺的0.67 eV。在另一方法中,拉伸應變藉由將矽層異質磊晶沈積於一鬆弛的矽鍺層上而形成於薄的單一結晶矽層中。在此實例中,異質磊晶沈積之矽經受
應變,因為其晶格常數約束於其下方鬆弛的矽鍺之較大晶格常數。拉伸應變通道通常展現增加之電子遷移率,且壓縮應變通道展現增加之電洞遷移率。
在此等實例中,藉由將晶格結構中之矽原子用其他原子替換而將應變誘發於單一結晶含矽材料中。此技術通常稱作取代摻雜。舉例而言,在單一結晶矽之晶格結構中用鍺原子取代矽原子中之一些在所得取代摻雜之單一結晶矽材料中產生壓縮應變,因為鍺原子大於其所替換之矽原子。可能藉由用碳進行取代摻雜而將拉伸應變誘發於單一結晶矽中,因為碳原子小於其所替換之矽原子。在Judy L.Hoyt於Taylor and Francis(New York 2002)中第59-89頁的“Silicon-Germanium Carbon Alloy”第3章“Substitutional Carbon Incorporation and Electronic Characterization of Si1-y
Cy
/Si and Si1-x-y
Gex
Cy
/Si Heterojunctions”中提供了額外的細節,所述參考在本文中稱為“Hoyt文章”。然而,非取代雜質將不誘發應變。
類似地,電學摻雜劑(electrical dopant)亦應取代地併入磊晶層中以便為電活性的。摻雜劑在沈積時併入,或基板應退火,以達成取代以及摻雜劑啟動之所要程度。用於剪裁晶格常數之雜質或電學摻雜劑之原位摻雜經常優於在進行外部摻雜之後退火以將摻雜劑併入晶格結構中,因為退火消耗熱預算。然而,實務上,原位取代摻雜由於在沈積期間將非取代地併入摻雜劑的趨勢而為複雜的,例如,藉由在矽內的晶疇或團簇中格隙地併入而非在晶格結
構中取代矽原子。非取代摻雜使(例如)矽之碳摻雜、矽鍺之碳摻雜以及半導體之以電活性摻雜劑之摻雜變複雜。如Hoyt文章第73頁之圖3.10所說明,先前沈積方法已用以使結晶矽具有高達2.3原子%之原位摻雜取代碳含量,其對應於超過5.4之晶格間距以及小於1.0 GPa之拉伸應變。
源極以及汲極凹區可用含矽合金填充作為“應變源(stressor)”,其施加壓縮或拉伸應變至源極與汲極之間的矽通道上。舉例而言,源極以及汲極凹區中之應變磊晶矽鍺(“SiGe”)可施加壓縮應變至矽通道上且提高電洞遷移率。類似地,源極/汲極凹區中拉伸應力下之摻碳矽(“Si:C”)磊晶合金可在通道上誘發拉伸應變且提高電子遷移率。一般地,通道上之應變與雜質(諸如C或Ge)之濃度有關。換言之,Ge或C含量愈高,則所產生的應變愈高。
根據本發明之態樣,提供用於選擇性形成半導體材料之方法。在化學氣相沈積腔室內提供基板。基板包括絕緣表面以及單晶半導體表面。單晶半導體表面包括凹區。半導體應變源選擇性形成於凹區中。半導體應變源經分級以使得凹區內半導體應變源之上部具有比下部高的應變量,且上部延伸至凹區之側壁。
根據本發明之另一態樣,提供用於選擇性形成異質磊晶半導體材料之方法。半導體材料沈積於基板之凹入單晶
半導體區域之底部以及側壁表面上。自凹入區域之側壁表面選擇性移除半導體材料之部分,同時在底部表面上留下半導體材料之異質磊晶層。重複沈積以及選擇性移除,其中半導體材料之後續沈積之異質磊晶層相比較半導體材料之先前沈積異質磊晶層而言包括不同濃度之應變誘發雜質。
根據本發明之另一態樣,提供用於在凹區中形成半導體材料之方法。提供其中形成有絕緣區域以及凹區之基板。異質磊晶含矽材料之襯墊層沈積於凹區中。襯墊層包括應變誘發雜質且部分填充凹區。藉由將填充劑沈積於襯墊層上而用包括含矽材料之填充劑填充凹區,所述含矽材料具有比襯墊層低的雜質濃度。
根據本發明之另一態樣,提供半導體元件,其包括基板中之凹區、異質磊晶襯墊、填充劑以及相鄰於凹區之電晶體通道。異質磊晶含矽襯墊實質上覆蓋凹區之所有單晶側壁表面。襯墊包括更改晶格常數之雜質。填充劑形成於襯墊上且填充凹區。填充劑包括含矽材料,其具有比上面形成填充劑之襯墊低的雜質濃度。
根據本發明之又一態樣,提供半導體基板,其包括凹區以及相鄰於凹區之電晶體通道。凹區填充有異質磊晶應變源材料。凹區內之應變源材料之上部具有第一雜質濃度,且凹區內之應變源材料之下部具有第二雜質濃度。第一雜質濃度高於第二雜質濃度,且上部延伸以接觸凹區之側壁。
術語“雜質”在本文中用以指代添加劑(例如鍺或碳),其更改相對於單獨矽之半導體晶格常數,所得半導體化合物經常稱作合金或簡稱為異質磊晶層。“摻雜劑”可指代雜質或電學摻雜劑(諸如磷、砷、硼等)。術語“含矽材料”以及類似術語在本文中用以指代多種含矽材料,包括但不限於:矽(包括結晶矽)、摻碳矽(“Si:C”)、矽鍺(“SiGe”)以及摻碳矽鍺(“SiGe:C”)。如本文所使用,“摻碳矽”、“Si:C”、“矽鍺”、“SiGe”、“摻碳矽鍺”、“SiGe:C”以及類似術語指代包括以各種比例之所指示化學元素以及(視情況)少量其他元素的材料。舉例而言,“矽鍺”為包括矽、鍺以及(視情況)其他元素(例如,諸如碳以及電活性摻雜劑之摻雜劑)的材料。諸如“Si:C”以及“SiGe:C”之簡寫術語本身並非化學計量之化學式,且因此並不限於包括特定比率之所指示元素之材料。此外,諸如Si:C以及SiGe:C之術語並不意欲排除其他摻雜劑之存在,使得摻磷以及摻碳之矽材料包括在術語Si:C以及術語Si:C:P中。除非另有說明,否則諸如碳或鍺之摻雜劑在含矽膜中之百分比在本文中用基於整個膜或子膜之原子百分比表示。應瞭解,諸如碳或鍺之雜質摻雜劑(但排除其他元素,諸如電學摻雜劑)在本文所述之含矽膜中之濃度為至少約0.3原子%。然而,熟習此項技術者將瞭解,電學摻雜劑可在層中誘發應變且因此亦可包括在此些層中。
可能藉由以下方法來確定取代摻雜於含矽材料中之諸如鍺或碳之雜質的量,例如:藉由x射線繞射來量測所摻雜含矽材料之垂直晶格間距,接著對於SiGe合金藉由在單晶矽與單晶鍺之間執行線性內插來應用魏加式定律(Vegard’s Law)或對於Si:C合金內之碳應用Kelires/Berti關係。在Hoyt文章中提供了關於此技術之額外細節。次級離子質譜分析(Secondary ion mass spectrometry,SIMS)可用以確定所摻雜矽中之總雜質含量。可能藉由自總雜質含量減去取代雜質含量而確定非取代或格隙雜質含量。可以類似方式來確定取代摻雜於其他含矽材料中之其他元素的量。
“基板”(在此術語用於本文中時)指代其上需要沈積之工件或暴露至一或多種沈積氣體之表面。舉例而言,在某些實施例中,基板為單晶矽晶圓、絕緣體上半導體(semiconductor-on-insulator,SOI)基板或磊晶矽表面、矽鍺表面或沈積於晶圓上之III-V族材料。工件並不限於晶圓,但亦包括玻璃、塑膠或半導體處理中所使用之其他基板。在所說明之實施例中,基板已經圖案化以具有兩種或兩種以上不同類型之表面。在某些實施例中,當最小化且較佳地避免在相鄰介電質或絕緣體上沈積時,含矽層選擇性地形成於單晶半導體材料上。在其他實施例中,當在相鄰絕緣體上沈積非晶形或多晶材料時,沈積磊晶發生在單晶半導體表面上。介電質或絕緣體材料之實例包括二氧化矽(包括低介電常數形式),諸如矽之摻碳以及摻氟氧化
物、氮化矽、金屬氧化物以及金屬矽化物。
術語“磊晶”、“異質磊晶”以及類似術語在本文中用以指代將結晶含矽材料沈積於結晶基板上,使得所沈積層採用或遵循下伏層或基板之晶格常數。當所沈積層之組合物不同於下伏層或基板之組合物時,磊晶沈積為異質磊晶。當所沈積層之組合物與下伏層或基板之組合物相同時,磊晶沈積為同質磊晶。
在某些應用中,圖案化基板具有具第一表面形態之第一表面以及具有第二表面形態之第二表面。即使表面由相同元素製造,若表面之形態或結晶性不同,則認為表面是不同的。非晶形以及結晶是不同形態之實例。多晶形態為由有序晶體之無序配置組成之結晶結構,且因此具有中間有序度(intermediate degree of order)。多晶材料中之原子在晶體中之每一者中是有序的,但晶體本身相對於彼此缺少長程順序(long range order)。單晶形態是具有高程度長程順序之結晶結構。磊晶膜之特徵在於與其所成長之基板(通常為單晶)相同之平面內晶體結構及定向。此等材料中之原子配置於晶格狀結構中,其持續在原子標度之相對長距離上。非晶形形態為具有低有序度之非結晶結構,因為原子缺少確定之週期配置。其他形態包括微晶以及非晶形與結晶材料之混合物。“非磊晶”因此包括非晶形、多晶、微晶以及其混合物。如本文所使用,“單晶”或“磊晶”用以描述其中具有容許錯誤數之相當大的晶體結構,如一般用於電晶體製造中的晶體結構。層之結晶性通常沿連續
區自非晶形降至多晶降至單晶;晶體結構通常被認為是單晶或磊晶(不管低密度錯誤)。無論是否由於不同的形態及/或不同的材料,具有兩個以上不同類型之表面的混合基板之特定實例包括但不限於:單晶/多晶、單晶/非晶形、磊晶/多晶、磊晶/非晶形、單晶/介電質、磊晶/介電質、導體/介電質以及半導體/介電質。本文所述之用於將含矽膜沈積於具有兩種類型表面之混合基板上的方法亦適用於具有三種或三種以上不同類型表面之混合基板。
當在凹入源極/汲極區中成長至低於其臨界厚度之厚度時,拉伸應變含矽材料將單軸拉伸應變誘發至相鄰於凹入源極/汲極區之矽通道中。此拉伸應變材料包括(但不限於)摻碳矽膜(Si:C膜)以及摻碳矽鍺膜(SiGe:C膜),其中鍺濃度小於碳濃度之約8-10倍,從而導致增強之電子遷移率,其對於NMOS元件尤其有益。此消除了提供鬆弛矽鍺緩衝層以支撐應變矽層之需要。在此些應用中,電活性摻雜劑藉由使用摻雜劑源或摻雜劑前驅體進行原位摻雜而併入。典型n
型摻雜劑源包括砷蒸氣以及摻雜劑、氫化物,諸如磷化氫以及砷化氫。磷化氫甲矽烷(Silylphosphine)(例如(H3
Si)3-x
PRx
)以及砷化氫甲矽烷(silylarsine)(例如(H3
Si)3-x
AsRx
)(其中x=0、1或2,且Rx
=H及/或氘(D))為磷以及砷摻雜劑之替代前驅體。磷以及砷尤其有用於摻雜NMOS元件之源極以及汲極區。SbH3
以及三甲基銦分別為銻以及銦之替代源。此摻雜劑前驅體有用於如下所述膜之製備,較佳為摻磷、摻銻、摻銦
以及摻砷矽、Si:C以及SiGe:C膜與合金。
當在凹入源極/汲極區中成長至低於臨界厚度之厚度時,壓縮應變含矽材料將單軸壓縮應變誘發至相鄰於凹入源極/汲極區之矽通道中,從而導致增強之電洞遷移率,其對於PMOS元件尤其有益。此壓縮應變材料包括(但不限於)矽鍺膜(“SiGe膜”)以及摻碳矽鍺膜(“SiGe:C膜”),其中鍺濃度大於碳濃度之約8-10倍。在此些應用中,電活性摻雜劑藉由使用摻雜劑源或摻雜劑前驅體進行原位摻雜而併入。典型p
型摻雜劑前驅體包括用於硼摻雜之乙硼烷(B2
H6
)以及三氯化硼(BCl3
)。用於Si之其他p型摻雜劑包括Al、Ga、In以及蒙德列夫(Mendeleiev)元素週期表中Si之左側的任何金屬。此摻雜劑前驅體有用於如下所述膜之製備,較佳為摻硼矽、SiGe以及SiGe:C膜與合金。
對於可在沒有過多錯位(dislocations)之情況下成長於凹入源極以及區域中之SiGe或Si:C之層的厚度存在限制。可成長之層的厚度大體上與雜質含量成反比。當前,具有均一組合物以及在約10-50 nm範圍內之厚度的SiGe合金可用可接受錯位量來沈積,其中對於SiGe具有小於約40原子%Ge且對於Si:C具有小於約3原子%C。在這些限制之外,層之可允許厚度以及成長速率隨過程溫度降低而急劇降低,以便抑制錯位晶核形成。舉例而言,通常,僅幾個單層之純Ge可成長於矽上而沒有錯位。在臨界厚度之外,在層中產生對元件之效能有害之大量錯位。高的整
體雜質含量可導致錯位。在本文所述之較佳實施例中,減少應變源中之整體雜質含量,同時仍藉由在相鄰於電晶體通道之凹區之側壁處使應變局部化而最大化應變之效應。
現已開發用於在暴露半導體窗中形成包括含矽材料(諸如Si:C、SiGe以及SiGe:C)之應變膜的技術。在所說明之實施例中,應變膜沈積於凹入源極/汲極區域中以施加應變至相鄰通道區域上,且因此亦稱作“應變源”。根據較佳實施例,應變異質磊晶半導體材料沈積於凹入源極/汲極區域中,以相對於基板中所誘發的整體應變而增加相鄰電晶體通道區域上所誘發的應變。因為應變源在凹區內之不同區域處具有不同組合物,所以應變源經分級,但等級在兩個或兩個以上離散層中可為連續或步進的。
圖1至圖5D說明異質磊晶應變源材料之沈積以由下而上方式進行且經分級以使得最高應變處於頂部表面且延伸至凹區之側壁的實施例。舉例而言,可能藉由以下步驟而完成此形成:(a)將Si:C膜毯覆式沈積於凹區中;以及(b)自凹區之側壁選擇性蝕刻半導體材料,在凹區之底部處留下異質磊晶層。步驟(b)可同時在絕緣體上蝕刻非磊晶半導體材料。步驟(a)以及(b)視情況用不同的雜質含量且因此不同的應變程度而循環重複,直至在凹入源極/汲極區域上達成目標磊晶膜厚度。在替代實施例中,其他沈積技術可用以在基板之凹區中形成垂直分級之含矽材
料。
可能藉由乾式蝕刻(dry etching)以及隨後之HF清潔以及原位退火而形成凹入源極/汲極區域。在使用乾式蝕刻之實施例中,選擇性成長之薄(介於大致1 nm與大致3 nm之間)矽晶種層(seed layer)之沈積幫助減少蝕刻損壞。晶種層亦幫助覆蓋先前摻雜劑植入過程所導致之損壞。在例示性實施例中,此晶種層可在約700℃與約800℃之間的沈積溫度下使用同時提供HCl
以及二氯甲矽烷而選擇性沈積。
根據某些實施例,在圖1中提供之流程圖中以及在圖2至圖5E中所說明之部分形成半導體結構的示意性說明中說明循環毯覆式沈積以及蝕刻過程。雖然下文在由特定循環過程進行之拉伸應變Si:C沈積之實施例的上下文中論述,但應瞭解如對於由其他技術以由下而上方式形成之其他應變材料,可在磊晶膜之形成中使用本文所述之凹區之由下而上分級填充。Si:C實施例較佳包括介於約0.1原子%與4原子%之間、且較佳介於約1原子%與3原子%範圍內的取代碳,且經分級以在靠近基板表面處具有最高應變。熟習此項技術者將瞭解,較佳循環過程可選擇性形成Si:C,其對於給定膜品質具有比習知選擇性沈積之同時蝕刻劑以及前驅體流更高的碳濃度,且亦允許應變源在凹區頂部處具有最高應變之部分延伸至相鄰於通道之凹區壁。在一些實施中將瞭解,凹區壁可由在蝕刻凹區之後經沈積以內襯凹區之磊晶層界定。本文所描述之技術可用於在凹
入源極/汲極區域中沈積其他磊晶膜,諸如SiGe及SiGe:C。
詳言之,圖1說明具有凹入源極/汲極區域之基板在操作區塊10中置放於處理腔室(process chamber)中。如操作區塊20所指示,半導體合金層保形(conformally)沈積於基板上。在一個實施例中,此保形沈積為在基板之任何絕緣體區域上留下非晶形或多晶材料之毯覆式沈積以及在源極/汲極區域之底部以及側壁上之磊晶沈積。在保形沈積之後,非晶形或多晶材料以及側壁磊晶材料之任何區域可經選擇性蝕刻,如操作區塊30所指示。在選擇性蝕刻之後,確定凹入源極/汲極區域中之磊晶膜的目標厚度是否達成,如操作區塊40所示。若目標厚度已達成,則過程結束,如操作區塊45中所示。若目標厚度尚未達成,則過程藉由遞增或增加誘發應變雜質濃度(諸如碳)而循環繼續,如操作區塊50所指示。此增加濃度用於半導體合金層之下一保形沈積,其由操作區塊20所指示。增加雜質濃度之下一保形沈積後接續有任何非晶形或多晶以及側壁磊晶材料之選擇性蝕刻,如操作區塊30所示。在此沈積以及蝕刻過程之後,凹入源極/汲極中磊晶膜厚度經評估以確定目標厚度是否達成,如操作區塊40所示。重複此循環過程直至達成目標厚度。進行至少兩次循環20-50以便達成分級應變源。
圖2提供示範性基板之示意性說明,其包括形成於半導體基板100(諸如矽晶圓)中之圖案化絕緣體110。絕緣體110為氧化物填充淺溝槽隔離(shallow trench isolation,STI)之形式並界定場隔離區域112,且相鄰於展示在閘極
結構115之任一側上之凹入源極/汲極區域114。請注意,閘極結構115覆蓋基板之通道區域117。通道117、源極以及汲極區域114共同界定電晶體主動區,其通常由場隔離區域112圍繞以防止與相鄰元件的干擾(cross-talk)。在其他配置中,多個電晶體可由場隔離圍繞。在一種情況下,閘極結構115之頂部可由介電材料覆蓋。此表面接著相對於其上之沈積而對場隔離區域112起類似的作用,且閘極頂部上之沈積將具有與場隔離區域上之沈積類似的結晶性。在閘極結構115未覆蓋有介電材料之情況下,閘極之表面將成長多晶材料,其接著可經由多晶材料之原位蝕刻而移除,但可應用不同之條件集合(諸如壓力、氣流等)用於確保自場隔離區域112移除材料。
下文描述涉及用於NMOS應用之摻碳矽(Si:C)之特定實例的實施例。如圖3中示意性說明,毯覆式Si:C層120、125、130沈積於混合基板上,較佳使用三矽烷(trisilane)作為矽前驅體,且亦使碳前驅體流動。此導致在場隔離區域112上之Si:C之主要非晶形或多晶或非磊晶沈積120,以及Si:C之下部磊晶沈積125與側壁磊晶沈積130內襯凹入源極/汲極區域114。請注意,“毯覆式沈積”意謂淨沈積在沈積階段中產生於非晶形絕緣體110以及單晶源極/汲極區域114兩者上。雖然缺少蝕刻劑或鹵化物在毯覆式沈積過程(在此情況下沈積亦被認為是“非選擇性的”)中為較佳的,但可能需要某些量之蝕刻劑以調諧各種區域上之所沈積厚度的比率。在需要此類少量蝕刻劑之
情況下,雖然是毯覆式,但沈積過程可能為部分選擇性的,因為每一沈積階段將在絕緣體110以及單晶區域(即源極/汲極區域114)上具有淨沈積。
根據一實施例,非晶形或多晶沈積120以及側壁磊晶沈積130之區域接著經選擇性蝕刻,因此產生示意性說明於圖4中之結構。在另一實施例中,側壁區域上之沈積可為多晶或非晶形材料。雖然在選擇性蝕刻期間自凹入源極/汲極區域114中之下部磊晶層125移除了一些磊晶沈積之Si:C,但保留了下部磊晶層125之至少一些。側壁磊晶層130成長於不同之結晶平面上,且亦由於在兩表面上之成長速率差異而比下部磊晶層125更具缺陷。熟習此項技術者將瞭解,垂直側壁磊晶層130中之晶格間距小於下部磊晶層125之晶格間距,其導致兩表面上之成長速率差異。因此,側壁磊晶層130較容易與非磊晶材料120一起移除。因此,每一過程循環可經調諧以達成對凹區(即源極/汲極區域114)之大量由下而上填充。如自圖1之論述將瞭解,每一循環包括自凹區側壁之毯覆式保形沈積20以及選擇性蝕刻30。
如下文中較詳細論述,在示範性實施例中,氣相蝕刻化學物較佳包括鹵化物,諸如含氟、含溴或含氯氣相化合物,且特定言之氯源,諸如HCl或Cl2
。在一些實施例中,蝕刻化學物亦包括鍺源,諸如類似於單鍺烷(GeH4
)之鍺烷、GeCl4
、有機鍺前驅體或固態源鍺。熟習此項技術者將瞭解,相同蝕刻化學物亦適用於SiGe以及SiGe:C膜。
在上文關於圖4所描述之選擇性蝕刻過程之後,第二毯覆式Si:C層122、132、135接著沈積於混合基板上,如圖5A所示。此第二毯覆式Si:C層122、132、135包括比第一毯覆式Si:C層120-130高的碳濃度,如圖3所示。根據實施例,第一毯覆式Si:C層120、125、130之碳濃度介於約1原子%與1.5原子%之間,且第二毯覆式Si:C層122、132、135之碳濃度大於約1.5原子%,且較佳在約1.5原子%至4原子%之間的範圍內。在SiGe膜之成長之替代實施例中,第一毯覆式SiGe層之鍺濃度在10原子%至20原子%之間的範圍內,且較佳為約15原子%;第二毯覆式SiGe層之鍺濃度在20原子%至100原子%之間的範圍內,且較佳在約30原子%至60原子%之間的範圍內。如圖5A所示,第二毯覆式Si:C層122、132、135包括非晶形或多晶矽部分122、側壁磊晶部分132以及凹區底部表面部分135。Si:C之此第二層122、132、135接著經選擇性蝕刻以移除場隔離區域112中之非晶形絕緣體110上之非磊晶部分以及側壁磊晶層132,如圖5B所示。在另一實施例中,側壁沈積為非晶形或多晶。在任何情況下,對於此實施例,側壁層比底部磊晶材料更容易移除。
重複此循環過程(包括具有漸進較高碳濃度之Si:C層之毯覆式沈積,後接續有選擇性蝕刻過程),直至在凹入源極/汲極區域114上達成磊晶Si:C膜厚度之目標厚度,如圖1所示之決策區塊40所示。此循環過程亦示意性說明於圖5A中以及圖5B中,圖5A說明毯覆式Si:C層122、132、
135之第二循環之沈積,且圖5B繪示非晶形或多晶Si:C層122以及側壁磊晶層132之第二循環之蝕刻以留下具有增加厚度之底部覆蓋磊晶Si:C。具有增加厚度之底部覆蓋磊晶Si:C在凹入源極/汲極區域114中包括離散分級層125、135。圖5C說明留下磊晶填充源極/汲極區域114之另一循環的結果,其中離散選擇性分級磊晶層之頂部層145粗略與絕緣體110共面。儘管經說明為另一循環,但熟習此項技術者將瞭解可執行額外循環以填充凹入源極/汲極區域114。
雖然圖5C展示三個離散分級層,但熟習此項技術者將瞭解,在其他實施例中可存在更多或更少數目之離散分級層以達成磊晶填充之源極/汲極區域,其具有粗略與場氧化層共面之頂部表面。將理解,在另一實施例中,離散分級磊晶層125、135、145可經選擇性沈積為升高之源極/汲極區域114。如圖5C所示,每一沈積層覆蓋凹入區域(即源極/汲極區域114)之側壁表面之至少一部分。根據替代實施例,層125、135、145等可形成連續分級層,其中每一後續沈積層具有漸進較高之碳濃度。舉例而言,每一層可在沈積時經分級及/或後續熱處理可藉由擴散而使分級平滑。無論分級層為連續的還是步進的,凹入區域內之最高應變處於凹區之頂部(大致與晶圓之表面共面),且分級磊晶層125、135、145等中之每一者延伸至相鄰於通道之凹區側壁。因此,即使在側壁處,分級主要為垂直而非水平遠離側壁延伸。如上所述,在一些配置中,凹區側壁由
具有可選凹區清潔或熱平滑步驟之蝕刻過程界定。在其他配置中,凹區側壁由諸如薄磊晶層之內襯層(lining layer)界定。分級結構之每一沈積層可具有約1 nm至100 nm之厚度。根據另一實施例,每一沈積層具有約3 nm至50 nm之厚度。根據另一實施例,每一沈積層具有約3-5 nm之厚度。在一些實施例中,分級磊晶層中之每一者具有相同厚度。在其他實施例中,分級磊晶層具有不同相對厚度。
選擇性形成過程可更包括毯覆式沈積以及選擇性回蝕之額外循環,以自介電區域移除沈積材料從而形成可選封蓋層(capping layer)150,如圖5D所示。封蓋層150可能具有或沒有雜質或電學摻雜劑。舉例而言,升高源極/汲極區域114在原始基板表面上方以及源極/汲極區域114之間的通道117上方的部分可為無碳的,因為此部分在其處於通道117水平面上方時並不貢獻於通道117上之應變。因此,可選封蓋層150可由Si、SiGe、SiGe:C或Si:C形成,且可用以提供用於接觸矽化(contact silicidation)之額外Si。在一個實施例中,層125、135、145可由Si:C形成,而封蓋層150由Si、SiGe、SiGe:C或Si:C形成。在另一實施例中,層125、135、145可由SiGe形成,而封蓋層150由Si、SiGe、SiGe:C或Si:C形成。在示範性實施例中,沈積分級Si:C層視情況包括電活性摻雜劑,特定言之適合於NMOS元件之摻雜劑,諸如磷或砷。
在一個實施例中,為了幫助維持取代碳以及電活性摻雜劑之高濃度,同時最小化溫度斜坡(temperature ramp)
/穩定時間,基板溫度至少在圖1之蝕刻階段30期間較佳保持為低的,例如在約350℃與700℃之間的範圍內。藉由使用低溫用於蝕刻亦降低了電活性摻雜劑原子在蝕刻期間去活性之可能性。舉例而言,用Cl 2
氣體蝕刻有利地允許降低蝕刻溫度,因此幫助維持取代碳以及電活性摻雜劑。用於蝕刻階段之低溫在利用低溫下達成之高摻雜劑併入的同時啟用粗略匹配之沈積階段溫度。可藉由以下方法提高蝕刻速率以允許此等低溫而不犧牲產量:藉由在蝕刻階段期間包括鍺源,例如GeH4
、GeCl4
、金屬有機Ge前驅體、固態源Ge;或藉由在蝕刻階段期間快速上升溫度以改良產量。在整個循環中設定點溫度保持相對恆定(例如在±10℃內)之等溫處理改良產量,且最小化溫度上升以及穩定之時間。類似地,毯覆式沈積以及蝕刻過程兩者均較佳為等壓的,其中壓力設定點在彼此的±20托內。等溫及/或等壓條件有助於因為避免上升以及穩定時間而獲得較佳產量。
如圖1所說明,視情況循環重複執行毯覆式沈積後接續有選擇性蝕刻之兩階段過程,直至達成填充源極/汲極凹區之目標磊晶膜厚度。用於穩定之例示性過程參數以及一個循環概述於下文之表A中,其列出示範性操作點以及在圓括號中列出較佳操作範圍。如自表A顯而易見,過程條件(諸如腔室溫度、腔室壓力以及載氣流動速率)較佳實質上類似於沈積以及蝕刻階段,從而允許增加產量。因此,以下實例對於一循環之兩階段使用等溫以及等壓條件。其
他參數用於具有不同雜質濃度之後續沈積之層。舉例而言,Si以及C前驅體流可能為不同的,或腔室溫度可經調整以沈積具有較高雜質濃度之層。
表A提供用於在凹入源極/汲極區域中沈積磊晶Si:C膜之示範性過程參數,如上文關於圖1至圖5D所論述。藉由使用表A中提供之參數,對於選擇性沈積於凹入源極/汲極區域中之磊晶Si:C:P膜,可能達成較佳在約4 nm/min與約11 nm/min之間的淨成長速率,且更佳地在約8
nm/min與約11 nm/min之間。亦可能達成薄的Si:C:P膜,其具有高達3.5%之取代碳含量(如藉由應用Kelires/Berti關係而確定)且具有介於約0.4 mΩ cm與約2.0 mΩ cm之間的電阻率。藉由操縱沈積條件,可能獲得其他的膜性質。熟習此項技術者將瞭解,沈積條件通常經調整用於沈積後續層。
在本文所揭露之蝕刻過程期間,在蝕刻選擇性介於約10:1與30:1之間的範圍中之每一蝕刻階段中,磊晶Si:C蝕刻顯著慢於非晶形或多晶Si:C。側壁磊晶材料亦在蝕刻階段優先移除。在較佳實施例中,循環沈積以及蝕刻過程條件經調諧以減少或消除非晶形絕緣體110上之淨成長,同時達成磊晶凹入源極/汲極區域114中(具體而言在凹區之底部表面上)之每一循環中之淨成長。此循環過程可與同時發生沈積以及蝕刻反應之習知選擇性沈積過程區別。
下文之表B以及表C給出使用類似於表A配方之配方的沈積與蝕刻持續時間以及所得厚度的兩個實例。配方經不同地調諧以藉由增加Si3
H8
之部分壓力以及最佳化蝕刻劑部分壓力而調變沈積以及蝕刻速率兩者。
如上所述,在替代實施例中,代替上述之循環毯覆式沈積/選擇性蝕刻過程,可使用其他選擇性沈積技術來在凹區中以由下而上方式沈積分級應變源。
圖6說明在操作區塊300中提供具有凹區之基板。如圖6中之操作區塊310所指示,基板之凹區之單晶表面襯有異質磊晶應變襯墊。在內襯凹區之後,經內襯凹區填充有與應變襯墊相比具有減少應變之材料,如操作區塊320所指示。
圖7及圖8說明圖6之方法之實施例。圖7提供包括形成於半導體基板200(諸如矽晶圓)中之圖案化絕緣體210的示範性基板的示意性說明。絕緣體210以氧化物填充STI之形式並界定場隔離區域212,且相鄰於展示於閘極結構215之任一側上之凹入源極/汲極區域214,閘極結構215覆蓋基板200之通道區域217。為了說明目的,絕緣體210經展示為與凹入源極/汲極區域214分離,使得所有凹區表面由單晶矽界定。然而,應理解,在其他配置中,一些凹區表面可由絕緣體材料界定,如圖2所示。如圖7所說明,異質磊晶含矽材料(諸如SiGe、SiGe:C以及Si:C)之襯墊層225形成於基板200之亦具有絕緣體210之凹入源極/汲極區域214中。異質磊晶襯墊層225較佳選擇性以及異質磊晶地沈積於所述凹入源極/汲極區域214之單晶表面上。
根據另一實施例,異質磊晶襯墊層225可藉由以下方法而形成:在具有絕緣體區域以及凹入源極/汲極區域之混合基板上選擇性沈積含矽材料(諸如SiGe、SiGe:C或Si:C)之毯覆式層,以及選擇性蝕刻所述毯覆式層使得所沈積含矽材料僅保留在凹入源極/汲極區域中,如上文關於圖1至圖5D所述。熟習此項技術者將瞭解,含矽材料之毯覆式層實質上為場隔離區域212上之非晶形或多晶或非磊晶材料以及凹入區域之底部表面上之磊晶材料。凹入區域之單晶側壁亦由含矽材料之異質磊晶襯墊層225覆蓋,如圖7所示。凹入區域之底部表面上之磊晶材料以及側壁上之磊晶材料共同用於凹入區域之異質磊晶襯墊層225。在選擇性蝕刻之後,僅異質磊晶襯墊層225保留在凹入源極/汲極區域214中。
如圖7所示,異質磊晶襯墊層225內襯凹入區域,使得異質磊晶襯墊層225覆蓋凹入區域之全部側壁表面以及底部表面。較佳地,此異質磊晶襯墊層225實質上均一沈積於凹入區域中之暴露矽上。異質磊晶襯墊層225之異質磊晶含矽材料可在約350℃至1000℃之間的範圍內的溫度下沈積,且較佳在約400℃至800℃之間的範圍內。在另一實施例中,磊晶含矽材料在約400℃至750℃之間的範圍內的溫度下沈積,且較佳在約450℃至650℃之間的範圍內。根據另一實施例,異質磊晶襯墊層225可為具有應變誘發雜質濃度之分級層,所述濃度遠離凹入區域之底部以及側表面而降低。分級可為離散的或連續的。
如圖8中所說明,凹入區域之剩餘部分接著用填充劑260填充,直至在凹入源極/汲極區域214上達成目標厚度。填充劑260包括具有較低雜質(諸如Ge或C)濃度之磊晶材料,所述雜質將應變引入於異質磊晶襯墊層225中。根據實施例,填充劑260包括矽。在圖8中展示之所說明實施例中,填充劑260填充絕緣體210與通道區域217之間的凹區,使得填充劑260之上部表面實質上與絕緣體210之上部表面共面。然而,熟習此項技術者將容易瞭解,此目標厚度亦可低於或高於絕緣體210之頂部表面。熟習此項技術者將瞭解,填充有由異質磊晶襯墊225以及減少應變填充劑260之所形成之應變源的填充凹入源極/汲極區域214比具有均一矽合金之習知應變源更穩定,因為應變源具有降低整體濃度之應變誘發雜質材料(諸如Ge或C)。結構仍在通道217之邊緣處提供高應變位準,其為所需要的。舉例而言,對於包含SiGe之異質磊晶襯墊層225,Ge含量通常介於20原子%與50原子%之間,且填充劑260之Ge含量較佳小於約20原子%或更小。對於Si:C襯墊,C含量通常介於0.5原子%與4原子%之間,且填充劑260之C含量較佳小於約1原子%且低於襯墊層225。如圖8所示,可選封蓋層250可較佳藉由選擇性沈積技術而沈積於填充源極/汲極區域214上。在一個實施例中,封蓋層250可由Si、SiGe、SiGe:C或Si:C形成。封蓋層250較佳具有低於磊晶材料225之襯墊層的較低雜質濃度。
圖9說明在操作區塊400中提供具有凹區之基板。如操作區塊410所指示,基板之凹區的單晶表面襯有異質磊晶應變襯墊。在內襯凹區之後,執行再分佈退火以在凹區之下部彎角中形成小面(facet),如操作區塊420所指示。凹區接著填充具有與應變襯墊相比減少應變之材料,如操作區塊430所指示。
襯墊層可經退火以重分佈磊晶襯墊層材料,使得材料遷移至凹區之側壁處的彎角。通常,此退火導致磊晶材料漸縮(tapered),從而具有小面化側截面形狀。經退火磊晶材料通常在凹區底部處比頂部處寬。較佳覆蓋凹區之實質上所有側壁表面之經退火磊晶材料施加橫向應變至相鄰電晶體通道上。
圖10及圖11說明圖9之方法。在襯墊層225沈積於圖7所示之結構中之後,無論是否藉由選擇性沈積技術或循環毯覆式沈積/選擇性蝕刻或非選擇性沈積以及圖案化,基板200接著藉由將其加熱至約600℃與1100℃之間而進行退火。在一個實施例中,基板在介於650℃與900℃之間的溫度下退火。在另一實施例中,退火溫度介於約725℃與775℃之間。熟習此項技術者可取決於選定溫度而容易確定適當的退火持續時間,從而達成所要的再分佈。儘管以完全界定於半導體材料內之凹區(即源極/汲極區域214)說明,使得楔形異質磊晶材料230形成環狀,但熟習此項技術者將瞭解一或多個側壁表面可由場隔離材料來界
定,如圖2至圖5D之實施例所說明。如關於先前描述之實施例所述,凹入區域之側壁可由形成其之蝕刻、由後續清潔或磨圓步驟、或諸如薄磊晶層之額外內襯層(未圖示)來界定。
作為退火過程之結果,襯墊層225(展示於圖7中)中之矽以及摻雜劑原子遷移,且材料再分佈導致經退火異質磊晶材料230具有小面化側截面形狀,如圖10所示。自結晶觀點來看,小面化異質磊晶材料230為下伏於閘極節構215之通道區域217之兩側上的晶體小面之等效物。如圖10所說明,小面化異質磊晶材料230為實質上沿凹入區域之側壁漸縮的層。
此小面化磊晶材料230亦為無錯位且應變的,但其在退火之前具有比圖7之磊晶襯墊225高的合金含量。如圖所說明,小面化磊晶材料230位於相鄰於閘電極結構215下方之通道217處,且內襯或覆蓋緊靠通道之實質上所有至少凹區側壁,且較佳為凹入區域之所有單晶側壁表面。因此,應變小面化異質磊晶材料230施加應變至下伏於閘極結構215之通道區域217上。
在所說明實施例中,原始襯墊225之磊晶材料中之一些在退火之後保留在凹入區域之底部表面上。如圖10所示,底部襯墊280之經退火磊晶材料變薄,且可具有不均勻表面,且亦可與楔形側壁覆蓋異質磊晶材料230不連續。底部覆蓋之不連續性可減少凹區底部之應變,而在相鄰於通道表面之凹區頂部沒有任何效應。儘管在所說明實
施例中底部襯墊280之經退火磊晶材料與小面化異質磊晶材料230隔離,但應瞭解在其他實施例中(未圖示),底部襯墊之經退火磊晶材料將不與覆蓋側壁表面之小面化磊晶材料隔離。此隔離或沒有隔離可藉由(例如)調整沈積時間或藉由添加後磊晶沈積化學蝕刻步驟(例如,原位後磊晶沈積HCl蝕刻)而達成。
凹入區域之剩餘部分接著填充填充劑260,如圖11所說明。填充劑260具有比小面化異質磊晶材料230低的應變誘發雜質濃度。此填充劑層260可經成長以與基板200之頂部表面實質上共面,如圖11所示,或在其他實施例中低於或高於基板200之頂部表面。在<100>具有水平底面之凹區之矽基板的情況下,小面化異質磊晶材料230與填充劑260之間的介面處的小面角(facet angle)相對於凹入區域底部之水平面介於約25°-55°之間的範圍內。根據另一實施例,小面角介於約11°-72°之間的範圍內。應瞭解,在小面化異質磊晶材料230與填充劑260之間的介面可具有一些彎曲,且凹入區域內之整體應變源230、260在側壁處存在較高應變或較高雜質濃度以及在凹入區域之中心處存在較低應變或較低雜質濃度的意義上為逆行的。實際上,填充劑260可由無任何應變誘發雜質之Si形成,其僅包括電學摻雜劑用於傳導性。可選封蓋層(未圖示)可形成於填充劑260上。圖12為繪示使用圖9所說明之方法形成之小面化SiGe襯墊層的顯微圖。填充劑260(圖11)在顯微圖中標記為“Si封蓋”,且多晶矽成長繪示於閘極結
構上,其指示非選擇性沈積用於此實例。
應瞭解,因為較高度應變磊晶含矽材料280、230之體積由於使用薄內襯層而非用高度應變材料完全填充凹區之緣故而顯著減小,所以臨界厚度約束放鬆且應變施力以及熱預算中之實質增益產生。可調整磊晶含矽材料280、230之雜質含量,從而產生不同的應變量。可顯著增加過程溫度,從而導致成長速率之顯著增加。
雖然以上詳細描述揭露本發明之若干實施例,但應瞭解本揭露案僅為說明性的且並不限於本發明。應瞭解所揭露之特定組態以及操作可不同於上述組態以及操作,且本文所述之方法可用於不同於半導體元件之製造的上下文中。
10、20、30、40、45、50、300、310、320、400、410、420、430‧‧‧區塊
100‧‧‧基板
110‧‧‧絕緣體
112‧‧‧場隔離區域
114‧‧‧源極/汲極區域
115‧‧‧閘極結構
117‧‧‧通道區域
120‧‧‧毯覆式Si:C層
122‧‧‧毯覆式Si:C層
125‧‧‧毯覆式Si:C層
130‧‧‧毯覆式Si:C層
132‧‧‧毯覆式Si:C層
135‧‧‧毯覆式Si:C層
145‧‧‧分級磊晶層
150‧‧‧封蓋層
200‧‧‧半導體基板
210‧‧‧絕緣體
212‧‧‧場隔離區域
214‧‧‧源極/汲極區域
215‧‧‧閘電極
217‧‧‧通道區域
225‧‧‧襯墊層
230‧‧‧異質磊晶材料
250‧‧‧封蓋層
260‧‧‧填充劑
280‧‧‧底部襯墊
圖1為說明用於在基板之凹入源極/汲極區域中以由下而上方式選擇性形成應變磊晶半導體層之過程的流程圖。
圖2為包括形成於半導體基板中之凹入源極/汲極區域之部分形成半導體結構的示意性截面說明。
圖3為在執行包括在凹入源極/汲極區域之底部上磊晶沈積的摻碳矽膜之毯覆式沈積(blanket deposition)之後的圖2之部分形成半導體結構之示意性截面說明。
圖4為在執行用以自絕緣體以及凹入側壁區域移除摻碳矽之選擇化學氣相蝕刻過程之後的圖3之部分形成半導體結構之示意性截面說明。
圖5A至圖5D為在執行毯覆式沈積以及選擇蝕刻之其他循環、以由下而上方式沈積具有增加應變之層之後的圖4之部分形成半導體結構之示意性截面說明。
圖6為說明用於在凹入源極/汲極區域中形成應變襯墊層(liner layer)之過程的流程圖。
圖7及圖8為根據另一實施例在混合基板表面之凹入區域中形成包括含矽膜之襯墊層且用填充劑填充凹入區域之後的圖2之部分形成半導體結構之示意性截面說明。
圖9為說明用於在基板之凹入源極/汲極區域中形成小面化(faceted)應變襯墊層之過程的流程圖。
圖10及圖11為根據另一實施例在退火襯墊層且用填充劑填充凹入區域之後的圖6之部分形成半導體結構之示意性截面說明。
圖12為展示經退火SiGe襯墊層之顯微圖。
10、20、30、40、45、50‧‧‧區塊
Claims (52)
- 一種選擇性形成半導體材料之方法,包括:在化學氣相沈積腔室內提供基板,所述基板包括絕緣表面以及單晶半導體表面,其中所述單晶半導體表面包括凹區;以及在所述凹區中選擇性形成半導體應變源,其中所述半導體應變源經分級使得所述凹區內之所述半導體應變源之上部具有比下部高的應變量,且其中所述上部延伸至所述凹區之側壁。
- 如申請專利範圍第1項所述之選擇性形成半導體材料之方法,其中所述半導體應變源包含離散層。
- 如申請專利範圍第1項所述之選擇性形成半導體材料之方法,其中所述選擇性形成包括:在所述基板之所述絕緣表面上以及所述單晶半導體表面上毯覆式沈積半導體材料;以及自所述絕緣表面選擇性移除非磊晶半導體材料,以及自所述凹區之所述側壁選擇性移除磊晶材料,同時在所述凹區之底部留下磊晶材料。
- 如申請專利範圍第3項所述之選擇性形成半導體材料之方法,更包括在多個循環中重複所述毯覆式沈積以及所述選擇性移除,其中每一循環在所述凹區之所述底部添加某厚度之磊晶材料,且其中任一毯覆式沈積半導體材料層包括比所述凹區中之下伏毯覆式沈積半導體材料層高的摻雜劑濃度。
- 如申請專利範圍第3項所述之選擇性形成半導體材料之方法,其中所述毯覆式沈積包括非選擇性沈積。
- 如申請專利範圍第3項所述之選擇性形成半導體材料之方法,其中所述毯覆式沈積包括在所述絕緣表面上主要形成非晶形半導體材料。
- 如申請專利範圍第3項所述之選擇性形成半導體材料之方法,其中所述毯覆式沈積包括將三矽烷以及碳前驅體流動至所述化學氣相沈積腔室中。
- 如申請專利範圍第1項所述之選擇性形成半導體材料之方法,其中所述半導體材料包括摻碳矽。
- 一種選擇性形成異質磊晶半導體材料之方法,包括:在基板之單晶半導體區域中之所形成的凹區之底部以及側壁表面上沈積半導體材料;以及自所述凹區之所述側壁表面選擇性移除所述半導體材料之部分,同時在所述底部表面上留下所述半導體材料之異質磊晶層;以及重複所述沈積以及所述選擇性移除,其中所述半導體材料之後續沈積異質磊晶層包括與所述半導體材料之先前沈積異質磊晶層相比而言不同之應變誘發雜質之濃度。
- 如申請專利範圍第9項所述之選擇性形成異質磊晶半導體材料之方法,其中所述半導體材料之所述沈積層離散地分級。
- 如申請專利範圍第9項所述之選擇性形成異質磊晶 半導體材料之方法,其中所述沈積包括在每一循環中將所述半導體材料之所述異質磊晶層形成為介於1nm與100nm之間的厚度。
- 如申請專利範圍第9項所述之選擇性形成異質磊晶半導體材料之方法,其中所述凹區中之所述半導體材料之所述異質磊晶層施加應變至所述基板之相鄰區域上。
- 如申請專利範圍第12項所述之選擇性形成異質磊晶半導體材料之方法,其中所述應變在所述凹區內之所述凹區之頂部處最高。
- 如申請專利範圍第9項所述之選擇性形成異質磊晶半導體材料之方法,其中所述半導體材料包括摻碳矽。
- 如申請專利範圍第9項所述之選擇性形成異質磊晶半導體材料之方法,其中所述凹區內之所述半導體材料之最高程度應變處於所述凹區之頂部處。
- 如申請專利範圍第9項所述之選擇性形成異質磊晶半導體材料之方法,其中所述半導體材料填充所述凹區。
- 如申請專利範圍第9項所述之選擇性形成異質磊晶半導體材料之方法,其中所述半導體材料之所述異質磊晶層之至少一最上層為拉伸應變的。
- 一種在包括單晶側壁表面的凹區中形成半導體材料之方法,包括:提供基板,其中形成有絕緣區域以及所述凹區;沈積異質磊晶含矽材料之襯墊層以覆蓋所述凹區之實質上所有單晶側壁表面,所述襯墊層包括應變誘發雜 質,所述襯墊層部分填充所述凹區;以及藉由將填充劑沈積於所述襯墊層上而用包括含矽材料之所述填充劑覆蓋所述襯墊層,從而在所述凹區中形成半導體材料,所述含矽材料具有比所述襯墊層低的所述雜質之濃度。
- 如申請專利範圍第18項所述之在凹區中形成半導體材料之方法,其中所述沈積包括用矽鍺內襯所述凹區的所述單晶側壁表面。
- 如申請專利範圍第18項所述之在凹區中形成半導體材料之方法,其中沈積所述襯墊層以及覆蓋所述襯墊層導致凹區用分級之矽鍺材料填充,其中鍺的濃度遠離所述凹區之底部以及側部而減少。
- 如申請專利範圍第18項所述之在凹區中形成半導體材料之方法,更包括將封蓋層沈積於所述填充劑上,所述封蓋層包括選自由以下各物組成之群的材料形成:矽、矽鍺、摻碳矽以及摻碳矽鍺。
- 如申請專利範圍第18項所述之在凹區中形成半導體材料之方法,其中:沈積所述襯墊層包括沈積分級之矽鍺層,其中鍺的濃度遠離所述凹區之底部以及側部而減少;以及覆蓋所述襯墊層包括在沈積所述襯墊層之後用矽填充所述凹區。
- 如申請專利範圍第22項所述之在凹區中形成半導體材料之方法,其中所述分級之矽鍺層包括離散分級之層。
- 如申請專利範圍第22項所述之在凹區中形成半導體材料之方法,其中所述分級之矽鍺層為連續分級之層。
- 如申請專利範圍第18項所述之在凹區中形成半導體材料之方法,其中沈積所述襯墊層包括用摻碳矽內襯所述凹區。
- 如申請專利範圍第25項所述之在凹區中形成半導體材料之方法,更包括將封蓋層沈積於所述填充劑上,所述封蓋層包括選自由以下各物組成之群的材料:矽、矽鍺、摻碳矽以及摻碳矽鍺。
- 如申請專利範圍第18項所述之在凹區中形成半導體材料之方法,其中所述凹區中之所述襯墊層異質磊晶含矽材料施加橫向拉伸應變至所述基板之相鄰區域上。
- 如申請專利範圍第27項所述之在凹區中形成半導體材料之方法,其中所述相鄰區域為電晶體通道區域。
- 如申請專利範圍第18項所述之在凹區中形成半導體材料之方法,更包括在沈積所述襯墊層之後且在用具有所述雜質之所述較低濃度的所述含矽材料覆蓋所述襯墊層之前使所述基板退火。
- 如申請專利範圍第29項所述之在凹區中形成半導體材料之方法,其中退火包括將所述基板加熱至介於650℃與900℃之間的溫度。
- 如申請專利範圍第29項所述之在凹區中形成半導體材料之方法,其中在所述退火之後,異質磊晶含矽材料覆蓋所述凹區之實質上全部側壁表面。
- 如申請專利範圍第29項所述之在凹區中形成半導體材料之方法,其中所述退火導致所述襯墊層之所述異質磊晶含矽材料的一部分遷移至所述凹區之彎角。
- 如申請專利範圍第29項所述之在凹區中形成半導體材料之方法,其中在所述退火之後,所述襯墊層具有小面化側截面形狀。
- 如申請專利範圍第33項所述之在凹區中形成半導體材料之方法,其中所述襯墊層與所述填充劑之間的介面相對於凹區之底部較佳在25°-55°之範圍內。
- 如申請專利範圍第33項所述之在凹區中形成半導體材料之方法,其中在所述退火之後,所述襯墊層實質上沿凹區之側壁漸縮。
- 一種半導體元件,包括:基板中之凹區;異質磊晶含矽襯墊,其覆蓋所述凹區之實質上所有單晶側壁表面,所述襯墊包括更改晶格常數之雜質;填充劑,其形成於所述襯墊上且填充所述凹區,其中所述填充劑包括含矽材料,所述含矽材料具有比其上形成所述填充劑之所述襯墊低的所述雜質之濃度;以及電晶體通道,其相鄰於所述凹區。
- 如申請專利範圍第36項所述之半導體元件,其中所述襯墊包括矽鍺。
- 如申請專利範圍第37項所述之半導體元件,更包括形成於所述填充劑上之封蓋層,所述封蓋層包括選自由 以下各物組成之群的材料:矽、矽鍺、摻碳矽以及摻碳矽鍺。
- 如申請專利範圍第36項所述之半導體元件,其中所述襯墊包括摻碳矽。
- 如申請專利範圍第39項所述之半導體元件,更包括形成於所述填充劑上之封蓋層,所述封蓋層包括選自以下各物組成之群的材料:矽、矽鍺、摻碳矽以及摻碳矽鍺。
- 如申請專利範圍第36項所述之半導體元件,更包括形成於所述填充劑上之封蓋層,所述封蓋層包括比覆蓋所述凹區之所有側壁表面之所述異質磊晶襯墊低的所述雜質之濃度。
- 如申請專利範圍第36項所述之半導體元件,其中所述襯墊與所述填充劑之間的介面漸縮,且所述襯墊在所述凹區之底部表面上為不連續的。
- 如申請專利範圍第36項所述之半導體元件,其中所述襯墊漸縮,且所述襯墊包括所述凹區之底部表面上比所述凹區之所述側壁表面上之所述襯墊薄的部分。
- 如申請專利範圍第36項所述之半導體元件,其中所述襯墊為拉伸應變的。
- 如申請專利範圍第36項所述之半導體元件,其中所述襯墊施加壓縮應變至所述電晶體通道上。
- 如申請專利範圍第45項所述之半導體元件,其中所述襯墊為矽鍺。
- 一種半導體元件,包括: 凹區,其用異質磊晶應變源材料填充,所述凹區內之所述應變源材料之上部具有第一雜質濃度,所述凹區內之所述應變源材料之下部具有第二雜質濃度,其中所述第一雜質濃度高於所述第二雜質濃度,且所述上部延伸以接觸所述凹區之側壁;以及電晶體通道,其相鄰於所述凹區。
- 如申請專利範圍第47項所述之半導體元件,其中所述應變源材料在頂部表面具有比在底部表面高的雜質濃度。
- 如申請專利範圍第47項所述之半導體元件,其中所述應變源材料為矽鍺。
- 如申請專利範圍第47項所述之半導體元件,其中所述應變源材料為摻碳矽。
- 如申請專利範圍第47項所述之半導體元件,其中所述應變源材料包括離散層,其中每一離散層具有高於其下方之層的雜質濃度。
- 如申請專利範圍第47項所述之半導體元件,其中所述應變源材料為拉伸應變的。
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US7759199B2 (en) | 2010-07-20 |
US20090075029A1 (en) | 2009-03-19 |
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