TW439151B - Method for forming conductive layer using atomic layer deposition process - Google Patents

Method for forming conductive layer using atomic layer deposition process Download PDF

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Publication number
TW439151B
TW439151B TW87106228A TW87106228A TW439151B TW 439151 B TW439151 B TW 439151B TW 87106228 A TW87106228 A TW 87106228A TW 87106228 A TW87106228 A TW 87106228A TW 439151 B TW439151 B TW 439151B
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Taiwan
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layer
metal
gas
patent application
atomic layer
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TW87106228A
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Chinese (zh)
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Sang-Bom Kang
Yun-Sook Chae
Chang-Soo Park
Sang-In Lee
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Samsung Electronics Co Ltd
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    • CCHEMISTRY; METALLURGY
    • C23COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23CCOATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/44Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating
    • C23C16/455Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for introducing gases into reaction chamber or for modifying gas flows in reaction chamber
    • C23C16/45523Pulsed gas flow or change of composition over time
    • C23C16/45525Atomic layer deposition [ALD]
    • C23C16/45527Atomic layer deposition [ALD] characterized by the ALD cycle, e.g. different flows or temperatures during half-reactions, unusual pulsing sequence, use of precursor mixtures or auxiliary reactants or activations
    • C23C16/45534Use of auxiliary reactants other than used for contributing to the composition of the main film, e.g. catalysts, activators or scavengers
    • CCHEMISTRY; METALLURGY
    • C23COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23CCOATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/06Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the deposition of metallic material
    • C23C16/08Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the deposition of metallic material from metal halides
    • CCHEMISTRY; METALLURGY
    • C23COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23CCOATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/22Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the deposition of inorganic material, other than metallic material
    • C23C16/30Deposition of compounds, mixtures or solid solutions, e.g. borides, carbides, nitrides
    • C23C16/42Silicides
    • CCHEMISTRY; METALLURGY
    • C23COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23CCOATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/44Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating
    • CCHEMISTRY; METALLURGY
    • C23COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23CCOATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/44Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating
    • C23C16/455Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for introducing gases into reaction chamber or for modifying gas flows in reaction chamber
    • C23C16/45561Gas plumbing upstream of the reaction chamber
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System
    • H01L21/28518Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System the conductive layers comprising silicides
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System
    • H01L21/28556Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System by chemical means, e.g. CVD, LPCVD, PECVD, laser CVD
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors

Abstract

A method for forming a conductive layer using an atomic layer deposition process. A sacrificial metal atomic layer is formed on a semiconductor substrate by reacting a precursor containing a metal with a reducing gas, and a metal atomic layer where metal atoms dissolved from a metal halide gas is deposited is formed on a semiconductor substrate by reacting the sacrificial metal atomic layer with a metal halide gas. Also, a silicon atomic layer may be additionally formed on the metal atomic layer using a silicon source gas, to thereby alternately stack metal atomic layers and silicon layers.

Description

4 4 Printed by the Consumers ’Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs A7 B7 V. Description of the Invention (I) Background of the Invention 1. Field of the Invention The present invention relates to a method for forming a conductive layer of a semiconductor device. A method of forming a semiconductor conductive layer during the deposition process. 2. Description of related technologies When the integration degree of a semiconductor device increases, the design scale decreases. In this way, the aspect ratio of the contact hole becomes very high, and the junction depth becomes very shallow. The junction depth depends directly on the short channel effect of a Mos transistor. That is, a MOS transistor suitable for high-integration semiconductor devices requires a short channel length and a shallow source / drain region, that is, the junction depth must be very shallow to increase the Performance of MOS transistor with short channel. A connection technology for connecting a shallow junction (shaU〇w''uncU〇n) and a metal connection line requires a metal barrier layer, which prevents the metal connection line from penetrating the shallow junction, that is, prevents the node spikes ( juncti〇n spiking) phenomenon. Titanium nitride (TiN) layers are widely used for metal barrier layers. An ohmic layer ', for example, a titanium silicide layer, intervenes between a metal barrier layer and a node. A titanium silicide layer with a melting point of 1M0 ° C, a resistivity of π ~ 16 / z Ω-cm, and a resistance of 0.6eV is an N-type impurity layer. It is widely used as an ohmic layer or a connection line. The comparative titanium layer is used as an ohmic layer. A titanium layer is formed on the junction, that is, the sand substrate (impurity layer) is doped with impurities and then annealed to react with the titanium layer. As mentioned above, a common method for forming metal connection lines is to form an intermediate dielectric layer on the impurity layer. This intermediate dielectric layer is patterned on the layout. 3 This paper is applicable to the Chinese National Standard (CNS) A4 specification (2 丨〇X 297 public love)-yL · <-^^ 1 tt ^^ 1 cl f 〆 »nn In n 4 · ^^ 1 nn 1 ^^ 1 I 71,« I (Please read the notes on the back first (Fill in this page again) A7 B7 V. Description of the invention (y) In order to form a connecting hole in a predetermined exposed area on the impurity layer. Also, the 'ohmic layer, the metal barrier layer, and the metal wiring are sequentially formed on the entire surface of the structure obtained by forming the connection hole. After forming a titanium layer on the exposed impurity layer, the titanium layer is annealed, or a titanium silicide layer is formed directly on the impurity layer to obtain an ohmic layer. The titanium silicide layer must be formed at a temperature low enough to suppress damage to the impurity layer. A proposed method for forming a titanium silicide layer is a plasma-enhanced chemical vapor deposition (PECVD) process, which is published by 1. Lee et al. In J. Electrochem · Soc., Vol. 139, No. 4, 1992 'pp. 1159-1165 "Electron Pad Enhanced CVD of TiSh Pavement on Oxide Layout Patterned Wafer", Alan E_Morgan et al., Published in J. Vac • Sci · Technol · B4 (3), 1986, pp.723-731 "Characteristics of Plasma Strengthened CVD Titanium Silicide". However, when a titanium silicide layer is formed on a connection hole with a high aspect ratio on a highly integrated semiconductor device, due to the characteristics of the plasma, poor step coverage is not shown. At the same time, the method of forming a silicide layer using a low pressure CVD (LPCVD) process at 600 ° C or higher was proposed by V. Ilderem et al. And G 'Reynolds et al. (See "Low Pressure CVD Titanium Silicide" Optimal Deposition Parameters "J · Electrochem-Soc-, 1988, ρρ · 2590-2596 and" Selective Titanium Silicide for Low Pressure CVD "" J · App:! · Phys. 65 (8), 1989, pp. 3212 -3218). However, when a titanium silicide layer is formed at a temperature of 600 ° C or higher, the silicon consumption of the impurity layer and the titanium layer is increased, thereby deteriorating the leakage current characteristics of the junction. LPCVD obtains suitable titanium silicide layers for highly integrated semiconductor devices that require shallow junctions. Essentials of Invention 4 The paper size is applicable to the Chinese National Standard (CNS) A4 specification (210 mm) (Please read the unintentional matter on the back before filling out (This page) Order --------- Line-Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 4391 5 A7 B7 V. Invention Description (3) The object of the present invention is to provide a product at 500 ° C or lower Conductive layer formation using atomic layer deposition process to increase step coverage at temperature Method ° Accordingly, according to one aspect of the present invention, the above-mentioned objective is achieved. 'A sacrificial metal atom layer is formed on a semiconductor substrate. This sacrificial metal atom layer reacts with a metal halide gas, and the sacrificial metal atom layer is removed to remove The metal atom layer originally dissolved in the metal halide gas is deposited to form such a metal atom layer. This semiconductor substrate is a silicon substrate and has a predetermined surface area, and the nodes on the semiconductor layer are doped with impurities to form an impurity layer. An intermediate dielectric layer layout pattern having a connecting hole exposing a predetermined region of an impurity layer can be formed on a semiconductor substrate. The sacrificial metal atom layer and the metal atom layer are on the initial metal atom layer, that is, on the semiconductor substrate The metal atomic layer originally formed thereon was formed at least once in succession, so a metal atomic layer containing a plurality of metal atomic layers was formed on the semiconductor substrate. Here, the initial sacrificial metal atomic layer, that is, the sacrificial firstly formed on the semiconductor substrate Metal atomic layer whose formation must completely cover the entire exposure The surface of the impurity layer. If the surface of the impurity layer exposed by the connection holes cannot be completely covered by the original sacrificial metal atom layer, the metal halide gas will react with and damage the impurity layer. In this way, an initial sacrificial metal layer completely covering the impurity layer, It can be formed before the initial sacrificial metal atom layer. At this time, when the initial sacrificial metal layer is formed, the semiconductor substrate is preferably heated to 300 ~ 500 ° C. The material of the initial sacrificial metal layer should be the same as that of the initial sacrificial metal. The atomic layer is the same. The initial sacrificial metal layer or the initial sacrificial metal atomic layer is made by reacting the sacrificial metal source gas and the reducing gas with each other. In this case, it is preferable to use Hz or SiH4 as the reducing gas. 5 This paper size is in accordance with Chinese National Standard (CNS) A4 specification m〇X 297 malea) (Please read the notes on the back before filling this page) Words:% Printed by the Intellectual Property Bureau, Ministry of Economic Affairs, Consumer Consumption Cooperative, 1 439151 1 A7 __B7____ 5. Explanation of the invention (ip At the same time, the metal halide gas must have a Gibbs free energy lower than that consisting of the metal atoms of the original sacrificial metal atomic layer and the halogen atoms of the metal halide gas. In other words, the metal atoms of the initial sacrificial metal atomic layer must be able to combine with the halogen atom to replace the metal atom of the metal halide with the halogen atom. For example, to form a metal atomic layer composed of titanium on a semiconductor substrate It is preferred to use the following metal halide gas: TiCU gas, TiL · gas, TiBn gas, or Tih gas. At this time, if the metal halide gas is TiCL · gas, the sacrificial metal atomic layer is preferably A1 layer 1 La layer, Pr layer, In layer, Ce layer, Nd layer or Be layer. At this time, the Gibbs free energy of TiCL · gas is lower than Al2Cl6, LaCh gas, PrCh gas, Ir ^ Ch gas, Ce. Ch gas, NdCls gas, BeCL · gas. Similarly, if TiL · gas is used to form a metal atomic layer composed of titanium on a semiconductor substrate, the preferred sacrificial metal atomic layers are the A1 layer, the Zr layer, and the Hf layer. The Gibbs free energy of TiL · gas is lower than AhL · gas, Zrl · gas, or HfL · gas. Different metal halide gases, such as TaCl5 gas, TaL · gas, TaBrs gas, TaF5 gas, HfCU gas, HfL · Gas, HfBn gas, HfF4 gas, ZrCU gas., Zrl · gas, ZrBn gas, or Zrh. Gas' can be used to form a corresponding metal atomic layer on a semiconductor substrate. As mentioned above, if a metal halide gas is used for sacrificial Metal atomic layer, or the structure surface formed by the initial sacrificial metal layer and the initial sacrificial metal atom layer, then, the metal atom on the sacrificial metal atom layer and the metal atom of the initial sacrificial metal layer and the metal halide gas. Halogen atom 'generates a volatile gas. In this way, gold 6 in metal halides (please read the precautions on the back before filling this page) i ^---- --- Order -------- Line — The paper is printed by the employees of the Intellectual Property Bureau of the Ministry of Economic Affairs, and the paper is printed in accordance with the Chinese National Standard (CNS) AJ specification (210 X 297 mm). Printed by Employee Consumer Cooperative

^ 3 91 5 I A7 B7 V. Description of the invention (<) Metal atoms, for example, transition metal atoms, are deposited on a semiconductor substrate to form a metal atom layer. The sacrificial metal atomic layer and the metal atomic layer are preferably sequentially formed when the semiconductor substrate is heated to 300 to 500 ° C. According to another aspect of the object achieved by the present invention, a sacrificial metal atom layer and a metal atom layer are formed on a semiconductor substrate in the same manner as in the above aspect, and a silicon atom layer is formed on the metal atom layer. Here, before the formation of the first sacrificial metal atom layer on the semiconductor substrate, the initial sacrificial metal layer is formed on the semiconductor substrate in the same manner as described above. Then, the sacrificial metal atomic layer, the metal atomic layer, and the silicon atomic layer are sequentially stacked on the structure formed by the initial silicon atomic layer at least once, so the metal atomic layer and the silicon atomic layer are alternately stacked on the semiconductor substrate. At this time, when the thickness of a metal atomic layer and the thickness of a silicon atomic layer are properly controlled, a metal silicide layer having a desired composition ratio is formed. Alternatively, the silicon atomic layer and the metal atomic layer are sequentially formed on the semiconductor substrate at least once, so that the silicon atomic layer and the metal atomic layer are alternately stacked. Then, if necessary, the obtained structure in which silicon atomic layers and metal atomic layers are alternately laminated is annealed to form a metal silicide layer capable of improving the connection resistance. The preferred solution is through rapid thermal processing (RTP) annealing, a furnace annealing or vacuum annealing. And when the silicon atomic layer is formed, the semiconductor substrate is heated to 300 ~ 500 ° C. The silicon atomic layer is formed using a precursor gas containing sand atoms. The sand source gas is best to use the following gases: SiH4, S12H6, (CH3) 3SiC ξ CSi (CH) 3, ((CEh), Si) 2CH2, (CH small CSUCH + Cl '(C4H9) SiCL ·, (CH3) 3SiN (C2H5) 2, (CH3) 2SiCl2 '((CH: 〇2Si-) n, (CsHshSiCh, (C6Hs) 2SiH2, 7) This paper size applies to China National Standard (CNS) A4 specifications (210 x 297 mm)- Γ I--II I --- {. 机 I ------- Order --------- 1 (Please read the precautions on the back before filling this page) S1I 蘧 A7 B7 V · Description of the invention () GHsSiCh, Cl3SiSiCl3, (CH3) 3SiSi (CH3) 3, CHdiChH, (CH3) (C6H5) Sia2, CsHsSiCb, SiBn, SiCU, S1F4, SiL ·, (C32Hl6N8) SiCl2, Si (Si (CH; ) 3) 4, Si (CH3) 4, CiLSiCh, HSiCh ′ (C2H5> SiCn, CF3Si (CH3) 3, (CH〇3SiCl, (CHASiH, (CH3) 3SiC = CH '(C5H5) Si (CH3) 3, (C5 (CH3) 5) Si (CH3) 3, (C6H5) 3SiCl, (C6H5) 3Sm, ((CH3) 2N) 3CH, CH port CHSiCh, etc.) According to the present invention, a metal layer with excellent step coverage or The metal silicide layer can be formed on a semiconductor substrate having a high aspect ratio connection hole at 500 ° C or lower. Thus, in manufacturing a highly integrated semiconductor device requiring a shallow junction, a conductive layer having excellent reliability, that is, a metal barrier layer or an ohmic layer having excellent reliability, is formed. The description of the figure describes the best implementation in detail For example, referring to the following related figures, the above-mentioned objects and advantages of the present invention will be very obvious: Figure 1 is a flowchart illustrating the processing sequence of an embodiment of the invention; Figure 2 is a timing diagram illustrating an embodiment of the invention; Figure 3 is A flowchart illustrating a processing sequence of another embodiment of the present invention; FIG. 4 is a timing diagram illustrating another embodiment of the present invention; FIG. 5 is a diagram illustrating related devices used in the embodiment for preparing a conductor layer of the present invention; FIG. 6扫描 Scanning electron microscope (SEM) photo of the cross section of the titanium layer in an embodiment of the present invention; Figure 7 shows the composition of the titanium layer in Figure 6 shown by X-ray fluorescence analysis. 0 $ (Please read the precautions on the back first (Fill in this page again) Order --------- line '. Printed by the Intellectual Property Bureau of the Ministry of Economic Affairs, Consumer Cooperatives This paper is printed in accordance with China National Standard (CNS) A4 (210 X 297) (%) Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs ^ S i _____B7_; _ V. Description of the invention (°)) Comparative description of the embodiment Figure 5 The device used to form the conductive layer of the present invention includes a reaction chamber 51 A susceptor 53 installed on the bottom of the reaction chamber 51 to fix the semiconductor substrate 55, a nozzle 57 installed on the susceptor 53 to inject a reaction gas to the reaction chamber 51, and a vacuum pump 59 connected to the reaction chamber 51 to control its pressure . Here, the spray head 57 includes two independent gas inlets A and B. Through the gas inlet A, a metal source gas and an inert gas are injected into the reaction chamber 51; through the gas inlet B, a silicon source gas, a sacrificial metal source gas, and a reducing gas are injected into the reaction chamber 51. Before reaching the reaction chamber 51, the reaction gas is suppressed in the injection port A or B. Injector A, the injection of metal source gas and inert gas is controlled by the first and second valves VI and V2, respectively. Injector B, the injection of silicon source gas, sacrificial metal source gas, and reducing gas are respectively controlled by the first The third, fourth and fifth valves V3, V4 and V5 are controlled respectively. Figures 1, 2 and 5 depict an embodiment of the present invention in which a node of doped impurities, that is, an impurity layer, is formed on a semiconductor substrate, for example, a predetermined area on a surface of a silicon substrate. For highly integrated semiconductor devices, the source / drain regions of the impurity layer corresponding to the MOS transistor must be flawed to a depth of 0.1 Aim or less. This is because the short channel effect of the MOS transistor is closely related to the junction depth. The lower the junction depth of the impurity layer, the more significant the short channel effect of the transistor. An intermediate dielectric layer is formed on the entire surface of the resulting structure where the impurity layer is formed, and the intermediate dielectric layer is patterned in a layout to form a connection hole exposing a predetermined region of the impurity layer. At this time, the integration degree of the semiconductor device is increased, the thickness of the intermediate dielectric layer is increased, and the diameter of the connection hole is reduced. Thus, as the integration degree of the semiconductor device increases, the aspect ratio of the connection hole also increases. The semiconductor substrate 55 forming the connection hole is contained in the shape 9 A7 (please read the note on the back? Matters before filling out this page) Order. -Line. This paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm) Printed by the Consumer Goods Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs A7 _B7_ V. Description of the Invention (忿) The reaction chamber susceptor 53 of the device forming a conductive layer. At the same time, in the processing program, η 値 is initialized to zero, and at the same time, κ 决定, which displays the required number of processing cycles, is determined (step 10). Next, if the temperature Ts of the semiconductor substrate 55 is controlled to 3 to 550 t, the second, fourth, and fifth valves V2, V4, and V5 are opened, and the emotional gas, the sacrificial metal source gas, and the reducing gas are injected into the 51 chamber within a predetermined time. Thus, an initial sacrificial metal layer is formed on the entire surface of the semiconductor substrate 55 where the connection hole is formed (step 11). The sacrificial metal source gas and the reducing gas are mixed with each other in the gas inlet B, but they cannot react with each other due to the low temperature of 100 ~ 150 ° C in the gas inlet B. At this time, the pressure in the reaction chamber 51 is controlled to 10 torr or lower. The initial sacrificial metal layer is preferably a metal layer that reacts with a metal source gas that forms a desired atomic layer in a subsequent process. The metal halide gas contains a transition metal and a halogen. For example, in order to form a titanium metal atomic layer, the metal halide preferably contains titanium metal, that is, TiCh, TiL ·, TiBn, or T1F4 is a desired metal halide gas. Similarly, if T1CI4 is used for a metal halide gas, the Al, La, Pr, In, Ce, Nd or Be layer is the required initial sacrificial metal layer. At this time, Ai is the more preferred initial sacrificial metal layer. Because the combination of different precursors such as aluminum and chlorine has the highest Gibbs free energy, as shown in Table la. Preferably, argon and nitrogen are used as the inert gas, and hydrogen is used as the reducing gas. The reducing gas reduces the sacrificial metal source gas. The Gibbs free energies for different metal halide gases at an absolute temperature of 700 ° K (427 ° C) are listed in Tables la, lb, 2, 3 and 4. 10 (Please read the precautions on the back before filling this page) I 丨 ___ Speech Line-This paper size is applicable to China Store Standard (CNS) A4 (210 X 297 mm) A7 B7 V. Description of the Invention) Ministry of Economic Affairs Employees of the Intellectual Property Bureau printed a table of cooperatives la Gibbs free energy compounds containing different metal halides gas at 42TC Gibbs free energy (kilojoules / mole) Compound Gibbs free energy (kilojoules / Moore) Compound Gibbs Free Energy (KJ / Mole) AI2C! 5 -1121.9 HfCI3 -626.7 BeCI2 -373.1 ThCI4 -895.8 EuCI3 -621.6 BC 丨 3 -367.7 UCI5 -811.9 YbCl3 -621.5 SiCI3 -365.7 HfCI.- 804.7 K2CI2 -609.8 SnCl4 -362.3 ZrCI4 -777.6 Rb2CI2 -607.6 [nCI3 -335.8 LaC [] -708.9 Li2CI2 -597.8 aici2 -305.5 PrCI3 -706.9 SiCI4 -569.6 butylaCI3 -300.1 ln2Clg -703.7 aici3 -550.1 ΟθΙΟ -699.5 Fe2Cls -526.8 MnCI2 -286.4 NdCI3 -696.6 巳 aCl2 -524.3 WCI5 -235.6 Be2CI4 -692.6 SrCI2 -498.1 CsCI -276.7 TiCI4 -678.3 TaC ^ -497.5 ZnCI2 -273.5 GdCI3 -674.3 CsCIt -489.1 WCI3-26b. -462.1 T i2CI2 -259.8 HoC! 3 -659.7 VaCla -447.2 GaCl: -258.4 ErCI3 -651.7 GeCL -410.8 SbCl5 -249.9 Cs2CI2 -644.1 MgCI, -407.8 Cu.CU -242.9 TmCI3 -641.5 Fe2CI4 &quot; 406.5 PC 丨 3 -242.3 TaCI3- 636.6 GaCI3 -388.6 FeCI3 -240.6 Π (Please read the precautions on the back before filling in this page) 'Clothing -------- Order ------ Thread &lt; This paper size applies to China National Standard (CNS ) A4 specification (210 X 297 mm) A7 ____ ί £ V. Description of the invention ((0) Table lb Gibbs free energy compounds of different metal halide gases containing chlorine at 427 ° C Gibbs free energy (kilojoules) / Mole) Compound Gibbs Free Energy (KJ / Mole) Compound Gibbs Free Energy (KJ / Mole) lnCI2 -240..2 CaCS -165.1 NiCI2 -101.8 BiCI3 -238.5 TeCI4 -136.4 HCI- 98.7 丨 AsCI3 -231.4 HgCI2 -136.2 SeCI2 -50.5 SnCI2 -215.8 TeCI2 -134.6 BiCI -30.9 巳 aC 丨 -198.5 CoCt2 ^ 125.2 巳 eCl ~ 6.2 | SiCI2 -195.5 GaCI -123.1 AgC! 29.6 SrCi '-181.5 AiCl ·- m.6 BCl · 74.3 · FeCl2 -174.5 BCi2 -109.9 SiCS 123.7 (Please read the precautions on the back before filling this page) Ordered by the Intellectual Property Bureau of the Ministry of Economic Affairs, printed by the cooperative. Table 2 Gibbs Free Energy Compounds with Different Metal Halide Gases Containing Iodine at 427 ° C Gibbs Free Energy (KJ / Mole) Compound Gibbs Free Energy (kilojoules / mole) Compound Gibbs free energy (kilojoules / mole) Thl4 -512 Zrl4 -409 Til, -320 Al2is -510 Hfl, -405 Pbl4 -266 Κ2ί2 -480 Dy 丨 3 -402 Mgl2 -239 La 丨 3 -457 Tm 丨 3 -399 Cul -237 Prl] -443 Gdl3 -388 Cs! -220 Cel3 -442 Bal2 -38.0 Tal5 -202 Ndl3 -438 ui, -377 SiL -150; Li2J2 -427 Srl2 -353 HI -11.8 E 「丨 3 -410 Cal , -338-12 This paper size is applicable to the Chinese Family Standard (CNS) A4 (210 X 297 mm) The system of employee consumer cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 4391 5 1 ^ A7 __B7 V. Description of the invention (f I) Table 3 Gibbs free energy compound of different metal halide gases containing bromine at 427 ° C Gibbs free energy (kJ / mole) Compound Gibbs free energy (KJ / Mole) Compound Gibbs Free Energy (KJ / Mole) Al2Brs -860 HoB 「3 -567 CaBr, -435 Mg2Br4 -764 Ε」 Β γ3 -566 PbB 「4 -428 ThBr, -743 Tm 巳「 3 -563 Ta8r5 • 424 HfBr4 -639 TbB 「3 -559 EuB」 2 -413 ZrBr, -627 DyB 「3 -559 SiBr4 -387 LaBr3 -621 GdBr3 -551 Cu3 巳 r3 -187 CeBr3 -646 Li2Bf2 -534 WBrs -139 PrBr3 -612 TiB 「4 -527 HBr -58.6 UBr4 -602 Na2Br2 -510--NdBr3 -598 SrBr2 -453--Table 4 Different fluorine-containing metals Gibbs free energy of compounds of halides at 427 ° C Gibbs free energy (kJ / mole) Compound Gibbs free energy (kJ / mole) Compound Gibbs free energy (kJ / mol) Ear) AI2Fs -2439 HfFd -1592 Li / 3 -1457 UFa -1958 ZrF4 -1587 P 「F] -1231 TaF5 -1687 -1581 AsF5 -1080 ThF, -1687 SiF, -1515 CuF, -287.3 Mg2F4 -1624 wf5- 1513 HF -277.1 NbFs' -1607 TiF4 -1467--13 (Please read the meanings on the back before filling out this page) c ------- tr-i This paper size applies Chinese National Standard (CNS) A4 Specifications (210 X 297 mm) Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs' 4391 51 Δ7 ------ B7_ V. Description of the invention (\ l) Suitable for forming the required metal source on the semiconductor substrate The metal source gas layer and the initial sacrificial metal layer, may be selected from Table 1-4. For example, in order to use a titanium atomic layer as a metal atomic layer, Al, La, Pr, In, Ce, Nd, Be can be a required initial sacrificial metal layer, and TiCl · gas can be a required metal source gas. The A1 layer is formed as a sacrificial metal source gas for the initial sacrificial metal layer, and preferably contains the A1 precursor, for example, (C4H &lt; 〇2AlH, (C4H4A1H, (C2H5) 3A, (CH + Al, A1H3N (CH small , (CH3) 2A1H, or (CH small C2H5N: A1H3. Similarly, the La layer used as the sacrificial metal source gas for the initial sacrificial metal layer is preferably a precursor containing La, for example, (C5H5) 3La or (C2H7C4EU: bLa, forming the Pr layer as the sacrificial metal source gas for the initial sacrificial metal layer, is a precursor containing Pr, such as (C5H03Pr or (C3H7GH small Pr.) Similarly, forming the In layer as the initial sacrificial The sacrificial metal source gas of the metal layer is preferably a precursor containing In, for example, GtLIn, (C.H3) 5C5In, (C2H5) 3In, or (CH small In.) Also, the Ce layer is formed as an initial sacrificial The sacrificial metal source gas of the metal layer is preferably a precursor containing Ce, for example, (C; H small Ce or ((C5H5) C5H4) 3Ce. Forming the Nd layer as the sacrificial property of the initial sacrificial metal layer The metal source gas is preferably a precursor containing Nd, such as (GH + Nd or (C3H? C5H small Nd. Furthermore, it forms As the sacrificial metal source gas of the initial sacrificial metal layer, the Be layer is preferably a precursor containing Be, for example, 'Be (C2H5) 2. The precursor containing A1 is the preferred choice of the sacrificial metal source gas. As above As mentioned above, because the Gibbs free energy of A1 is higher than other transition metals and precursors combined with halogen atoms Cl, Br, I. If the A1 layer is used as the initial sacrificial metal layer, TMA (trimethyl bromide 14 ( Please read the precautions on the back before filling in this page) Order --------- Line — This paper size is applicable to the national standard (CNS) A4 specification (210 X 297 mm) Fine ^ '· &gt;; Α7 Β7 Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs V. Invention Description (P?); (CH + Al) is a typical precursor of a sacrificial metal source gas. At this time, H2 is used as a reducing gas, and The TMA gas reaction causes CH3 in TMA to become CH4. CH4 is removed from the reaction chamber 51, and A1 atoms are deposited on the surface of the semiconductor substrate to form the A1 layer. Then, the surrounding portion of the resulting structure where the sacrificial metal layer is formed is inert. The gas is eliminated and the sacrificial metal source gas remaining in the reaction chamber 51 is completely eliminated (Step Π), (first eradication process). The reducing gas can be supplied during the first erasure process. Similarly, the semiconductor substrate is maintained at 300 ~ 500 ° C. Here, the semiconductor substrate is in the initial sacrificial metal layer. The temperature during the formation process can be controlled to be the same as or different from the temperature during the first elimination process. After the first elimination process is completed, the sacrificial metal source gas, reducing gas, and inert gas are injected into the reaction chamber 51, The sacrificial metal source gas and the reducing gas are reacted, so that the sacrificial metal atom layer is formed on the initial sacrificial metal layer (step 15). For example, if TMA ((CH3) 3A1) gas and hydrogen gas are used as the sacrificial metal source gas and the reducing gas, respectively, the A1 layer will form a sacrificial metal atomic layer. Here, the sacrificial metal atom layer is formed of the same material as the original sacrificial metal layer. For example, if the initial sacrificial metal layer is M, the sacrificial metal atom layer is also formed of A1. Similarly, the sacrificial metal atomic layer is formed using the same sacrificial metal source gas as the initial sacrificial metal layer. In this case, the thickness of the sacrificial metal atomic layer should preferably be 4 to 5A. Here, when the entire surface of the exposed impurity layer is covered with a sacrificial metal atom layer, the formation process of the initial sacrificial metal layer can be omitted. In other words, the formation of the initial sacrificial metal layer is to prevent the metal source gas injected into the reaction chamber 51 from forming on the metal atomic layer in accordance with 15 paper standards + National Standard (CNS) A4 (210 X 297) Mm) IK-I n J1— —1 -1--ί J. ^ Λ -I----n --- ^-T ° J1 1—---nn I (Please read the note on the back first Please fill in this page again for details) Printed by the Consumers' Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs A7 B7 V. Description of the invention (α) The silicon atom in the impurity layer reacts. The surrounding portion of the structure obtained at the formation of the sacrificial metal layer is purged with an inert gas, and the sacrificial metal source gas remaining in the reaction chamber is completely excluded (step 17) (second purging process). The reducing gas may be supplied during the second scavenging process. After the second eradication process is completed, the inert gas and the reducing gas of the metal source gas are injected into the reaction chamber 51, thereby removing the sacrificial metal atomic layer and the initial sacrificial metal layer, and simultaneously forming a metal on the entire surface of the semiconductor substrate Atomic layer (step 19). At this time, 'a metal halide gas containing metal atoms forming a metal layer, such as TiCh', is preferably used as the metal source gas. An inert gas, such as N2 gas or Ar gas, is a carrier gas for a metal source gas, that is, a metal halide gas. When the sacrificial metal atomic layer and the initial sacrificial metal layer are both A1 layers, TiCU gas is used as the metal halide gas. 'AhCU gas will be generated by the combination of the A1 atom in the A1 layer and the TiCU (: 1 atom) to dissolve. Ti atoms in TiCL · gas will be deposited on the semiconductor substrate to form a Ti layer. AhCh gas will be eliminated in the reaction chamber 51. Because the Gibbs free energy of AhCU is higher than that of TiCU gas, as shown in Table 1A, A1 The layer reacts with TiCU gas to form a titanium layer. TaCls, HfCU, ZrCh, TiL ..., TaL ·, HfL ·, Zrh, TiBn, TaBn, HfBn, ZrBn, TiF *, TaF5, HfF, or ZrF * gas can be used instead TiCl · gas is used as metal halide gas. In order to form Hf or Zr layer using HfCl · or ZrCU gas as metal halide gas, A1 layer is the best sacrificial metal atomic layer or initial sacrificial metal layer. Because HfCL · And ZrCL · gas Gibbs free energy higher than LaCh, PrCh, ImCU, CeCh, NdCl; and BezCU gas, as shown in Table 1A. Similarly, in order to form the required metal atomic layer, [6 X \ JI --- ---------- -------- Order --------- line- (Please read the note on the back first Please fill in this page for the matters needing attention.) This paper size is in accordance with Chinese National Standard (CNS) A4 specification (2i0 X 297 mm) A7 ______B7 _____ 5. Description of the invention ((^) Most metal halide gases are used, as shown in Table 2 As shown in Fig. 4, the A1 layer is the optimal sacrificial metal atomic layer or the initial sacrificial metal layer. Steps 13, 15 '17 and 19 (first eradication to form a sacrificial metal atomic layer, second erasure, The formation of the metal atomic layer) is preferably performed at the same temperature. After the metal atomic layer is formed, η 値 is increased by 1 (step 21), and the increased η is compared with the initial predetermined cycle number k (step 23). If the increased η 値 ratio is The initial predetermined number of cycles k is small, steps 13, 15, Π, and 19 (the first eradication to form a sacrificial metal atomic layer, the second eradication to form a metal atomic layer) are repeated one by one until II 値 equals the cycle A number of k, thereby forming a metal layer of a desired thickness on the semiconductor substrate. When the resulting structure where the metal layer is formed is annealed at a predetermined temperature, a metal silicide layer is formed at the interface between the impurity layer and the metal layer. Metal silicide layer An ohmic layer connecting impedance with the impurity layer. As shown in FIG. 6, a titanium layer is formed according to an embodiment of the present invention. In the process of forming the initial sacrificial metal layer, the first sacrificial metal atom layer is formed, and the first The second elimination formed a metal atomic layer, and the temperature Ts of the semiconductor substrate was 450 ° C. The initial sacrificial metal layer was formed by reacting the TMA gas with the outgas for ten seconds. At this time, the inert% gas was also injected into the reaction chamber, and% and Η: were injected into the reaction chamber at a flow rate of 40 sccm and iOOOsccm, respectively, and the pressure in the reaction chamber was about 3 toa. Similarly, TMA gas is generated at room temperature using a diffuser. At this time, no carrier gas is used for the TMA gas, so the TMA gas is injected into the reaction chamber due to the difference between the vapor pressure of the TMA gas and the pressure of the reaction chamber. After the initial sacrificial metal layer (layer A1) is formed, the TMA gas is no longer supplied. In order to eliminate the TMA gas remaining in the reaction chamber, the first removal process is L7. This paper applies the Chinese National Standard (CNS) A4 specification ( 210 X 297 mm) '^ (Please read the precautions on the back before filling this page) k -------- tr-i -------- line' Consumption by the Intellectual Property Bureau of the Ministry of Economic Affairs Printed by the cooperative 4391 51 V. Description of the invention (^) A7 B7 Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs for 5 seconds. At this time, N2 gas and outlet gas were continuously injected to keep the pressure in the reaction chamber at about 8 torr. Then, after the first scavenging process is completed, the TMA gas is supplied for about 1 second, so that H2 reacts with the TMA gas to form a thin sacrificial metal atomic layer, that is, an aluminum atomic layer. Next, the supply of TMA gas is stopped, and the second erasing process is performed in the same manner as the first erasing process. After that, the T: 14 gas is injected into the reaction chamber for about 5 seconds. In this way, the aluminum layer and the TiCL * gas react with each other to form a titanium atom layer on the entire surface of the semiconductor substrate. Next, the first elimination is performed to form a sacrificial metal atomic layer, and the second elimination is performed to form a metal atomic layer, which is sequentially repeated 50 times. Referring to FIG. 6, according to an embodiment of the present invention, a titanium layer is formed in a connection hole having an aspect ratio of 5 or higher, and has a uniform thickness of about 600A in a portion around the connection hole. In Fig. 7, the horizontal axis represents the diffraction angle of X-rays, and the vertical axis represents the diffraction X-ray intensity in arbitrary units. Similarly, in the figure, the range of X-ray diffraction angle 20 between 140 ° and 170 ° is the result obtained by measuring the A1 component, and the angle between 84 ° and 89 ° is the result obtained by measuring the Ti component. The measurement of the C1 component is between 90 ° and 96 °. It can be seen from FIG. 7 that the Ti layer formed according to an embodiment of the present invention does not contain impurities, but only Ti atoms. 3 and 4, the parts marked with the same reference numerals represent the same steps mentioned in the first embodiment. Referring to FIGS. 3, 4 and 5, the formation of the initial sacrificial metal layer, the first erasure, and the formation of the sacrificial The metal atomic layer, the second elimination, the steps of forming the metal atomic layer 11, 13, 15, 17, and 19, the third 18 (please read the precautions on the back before filling this page) -Q- ----- Order-line · This paper size applies to China National Standard (CNS) A4 (2 〖0 X 297mm) Printed by the member of Intellectual Property Bureau of the Ministry of Economic Affairs and Consumer Cooperatives 43 91 δ 1 Α7 ______ Β7 ______ 5. Description of the invention (Q) Steps 25 and 27 of removing and forming a silicon atom layer thereby forming a metal silicide layer. Step 25 of the third eradication is the same as steps 13 and 17 of the first erasure. After the completion of step 25 of the third elimination, a silicon atomic layer formed on the metal atomic layer is reacted by injecting a silicon source gas into the reaction chamber 51. At this time, during the formation of the silicon layer, the temperature of the semiconductor substrate was maintained at the same temperature as that in the third erasing step 25, that is, 300 to 500 ° C. Like steps 11, 13, 15, Π, 19, 25, and 27 in the first embodiment of the present invention (the first erasure, the formation of a sacrificial metal atom layer, the second erasure 1, the formation of a metal atom layer, The third eradication and formation of a silicon metal atomic layer) Repeat as necessary in order, so that the metal atomic layer and the silicon atomic layer are alternately stacked. At this time, the metal atomic layer and the silicon atomic layer react with each other, so that a metal sand layer can be formed. The composition ratio of the metal silicide layer can be changed by controlling the thickness of the metal atomic layer and the silicon atomic layer. The metal source gas is preferably SiH-, S12H6, (CH〇3SiC ξ CSi (CH) 3, ((CH3) 3Si) 2CH2, (CH3) 3CSi (CH3) 2Cl '(C4H9) SiCh, (CH3) 3SiN (C2H5 ) 2, (CH3) 2SiCl2, ((CH〇2Si-) n, (C6H5) 2SiCl2, (C6H5) 2SiH2, C ^ HsSiCh, ChSiSiCh, (CH3) 3SiSi (CH3) 3, CHsSiChH, (CH3) (CsH5) SiCl2, C6H5SiCh, SiBn, SiCh, SiF4, SiL ·, (C32HieNs) SiCh, Si (Si (CH3) 3) 4, Si (CH3 &gt;, CH ^ SiCh, HSiCh, (GH5) 3SiQ, CF3Si (CH3) 3, (CHbhSiCl, (CH3) 3SiH, (CH3) 3SiC three CH, (C5H5) Si (CH3) 3, (C5 (CH3) 5) Si (CH3h, (C6H5) 3SiCl, (CsH small SiH, (CHANHCH, CH2 = CHSiCl3 gas. Fenggen According to another specific embodiment of the present invention, the required metal silicide layer, such as a 'TiSi layer, a TaSi layer, a ZrSi layer, or a HfSi layer, can be applied to the country according to the metal __19 This scale ^ ~ Quasi- (Certificate 4 regulations' T2iG χ 297-(Please read the precautions on the back before filling out this page) -rlk &lt; -------'-- tT .--------- Line ~ 3 '9 1 δ 1 Α7 _Β7_ V. Description of invention (ίβ) The type of the atomic layer is formed. Similarly, metal silicon with excellent step coverage The physical layer can be formed in the connection hole having a high aspect ratio. As described above, according to the present invention, the metal layer or the metal silicide layer having excellent step coverage can be formed in the connection hole having a high aspect ratio. Therefore, a metal connection suitable for a highly integrated semiconductor device can be formed. The present invention is not limited to the specific embodiments illustrated, and those skilled in the art can make many changes and modifications within the scope of the present invention. &Quot; TJ icon r | 丨 丨 丨 丨 4 β5- (Please read the precautions on the back before filling this page) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 2 This paper is applicable to the national standard (CNS) A4 specification (210 X 297 mm)

Claims (1)

  1. The Ministry of Economic Affairs, Intellectual Property, General Affairs / $. 局 员 消 ## 社 社 印 1. A method of forming a metal layer, which includes the following steps: (a) Carving a sacrificial metal atom layer on a single-conductor substrate; (b) On a semiconductor On the substrate, by reacting the sacrificial metal atomic layer with the metal halide gas, the sacrificial metal atomic layer is eliminated and a metal atomic layer is formed at the same time; and (c) the sacrificial metal atomic layer and the gold eyebrow atom-layer are alternately formed at least once Metal atom layers are alternately stacked on a semiconductor substrate, wherein the metal atom layer is formed by reducing a metal in a metal halide, and the metal constituting the metal atom layer is different from the metal constituting the sacrificial metal atom layer-a metal element. 2. The method according to item 1 of the patent application scope, further comprising, before the step (i) of forming a sacrificial metal atomic layer ', forming an initial sacrificial metal layer on the semiconductor substrate. 3. The method according to item 2 of the patent application range, wherein the semiconductor substrate is heated to 300 to 500 ° C when the initial sacrificial metal layer is formed. 4. The method according to item 2 of the application, wherein the initial sacrificial metal layer and the sacrificial metal atomic layer are carved from the same material. 5. The method of claim 2 in which the initial sacrificial metal layer and the sacrificial metal atom layer are formed of the same reactive gas. 6. The method according to item 1 of the patent application, wherein when the sacrificial metal atomic layer or metal atom layer is formed, the semiconductor substrate is heated to 300 ~ 500 ° C ° 7. The method according to item 1 of the patent application, wherein Djiboumu paper composed of metal atoms of sacrificial metal atomic layer and halogen atoms of metal halide gas is applicable to Chinese national standards (CNS &gt; A4 now (2t0X2W mm)), ----------- T ------ 1TI .------ ^ =-(Please read the notes on the back before filling this page)
    The profit scope of ABCD is the wisdom of the Ministry of Economic Affairs; the 4th bureau of 财 cai; the free energy of industrial consumer t cooperatives, which is higher than the Gibbs free energy of metal halides. 8 * The method according to item 7 of the scope of patent application, wherein a sacrificial metal atomic layer is formed by reacting a sacrificial metal source gas with a reducing gas. 9. The method of claim 8 in which the reducing gas is selected from the group consisting of H2 and silane gas. 10. The method according to item 7 in the scope of patent application, wherein the metal halide gas is selected from the group consisting of the following gases: TiCh, TaCh, HfCL, ZrCh 'TiL, TaL, HfL, ZrL, TiBr4 , TaBr5, HfBn, ZrBn, TiF4, TaF5, TiF *, HfF4 and ZrF4. 11 'The method according to item 10 of the scope of patent application, wherein when the metal halide gas is TiCU, the sacrificial metal layer is selected from the group consisting of the following metal layers: A1 layer, La layer, Pr layer, In layer, Ce layer, Nd layer and Be layer. 12. The method according to item 丨 丨 in the scope of patent application, wherein the sacrificial metal source gases used to form the A1 layer, the La layer, the pr layer, the in layer, the Ce layer, the Nd layer, or the Be layer respectively include Al, La, Precursor of Pr, In, Ce, Nd or Be. 13 'The method according to item 12 of the scope of patent application, wherein the precursor containing Al is selected from the group consisting of: (C4H9) 2A1H, (GH + AIH, (C2H5: hAl, (CH + Al, A1H3N (CIL ) 3, (CH3) 2A1H, and (CH〇2C2H5N: A1H3) Η · As in the method of claim 12 of the patent application, the precursor containing La is selected from the group consisting of: (C5H5) 3La and (C2H7C4H4 ) 3La 0 2 The size of the paper is applicable to the Chinese national standard (CNS> A4 size (210X297)) — —.-------- Ύ ------, 玎 ------ line U (Please read the notes on the back before filling this page)
    • Benefit range 8 8 8 8 ABCD 15 · As in the method of claim 12 of the patent scope, the precursors containing Pr are selected from the following groups: (C5H〇3Pr and (〇Η7〇Η 小 Pr (Please read first Note on the back page, please fill out this page again) 16. If the method of the scope of patent application No. 12, the precursor containing In is selected from the following groups: CMWn, (CH3) 5C5In, (GH5) 3In, and (CH + In. 17. The method according to item 12 of the scope of patent application, in which the precursor containing Ce is selected from the group consisting of: (C5H5: hCe and ((CsH5) C5H03Ce ° 18. The method of 12 items, in which the precursor containing Nd is selected from the group consisting of: (C5H03Nd and (C3H7C5H4) 3Nd.) 19. The method of item 12 in the scope of patent application, wherein the precursor containing Be is Be (CiH5) 2. 20 * The method according to item 2 of the patent application scope, further comprising, before step (a) of forming a sacrificial metal atomic layer, purging the obtained structure at the formation site of the initial sacrificial metal layer with an inert gas. The steps of the surrounding part. ^ Review of the cooperative cooperative disaster 21. The method according to item 丨 of the patent application, further comprising, before step (b) of forming a metal atomic layer, purging the surrounding portion of the resulting structure where the initial sacrificial metal layer is formed with an inert gas. 22. The method according to item 20 of the patent application, wherein the inert gas system is selected from the group consisting of N: gas and Ar gas. 23. The method according to item 21 of the patent application, wherein the inert gas It is selected from the group consisting of N2 gas and Ar gas. This paper size is applicable to China National Standard (CNS) A4 (210X 297 mm)
    The scope of claim 24. The method according to item 1 of the patent application scope, further comprising a step of laminating a metal atomic layer (after the annealing treatment on the interface between the semiconductor substrate and a plurality of metal atomic layers), so that the semiconductor substrate and Steps in which the metal atomic layers react with each other to form an ohmic layer. 25. The method according to item 24 of the patent application, wherein during the annealing process, the ambient gas can be selected from the group consisting of Ar, Qin and NH3 gas. 26 The method of claim 24, wherein the ohmic layer is a metal silicide layer. J: 27. A method for forming a metal silicide layer, which includes the following steps of forming a sacrificial metal atom layer on a semiconductor substrate; On the semiconductor substrate, by reacting the sacrificial metal atom layer with the _Jinlixide gas, the sacrificial metal atom layer is eliminated and a metal atom layer is formed at the same time; a silicon atom layer is formed on the metal atom layer;财 工 消 # Cooperation 钍 India disaster (please read the precautions on the back before filling this page) Line I through the formation of sacrificial metal atoms , Metal atomic layer and silicon atomic layer at least one time, alternately stacked on a semiconductor substrate will be an atomic layer and a silicon atomic layer, wherein the metal atomic layer is formed by reduction of a metal in a metal halide 'and the constituent metal atomic layer And the metal constituting the sacrificial metal atomic layer is a different metal element. 28. The method of claim 27, further comprising forming an initial sacrificial property on the semiconductor substrate before the step of forming the sacrificial metal atomic layer. Steps of the metal layer. This paper size applies the Chinese National Standard (CNS) A4 specification (210X297 mm> A8 BS C8 D8 Wu, applied for the scope of patent 29. If the method of the scope of the patent application No. 28 method, where the initial sacrificial metal layer During the formation, the semiconductor substrate is heated to 300 ~ 5 (χΓ (:. (Please read the precautions on the back before filling out this page) 30. If the method of the scope of patent application No. 28, the initial sacrificial metal atomic layer and The sacrificial metal layer is formed of the same material. 31. The method of claim 28, wherein the initial sacrificial metal source The layer and the sacrificial metal layer are formed of the same reaction gas. 32. The method according to item 27 of the patent application, wherein when the initial sacrificial metal atom layer, metal atom layer and silicon atom layer are formed, the semiconductor substrate is heated to 300 to 500 ° C. 33. The method according to item 27 of the patent application, wherein the Gibbs free energy of the component containing the metal atom of the sacrificial metal atom layer and the halogen atom of the metal halide gas is higher than that of the metal halide Gibbs 34. The method according to item 33 of the patent application, wherein the sacrificial metal source gas is reacted with the reducing gas to form a sacrificial metal atomic layer. 35 * The method according to item 34 of the patent application, wherein The reducing gas system is selected from the group consisting of H2 and silane gas. Ministry of Economic Affairs, Treasury, 4th Bureau; '/] # Cooperative Du printed 36. If the method of applying for the scope of the patent No. 35, wherein the metal halide gas is selected from the group consisting of: TiCU, TaCh, HfCh , ZrCU, T1I4, TaL ·, Hfh, ZrL ·, TiBn, TaBn, HfBr4, ZrBn, TiF4, TaF5, Hfh, and ZrF4 gases. 37. The method of claim 36, wherein when the metal halide gas is TKh, the sacrificial metal layer is selected from the group consisting of the following metal layers: A1. Layer, La layer, Pr layer, In layer, Ce layer, Nd layer and Be 5 The meaning of this paper is applicable to China's national standard (CNS &gt; 8 4 specifications (210 × 297 mm) 1391 5 1
    Boli range
    A8 B8 C8 D8 layer. (Please read the precautions on the back before filling this page) 38. If the method of the scope of patent application No. 37, which is used to form the A1 layer, La layer, Pr layer, In layer, Ce layer, Nci layer or Be layer The sacrificial metal source gas is a precursor containing Al, La, Pr, In, Ce, Nd or Be, respectively. 39. The method of claim 38, wherein the precursor containing A1 is selected from the group consisting of: (GH small A1H, (C% H 屮 A1H, (C2H5) 3A1, (CHb) 3Al, A1H3N (CH3) 3, (CH3) 2A1H, and (CH ^ GfLN: Aim. 40. As in the method of claim 38, the precursor containing La is selected from the group consisting of: (C5H5) 3La and (C2H7C4H Small La Q 41 · As in the method of applying for the scope of patent No. 38, the precursor containing Pr is selected from the group consisting of: (C5H5) 3Pr and (GHvGH + Pr Ministry of Economy and Intellectual Property &quot; As ( Industrial consumption cooperatives seal% 42. As in the method of the 38th patent application, the precursor containing In is selected from the group consisting of: C2H5In, (CH3) 5C5In, (C2H5) 3In, and (CH3) 3ln. 43. The method according to item 38 of the patent application, wherein the precursor containing Ce is selected from the group consisting of (C5H5) 3Ce and ((C5H5) C5H4) 3Ce. 44. Method, in which precursors containing Nd are selected from the group consisting of: (C5H5) 3Nd and (C3H7C5H4) 3Nd. Applicable to China National Standard (CNS) A4 specification (210X297 mm) A8 B8 C8 D8 439151 6. Application for patent scope 45. For the method of applying for patent scope item 38, the precursor containing Be is Be (GH5) 2. 46 The method according to item 28 of the patent application scope, further comprising the step of purging the surrounding portion of the resulting structure where the initial sacrificial metal layer is formed with an inert gas before forming the sacrificial metal atomic layer. The method according to item 27, further comprising the step of removing the surrounding portion of the structure obtained at the formation site of the sacrificial metal atom layer with an inert gas before forming the metal atom layer. 48. The method according to item 27 in the scope of patent application, which The method further includes a step of purging the surrounding portion of the resulting structure at the place where the metal atomic layer is formed with an inert gas before forming the silicon atomic layer. 49. The method according to item 46 of the patent application range, wherein the inert gas system is from% gas and Ar Choose one of the groups consisting of gas. 50. The method according to item 47 of the scope of patent application, wherein the inert gas system is composed of N2 gas and Ar gas. 51. The method according to item 48 of the patent application, wherein the inert gas system selects one from the group consisting of N2 gas and Ar gas. 52. The method according to item 27 of the patent application The silicon atomic layer is formed by the reaction of a silicon source gas. 53. The method according to item 52 of the patent application range, wherein the silicon source gas system is selected from the group consisting of the following gases: S: iH4, S12H6, ( CH3) 3SiC Three CSi (CH) 3, ((CH3) 3Si) 2CH2, (CH3) 3CSi (CH3) 2C1, (C% H0SiC13, (CH3) 3SiN (C2H5) 2, (CH + SiCh, (( CH3) 2Si-) n, (C6H5) 2SiCl2, (C6H5) 2SiH2, C2H5S1CI3, CbSiSiCb '7 (Please read the precautions on the back before filling this page) Order! The paper scale is applicable to China National Standard (CNS) A4 (210X297 mm)
    Α8 Β8 C8 D8 VI. Patent application scope (CH3) 3SiSi (CH3) 3, OLSiCKH, (CH3) (C6H5) SiCh, OBLSiCh, SiBn, Sicl &lt; t, SiF · *, Sih, (CizHieNOSiClz, Si (Si (CH (3 ) 3) 4, Si (CHb>, CH3SiCl3, HSiCh, (C2H5) 3SiCl, CF3Si (CH3) 3 '(CHahSiCl, (CH3) 3SiH, (CH3) 3SiC three CH, (C5H5) Si (CH3) 3' C5 (CH3) 5) Si (CH3) 3, (GH5) 3SiCl, (C6H5) 3SiH, ((CH3) decorated with CH and CH2 = CHSiCl3 gas. 54. If the method of the 27th scope of the patent application, it is further included in The step of annealing at a predetermined temperature after alternately stacking a metal atomic layer and a silicon atomic layer on a semiconductor substrate. 55 * As the method of the scope of patent application No. 54, which includes rapid thermal processing (RTP) annealing, furnace annealing processing, and vacuum thermal processing. One of them is to perform annealing. 56. A method for forming a metal silicide layer, which includes the following steps of forming a silicon atom layer on a semiconductor substrate; forming a sacrificial metal atom layer on the silicon atom layer; On the substrate, the sacrificial metal atomic layer reacts with the metal dentate gas. Eliminate the sacrificial metal atomic layer and simultaneously form the metal atomic layer; and by sequentially forming the sand atomic layer, the sacrificial metal atomic layer, and the metal atomic layer at least once, 'the metal atomic layer and the political atomic layer are alternately stacked on the semiconductor substrate, The metal atomic layer is formed from the metal of the metal halide, and the metal constituting the metal atomic layer is different from the metal element constituting the sacrificial metal atomic layer. ^ _ 8 ^ The scale applies to Chinese national standards (CNS) Μ is now (210X297 mm) ----- (Please read the precautions on the back before filling in this page), τ. Line——
TW87106228A 1997-12-31 1998-04-23 Method for forming conductive layer using atomic layer deposition process TW439151B (en)

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