TWI446453B - 受應力之場效電晶體以及其製造方法 - Google Patents

受應力之場效電晶體以及其製造方法 Download PDF

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TWI446453B
TWI446453B TW096135865A TW96135865A TWI446453B TW I446453 B TWI446453 B TW I446453B TW 096135865 A TW096135865 A TW 096135865A TW 96135865 A TW96135865 A TW 96135865A TW I446453 B TWI446453 B TW I446453B
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germanium
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Andrew M Waite
Scott Luning
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Description

受應力之場效電晶體以及其製造方法
本發明大體上係關於受應力之場效電晶體以及其製造方法,且更詳言之,係關於嵌入之矽鍺受應力之場效電晶體以及其製造方法。
大多數現今積體電路(integrated circuit,IC)係藉由使用多個相互連接的場效電晶體(field effect transistor,FET)而實施,該場效電晶體也稱為金屬氧化物半導體場效電晶體(metal oxide semiconductor field effect transistor,MOSFET),或者簡稱為MOS電晶體。FET包含閘電極作為控制電極、及分隔開之源極和汲極電極,該源極和汲極電極之間能流過電流。施加至該閘電極之控制電壓控制電流流過該源極和汲極電極之間之通道。
FET之增益,通常由互導(transconductance)(gm )所定義,係與電晶體通道中之主要載子之移動率(mobility)成比例。MOS電晶體之電流載送能力係與互導乘以該通道之寬度除以該通道之長度(gm W/I)成比例。FET通常製造於具有(100)晶面方向(crystallographic surface orientation)之矽基板上,其為矽技術上所習知。對於此方向與許多其它的方向,電洞(於P通道FET(PFET)中之主要載子)之移動率,能藉由對該通道施加壓縮縱向應力而增加。壓縮縱向應力能施加於該FET之通道,其係藉由嵌入擴張材料(如假晶(pseudomorphic)SiGe)於該矽基板中在該電晶體通道之端部而達成(例如,見IEEE電子裝置文獻(IEEE Electron Device Letters)第25卷,第4冊,第191頁,2004年)。矽鍺(SiGe)晶體的晶格常數大於矽晶體的晶格常數,所以嵌入之SiGe之存在導致矽基體(matrix)之變形,因而壓縮(compress)該通道區域中之矽。雖然若干技術對嵌入SiGe為已知以提高於PFET中的主要載子電洞之移動率,但是尚沒有任何技術用嵌入的矽鍺達到可能得到的增加移動率。
因此,希望提供一種場效電晶體具有提升的主要載子通道移動率。另外,希望提供一種製造具有提升的電洞移動率之P通道場效電晶體的方法。此外,由接下來的詳細說明與附加的申請專利範圍,並結合所附的圖式與前述技術領域及先前技術,本發明之其它所希望的特性與特徵將變得清楚。
本發明提供一種具有提升主要載子移動率之受應力之場效電晶體。該受應力之場效電晶體包括矽基板,在該矽基板上覆有閘極絕緣體。閘電極覆於該閘極絕緣體上,並且於該閘電極下方之矽基板中定義通道區域。具有第一厚度之第一矽鍺區域嵌入於該矽基板中,並接觸該通道區域。具有大於該第一厚度之第二厚度的第二矽鍺區域也嵌入該矽基板中,並且與該通道區域分隔開。
本發明提供具有提升主要載子移動率之受應力之場效電晶體的製造方法。該方法包括形成絕緣體上覆矽基板(silicon on insulator substrate),該基板包括位在矽基板上之絕緣體層上之矽層。形成閘電極覆於該矽層上。第一未摻雜矽鍺層以磊晶方式嵌入該矽層中,並且對齊該閘電極。第二雜質摻雜矽鍺層以磊晶方式嵌入該矽層中,並與該閘電極分隔開。
以下詳細說明僅為例示性質,並不欲限制本發明或本發明之應用和使用。另外,無意由任何在前面的技術領域、先前技術、發明內容或以下的實施方式中所提出之明示或暗示的理論來束縛本發明。
第1圖示意地顯示根據本發明之一個實施例之場效電晶體(FET)20(特別是P通道FET(PFET))之剖面圖。FET20包含矽基板22,該矽基板22具有閘極絕緣體23形成於該基板表面。閘電極24覆於該閘極絕緣體23上。該閘電極定義在該基板表面並位於該閘電極下方之電晶體通道26之位置。較佳未摻雜矽鍺(SiGe)之淺區域28被嵌入該矽基板中且相當接近該電晶體通道之邊緣。較佳原位(in situ)雜質摻雜SiGe之較深區域30被嵌入該矽基板中於與該通道區域更分隔開的位置。該二個嵌入之SiGe區域共同給予單軸(uniaxial)壓縮應力於該通道區域26,如箭頭32所表示,該壓縮應力提升於該通道中之主要載子電洞之移動率。該淺的嵌入矽鍺區域將之該應力引發材料(stress inducing material)定位於相當接近該通道區域,但因為此矽鍺區域係未被摻雜,因此沒有硼摻雜物侵入延伸區之不利的影響,並因此降低裝置短通道效能。該較深的嵌入矽鍺區域有效地對通道區域施加應力;該雜質摻雜係與該通道分隔開,並因此避免通道侵入(channel encroachment),以及該雜質摻雜用來形成該電晶體之源極34與汲極36。使用選擇性生長磊晶SiGe(其於原位摻雜有硼,舉例而言,藉由添加如二硼烷(diborane)之雜質摻雜氣體至磊晶生長反應物中)省去離子植入步驟。該於原位雜質摻雜省去製程步驟,但是應變保留係於原位摻雜之更重要的優點。應變SiGe區域之離子植入具有導致於SiGe區域中應變之鬆弛之不利的影響。於該嵌入區域中應變之鬆弛劣化由該嵌入之應變引發區域所達成之移動率提升。由於該源極與汲極區域之於原位摻雜,因此免除了對這些區域進行離子植入之需要,並且保留了與該些嵌入區域相關之應變。按照本發明之實施例,於PFET的通道中之載子之移動率係由淺的緊鄰未摻雜SiGe區域與由較深的原位摻雜SiGe區域之結合效果而提升,該淺的緊鄰未摻雜SiGe區域定位成相當對齊該閘電極,而該較深的原位摻雜SiGe區域係由源極/汲極離子植入而鬆弛。如下更完全說明,PFET 20能形成於塊體(bulk)矽區域中、在絕緣體上覆薄矽層(thin siliconlayer on insulator,SOI)中、或者於支撐該SOI之該基板中。
第2至13圖示意地顯示根據本發明之實施例之受應力之P通道場效電晶體40之製造方法步驟之剖面圖。製造場效電晶體之各種步驟係眾所週知,因此為了簡潔之目的,許多習知步驟於此僅會簡單論述或將其全部省略而不提供眾所週知的製程細節。PFET 40能為積體電路的一部分,該積體電路包括大量的PFET以及N通道FET(NFET),雖然於此例示的實施例中僅顯示了單一場效電晶體。其它用於該積體電路中之電晶體能包含受應力以及未受應力之電晶體。
如第2圖中所示,根據本發明之實施例之受應力之FET 40之製造從提供半導體基板42開始。該半導體基板較佳為單晶矽基板,其中此處所使用之用語“矽基板”包含典型使用於半導體工業之相當純的矽材料。矽基板42可能為塊體矽晶圓、或者如此所顯示的(但不限於此)為SOI晶圓,該SOI晶圓包含於絕緣層46上之薄矽層44,該絕緣層46依序由矽載體晶圓48所支撐。較佳該矽晶圓具有(100)或(110)方向。該薄層44之厚度視被實施之積體電路之類型而定,舉例而言,該厚度可為大約50至120奈米(nm)。該薄矽層44之顯示部分50係摻雜有N型雜質摻雜物。該部分50能被摻雜至適當的導電率(conductivity),例如,藉由離子植入。形成淺溝槽隔離(Shallow Trench Isolation,STI)52以使個別裝置彼此電性隔離。如眾所週知,能使用許多製程以形成STI 52,所以該些製程於此不須詳加論述。一般而言,STI包含淺溝槽,該淺溝槽被蝕刻至該半導體基板之表面中,並且該淺溝槽隨後被填入有絕緣材料。該STI 52較佳延伸穿過該薄矽層之厚度至下方之絕緣體46。在該溝槽被填入有絕緣材料後,該表面通常用例如化學機械平坦化(Chemical Mechanical Planarization,CMP)製程而平坦化。
該方法繼續如第3圖中所顯示,根據本發明之一實施例,形成閘極絕緣體54在矽層44之表面56。閘極絕緣體54可能為氧化矽、高介電常數絕緣材料、或類似物,並且能具有例如大約1至5nm之厚度,雖然某些裝置將需要較薄或較厚的閘極絕緣體與/或由相同或不同的材料之多層形成之閘極絕緣體。較佳閘極絕緣體54是由矽層44之熱氧化作用而形成之二氧化矽。或者,閘極絕緣體54可能由化學氣相沉積(Chemical Vapor Deposition,CVD)或化學氣相沉積之變化之其中一者例如低壓化學氣相沉積(Low Pressure Chemical Vapor Deposition,LPCVD)、電漿增強化學氣相沉積(Plasma Enhanced Chemical Vapor Deposition,PECVD)、或類似者所形成。該閘極絕緣體層形成後,接著沉積閘電極形成材料層58與蓋層(capping layer)60。較佳該閘電極形成材料是未摻雜之多晶矽,其係由CVD沉積至大約100奈米的厚度,而該蓋層是由LPCVD沉積之氮化矽至大約30奈米的厚度。能例如藉由矽烷(SiH4 )之還原而沉積該多晶矽,以及能例如藉由二氯矽烷(SiH2 Cl2 )與氨之反應而沉積該氮化矽。
該方法繼續由圖案化閘電極形成材料層58與蓋層60而形成閘電極62,如第4圖中所顯示。此二層能使用習知的光學微影與蝕刻技術而圖案化和蝕刻。例如,能藉由使用Cl或HBr/O2 化學作用之電漿蝕刻而蝕刻該多晶矽層,以及能使用CHF3 、CF4 或SF6 化學作用而電漿蝕刻該氮化矽。該閘電極62之側壁64與該薄矽層44之暴露表面被熱氧化以生長薄二氧化矽層66。該薄二氧化矽層能為3至4奈米厚,並用以保護在該閘電極62之基底之薄閘極氧化物之邊緣並分隔該多晶矽與隨後步驟中待沉積之各層。閘電極62定義該FET之通道區域68為在該閘電極下方之該薄矽層44之一部分。
依據本發明之一個實施例之方法繼續如第5圖所示,在該閘電極62之側壁64上形成可棄式(disposable)側壁間隔件。藉由沉積譬如氮化矽層之側壁形成材料層70而在閘電極62上形成側壁間隔件。能藉由LPCVD沉積例如大約8至18奈米厚度之氮化矽,係沉積在剩餘部分之蓋層60與薄二氧化矽層66上。
可棄式側壁間隔件72之形成係如第6圖所顯示,其藉由反應性離子蝕刻(RIE)之非等向性蝕刻層70而形成。該RIE留下具有大約7至15奈米厚度之側壁間隔件72於該閘電極62之側上。該側壁間隔件、蓋層60與STI 52用作為蝕刻遮罩,以及凹槽74被蝕刻入該薄矽層44之表面中。該些凹槽係藉由使用HBr/O2 與Cl化學作用之電漿蝕刻而蝕刻至大約40奈米之深度。該些凹槽係被蝕刻於將要成為該場效電晶體之源極與汲極區域中。該些凹槽係自行對齊該閘電極,並相當接近該通道區域68之端部。該積體電路之其它未打算形成凹槽之部分能藉由圖案化之光阻層(未圖示)而在該電漿蝕刻期間被遮罩。
該些凹槽74被填入有未摻雜之應力引發材料層76,如第7圖中所示。該應力引發材料能為任何假晶(pseudomorphic)材料,其具有與矽之晶格常數不同之晶格常數,並能夠生長於該矽層上。該二種並置(juxtaposed)材料於晶格常數之差異於主體(host)材料中產生應力。舉例而言,該應力引發材料可能為單晶矽鍺(SiGe),其具有大約10至35原子百分比的鍺,且較佳為大約20至35原子百分比的鍺。較佳該應力引發材料係藉由選擇性生長製程而磊晶生長至足夠填滿該些凹槽之厚度。以選擇性方式磊晶成長這些材料在矽主體上之方法為眾所週知,並不需要於此論述。SiGe較矽具有較大的晶格常數,並且壓縮縱向應力(compressive longitudinal stress)施加到電晶體通道。該壓縮縱向應力增加於通道中之電洞的移動率,並因此改進P通道場效電晶體之效能。
第二層可棄式側壁間隔件材料(未顯示),譬如氮化矽層,係全面性沉積(blanket deposited)覆於該閘電極結構和先前生長的矽鍺區域76上。該第二層被非等向性蝕刻以形成第二可棄式側壁間隔件78覆於側壁間隔件72上,如第8圖所示。側壁間隔件72加上側壁間隔件78之結合厚度較佳是大約23至30奈米。第二凹槽80被電漿蝕刻入該薄矽層44與SiGe區域76中,使用該蓋層60、側壁間隔件78與STI 52作為蝕刻遮罩。如前面所述,該積體電路之其它未打算形成凹槽之部分於電漿蝕刻期間能藉由圖案化之光阻層(未顯示)而被遮罩。該電漿蝕刻持續進行直到該凹槽具有至少大約80至100奈米的深度為止,但是在該凹槽延伸完全穿透該薄矽層44之厚度到達下方之絕緣體層46之前即終止。矽層44之至少一薄部分保持於該凹槽80之底部。該薄剩餘部份將作為核心層(nucleating layer),用於後續之應力引發材料之生長,如下文說明。凹槽80係因此自行對齊閘電極60和通道區域68,但與該閘電極60和通道區域68分隔開。
如第9圖所顯示,依據本發明之實施例,凹槽80被填滿有應力引發材料82。如同應力引發材料76,應力引發材料82能為任何假晶材料,其具有不同於矽之晶格常數之晶格常數,並能生長於該矽層上。較佳該應力引發材料相同於應力引發材料76,並且以與應力引發材料76相同的生長方式生長。舉例而言,應力引發材料82可為單晶矽鍺(SiGe),其具有大約10至35原子百分比的鍺,且較佳為大約20至35原子百分比的鍺。該SiGe能生長成至少填滿凹槽80之足夠厚度,並且較佳地用硼進行雜質摻雜至大約1×1020 至3×1020 cm-3 的摻雜濃度範圍。
在SiGe材料82選擇性生長後,側壁間隔件72、78與蓋層60脫離該裝置,如第10圖中所顯示。使用閘電極62與STI 52作為離子植入遮罩,硼離子被植入於薄矽層44、SiGe區域76與SiGe區域82之暴露部分中以形成源極與汲極延伸區與環狀植入物(HALO implant)84。該植入物形成淺的雜質摻雜區域接近該矽與矽鍺區域之表面。該積體電路之未被植入有硼離子之部分(譬如IC之NFET部分)能用圖案化之光阻層(未顯示)遮罩。
如第11圖所示,另外的氮化矽層或其它側壁間隔件形成介電材料(未顯示)係全面性沉積於閘電極62及STI 52、薄矽層與SiGe磊晶區域之表面之上。該另外的側壁間隔件形成材料層被非等向性蝕刻,舉例而言,藉由反應性離子蝕刻,以在閘電極62之側壁66上形成持久性(permanent)側壁間隔件86。該持久性側壁間隔件和STI 52能用作為離子植入遮罩以植入額外的P型雜質摻雜物離子於SiGe區域82中。再次地,該IC之該等未接收任何額外的P型雜質離子之部分能由圖案化之光阻層所遮罩。接著該額外的離子植入,若使用此種植入物,則該裝置受到熱退火,較佳為快速熱退火(Rapid Thermal Anneal,RTA)。該RTA活化任何已進行之離子植入,並且導致摻雜物雜質從原位摻雜SiGe區域82擴散出以形成源極區域90和汲極區域92。
也能使用側壁間隔件86以形成自行對齊之矽化物區域,該矽化物區域接觸該源極區域、汲極區域、與閘電極,作為第一步驟提供電性接觸至各種裝置區域。如第12圖所顯示,矽化物形成金屬層94,如鈷、鎳、鈦或類似者之層,被沉積於第11圖之裝置結構之表面之上。加熱該矽化物形成金屬層以使該金屬與下方之矽或矽鍺反應,以分別形成金屬矽化物電性接觸件96、97、98至該源極區域、汲極區域與閘電極,如第13圖所顯示。未與矽或矽鍺接觸之金屬,譬如位於STI 52上或側壁間隔件86上之金屬,不起反應,並且隨後能藉由在H2 O2 /H2 SO4 或HNO3 /HCl溶液中清洗而予以去除。
於前面說明中在蝕刻凹槽80與生長深的雜質摻雜SiGe區域之前,先蝕刻凹槽74以及生長淺的嵌入SiGe區域76。如於第14至18圖中剖面圖所顯示,依據本發明之另一實施例,這些方法步驟之順序能夠顛倒。依照本發明之此實施例,製造PFET 140之方法開始於如第2至4圖所顯示之相同方式。如第14圖所示,譬如氮化矽層之側壁間隔件形成材料層170沉積於第4圖之結構上。該氮化矽層應具有大約20至30奈米之厚度。
如第15圖所顯示,層170被非等向性蝕刻以於該閘電極62之邊緣上形成側壁間隔件172。該側壁間隔件172與STI 52與蓋層60一起用來形成蝕刻遮罩,並且凹槽174被電漿蝕刻入薄矽層44之表面中。凹槽174能具有至少80至100奈米之深度,但是在該凹槽延伸整個穿過該薄矽層44之厚度到達下方之絕緣體層46之前被終止。矽層44之至少一薄部分保持於該凹槽之底部。凹槽174因此自行對齊閘電極62與通道區域68,但該閘電極62與通道區域68由一厚度分隔開,該厚度係取決於側壁間隔件172之寬度。
藉由選擇性生長譬如SiGe層176之嵌入之應力引發材料磊晶層而填滿凹槽174,如第16圖所顯示。較佳該SiGe包括大約10至35原子百分比的鍺,且更佳包括大約20至35原子百分比的鍺。同樣情況,該SiGe較佳用硼進行原位雜質摻雜至大約1×1020 至3×1020 cm-3 的濃度。層176可於磊晶生長該SiGe期間藉由加入例如二硼烷於反應物流(reactant flow)而於原位被摻雜。
接著SiGe層176之選擇性磊晶生長,側壁間隔件172被移除,而具有厚度少於該側壁間隔件172之厚度的新側壁間隔件178形成於閘電極62之側壁上。側壁間隔件178係以與前面所述之側壁間隔件72相同的方式形成。側壁間隔件178能以氮化矽或其他介電材料形成,並且較佳具有大約7至15nm之厚度。側壁間隔件178、蓋層60與STI 52被用來作為蝕刻遮罩,並且淺凹槽180被電漿蝕刻入SiGe層176之表面中,如第17圖所示。凹槽180較佳具有大約40nm之深度。
藉由選擇性生長譬如SiGe層182之嵌入之未摻雜應力引發材料磊晶層而填滿凹槽180,如第18圖所顯示。較佳該SiGe包括大約10至35原子百分比的鍺,且更佳包括大約20至35原子百分比的鍺。該未摻雜之SiGe自行對齊該閘電極,以及相當接近該通道68之端部。PFET 140之進一步製程以如第10至13圖所示相同方式進行。
第19至22圖顯示根據本發明之另一實施例之受應力之PFET 240之製造方法步驟之剖面圖。根據本發明之此實施例,受應力之PFET 240製造於絕緣體上覆矽(Silicon on Insulator,SOI)半導體基板的支撐基板中。PFET 240之製造方法開始於提供半導體基板242。如第19圖所顯示,半導體基板242包括覆於絕緣體層246上之薄矽層244,該絕緣體層246依序覆於單晶矽基板248上。矽層244與矽基板248能為(100)或(110)結晶方向之其中一者,但較佳該矽層244為(100)結晶方向而該矽基板248為(110)結晶方向。電洞移動率於矽的(110)方向中較於矽的(100)方向中為大,而電子移動率相反,其在矽的(100)方向要大於矽的(110)方向。淺溝槽隔離區域252是形成於該薄矽層中,並且較佳延伸穿過該層244之厚度至該絕緣體246。該STI能以如上述第2圖中所述之相同方式形成。
如第20圖所顯示,凹槽254被蝕刻穿過該STI區域之其中一者並穿過絕緣體層246,以暴露矽基板248之一部分256。圖案化之光阻層(未顯示)能用作為蝕刻遮罩以定義該蝕刻區域。雖然受應力之PEFT能依據顯示於上述第2至13圖或第14至18圖中類似方法製造於暴露部分256中,但是較佳為選擇地生成長磊晶矽層258填滿凹槽254,如第21圖中所顯示。可藉由熟悉此項技藝者所熟知之技術,使用暴露部分256以令具有與矽基板248相同之結晶方向之單晶生長作為核心而選擇性地生長矽層258。用磊晶矽填滿該凹槽254提供大體上平坦表面260,用於隨後在磊晶矽與於剩餘的矽層244二者中製造電晶體。矽層258有效地變成該矽基板248之延伸區,具有相同的結晶方向,並且較佳是(110)結晶矽方向。具有(110)基板或基板延伸區允許製造其為混合定向電晶體(Hybrid Orientation Transistor,HOT)之PFET。HOT裝置具有對於(110)基板上可用之PFET提升電洞移動率的優點,而NFET被製造於具有(100)結晶方向之薄矽層中,其中電子具有相當高移動率。
如第22圖所顯示,依據本發明之實施例,P通道HOT 290製造於矽層258中。HOT 290能依據顯示於第2至13圖中的方法或依據顯示於第14至18圖中的方法製造。HOT 290包括有閘極絕緣體層294、形成於該閘極絕緣體上之閘電極296、在閘電極296下方之通道區域297、生長於凹槽300中之第一嵌入之未摻雜磊晶矽鍺層298、及形成在第二凹槽304中之第二雜質摻雜之嵌入磊晶矽鍺層302。此外,依據本發明之另一實施例,受應力之PFET 292能依據第2至13圖所顯示之方法或者依據第14至18圖所顯示之方法製造於薄矽層244中。此外,雖然未予顯示,其它的PFET與NFET(其係受應力或非受應力之其中任一情況),如必要時能製造於薄矽層244中以實施所希望的積體電路功能。
雖然於上述詳細說明中已提出了至少一個例示實施例,但是應了解到存在著大量的變化。也應該明白該例示實施例或者該等例示實施例僅為例子,並不欲限制本發明之範疇、可應用性與組構於任何方式。更確切地說,該前述之詳細說明將提供熟悉此項技術者實施該例示實施例或該等例示實施例之便利的指引。應該了解在元件之功能和配置上能夠作各種改變而不會偏離本發明之範疇,如提出於所附申請專利範圍與其合法的等效者。
20...場效電晶體(FET)
22...矽基板
23、294...閘極絕緣體
24、62、296...閘電極
26...電晶體通道
28...未摻雜矽鍺
30...雜質摻雜矽鍺(SiGe)
32...箭頭
34...源極
36...汲極
40...P通道場效電晶體
42、242...半導體基板
44、244...薄矽層
46、246...絕緣層、絕緣體
48...矽載體晶圓
50、256...部分
52、252...淺溝槽隔離(STI)
54...閘極絕緣體
56...表面
58...閘電極形成材料層
60...蓋層
66...薄二氧化矽層
68...通道區域
70...側壁形成材料層
72、78、86、172、178...側壁間隔件
74、80、174、180、254、300...凹槽
76、82...應力引發材料(層)
84...植入物
90...源極區域
92...汲極區域
94...矽化物形成金屬層
96、97、98...接觸件
140、240、292...PFET
170...側壁間隔件形成材料層
174...凹槽
176、182...SiGe層
248...單晶矽基板
258...矽層
260...表面
290...HOT
297...通道區域
298...第一嵌入之未摻雜磊晶矽鍺層
302...第二雜質摻雜之嵌入磊晶矽鍺層
304...第二凹槽
上文結合隨後的圖式說明本發明,其中相似的元件符號表示相似的元件,以及其中第1圖示意地顯示根據本發明之一個實施例之場效電晶體之剖面圖;第2至13圖示意地顯示根據本發明之實施例之受應力之場效電晶體之製造方法步驟之剖面圖;第14至18圖示意地顯示根據本發明之另外的實施例之受應力之場效電晶體之製造方法步驟之剖面圖;以及第19至22圖顯示根據本發明之另一實施例之受應力之P通道場效電晶體之製造方法步驟之剖面圖。
20...場效電晶體(FET)
22...矽基板
23...閘極絕緣體
24...閘電極
26...電晶體通道
28...未摻雜矽鍺
30...雜質摻雜矽鍺(SiGe)
32...箭頭
34...源極
36...汲極

Claims (17)

  1. 一種受應力之場效電晶體,包括:矽基板;閘極絕緣體,覆於該矽基板上;閘電極,覆於該閘極絕緣體上;通道區域,在該矽基板中且位於該閘電極之下方;未摻雜之磊晶生長嵌入矽鍺區域,具有第一厚度且接觸該通道區域;以及原位雜質摻雜之磊晶生長嵌入矽鍺區域,具有大於該第一厚度之第二厚度且與該通道區域分隔開。
  2. 如申請專利範圍第1項之受應力之場效電晶體,其中,該矽基板包括<110>方向矽基板,使第一絕緣層與第二單晶矽層覆於該矽基板上。
  3. 如申請專利範圍第1項之受應力之場效電晶體,其中,該矽基板包括覆於絕緣層上之單晶矽層。
  4. 一種用於製造受應力之場效電晶體之方法,該受應力之場效電晶體包含單晶矽基板,該方法包括下列步驟:沉積與圖案化覆於該矽基板上之多晶矽層,以形成閘電極,該閘極電定義位於該矽基板中該閘電極下方之通道區域;沉積第一層之間隔件形成材料覆於該閘電極上;非等向性蝕刻該第一層以於該閘電極上形成第一側壁間隔件;使用該閘電極與該側壁間隔件作為蝕刻遮罩來蝕 刻第一凹槽至該矽基板中;磊晶生長未摻雜之嵌入矽鍺層於該第一凹槽中;沉積第二層之間隔件形成材料覆於該閘電極與該第一側壁間隔件上;非等向性蝕刻該第二層以於該第一側壁間隔件上形成第二側壁間隔件;使用該閘電極與該第二側壁間隔件作為蝕刻遮罩來蝕刻第二凹槽至該矽基板中;磊晶生長原位雜質摻雜之嵌入矽鍺層於該第二凹槽中;以及形成電性接觸件至該閘極及至該原位雜質摻雜之嵌入矽鍺層。
  5. 如申請專利範圍第4項之方法,復包括下列步驟:移除該第一側壁間隔件與該第二側壁間隔件;植入導電率判定離子至該未摻雜之嵌入矽鍺層與該原位雜質摻雜之嵌入矽鍺層中以形成源極與汲極延伸區。
  6. 如申請專利範圍第5項之方法,復包括下列步驟:沉積第三層之間隔件形成材料覆於該閘電極上;非等向性蝕刻該第三層以於該閘電極上形成第三側壁間隔件;以及熱退火該原位雜質摻雜之嵌入矽鍺層以形成源極與汲極區域。
  7. 如申請專利範圍第6項之方法,復包括下列步驟: 於該閘電極上與在該原位雜質摻雜之嵌入矽鍺層之表面形成金屬矽化物,該金屬矽化物自行對齊該第三側壁間隔件。
  8. 如申請專利範圍第4項之方法,其中,磊晶生長未摻雜之嵌入矽鍺層之該步驟包括磊晶生成接觸該通道區域之未摻雜之嵌入矽鍺層之步驟。
  9. 如申請專利範圍第8項之方法,其中,磊晶生長原位雜質摻雜之嵌入矽鍺層之該步驟包括磊晶生長與該通道區域分隔開原位雜質摻雜之嵌入矽鍺層之步驟。
  10. 如申請專利範圍第4項之方法,其中,磊晶生長未摻雜之嵌入矽鍺層之該步驟包括磊晶生長具有第一厚度之未摻雜之嵌入矽鍺層之步驟,以及其中,磊晶生長原位雜質摻雜之嵌入矽鍺層之該步驟包括磊晶生長具有第二厚度之原位雜質摻雜之嵌入矽鍺層之步驟,該第二厚度大於該第一厚度。
  11. 一種用於製造受應力之場效電晶體之方法,包括下列步驟:形成絕緣體上覆矽基板,該基板包括位於矽基板上之絕緣體層上之矽層;形成閘電極覆於該矽層上;磊晶生長第一未摻雜矽鍺層,該第一未摻雜矽鍺層嵌入至該矽層中且對齊該閘電極;磊晶生長第二雜質摻雜矽鍺層,該第二雜質摻雜矽鍺層嵌入至該矽層中且與該閘電極分隔開。
  12. 如申請專利範圍第11項之方法,復包括下列步驟:植入導電率判定離子至該第一未摻雜矽鍺層、該第二雜質摻雜矽鍺層與該矽層中以形成源極與汲極延伸區。
  13. 如申請專利範圍第11項之方法,其中,磊晶生長第一未摻雜矽鍺層之該步驟包括磊晶生長嵌入至該矽層與該第二雜質摻雜矽鍺層之一部分中之第一未摻雜矽鍺層之步驟。
  14. 如申請專利範圍第11項之方法,其中,磊晶生長第二雜質摻雜矽鍺層之該步驟包括磊晶生長嵌入至該矽層中且延伸穿過該第一未摻雜矽鍺層之一部分之第二雜質摻雜矽鍺層之步驟。
  15. 一種用於製造受應力之場效電晶體之方法,包括下列步驟:形成絕緣體上覆矽基板,該基板包括位於矽基板上之絕緣體層上之矽層;蝕刻開口延伸穿過該矽層與該絕緣體層以暴露該矽基板之表面之一部分;生長二氧化矽層於該矽基板之該表面;形成多晶矽閘電極於該二氧化矽層上;蝕刻第一凹槽至該矽基板中且對齊該閘電極;磊晶生長第一嵌入矽鍺層以填滿該第一凹槽;蝕刻第二凹槽至該矽基板中且與該閘電極分隔開;以及 磊晶生長第二嵌入矽鍺層以填滿該第二凹槽。
  16. 如申請專利範圍第15項之方法,復包括下列步驟:於該矽層中製造場效電晶體。
  17. 如申請專利範圍第15項之方法,其中,形成絕緣體上覆矽基板之該步驟包括在具有<110>方向之矽基板上之絕緣體層上形成具有<100>方向之矽層之步驟。
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