JP4604637B2 - 半導体装置および半導体装置の製造方法 - Google Patents
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- 239000004065 semiconductor Substances 0.000 title claims description 97
- 238000004519 manufacturing process Methods 0.000 title claims description 37
- 229910000577 Silicon-germanium Inorganic materials 0.000 claims description 204
- 239000000758 substrate Substances 0.000 claims description 100
- 229910052710 silicon Inorganic materials 0.000 claims description 20
- 238000000034 method Methods 0.000 claims description 17
- 229910052732 germanium Inorganic materials 0.000 claims description 16
- 239000010410 layer Substances 0.000 description 448
- 239000010408 film Substances 0.000 description 92
- 229910004298 SiO 2 Inorganic materials 0.000 description 24
- 229910052581 Si3N4 Inorganic materials 0.000 description 17
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 17
- 239000013078 crystal Substances 0.000 description 11
- 230000001681 protective effect Effects 0.000 description 10
- 238000005530 etching Methods 0.000 description 9
- 238000002955 isolation Methods 0.000 description 9
- 229910021332 silicide Inorganic materials 0.000 description 6
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 6
- 239000012535 impurity Substances 0.000 description 5
- 230000015572 biosynthetic process Effects 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- 238000009792 diffusion process Methods 0.000 description 4
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 3
- 229910052796 boron Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 239000002344 surface layer Substances 0.000 description 3
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 239000001257 hydrogen Substances 0.000 description 2
- 229910052739 hydrogen Inorganic materials 0.000 description 2
- 239000012212 insulator Substances 0.000 description 2
- 239000003870 refractory metal Substances 0.000 description 2
- 239000010409 thin film Substances 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- 229910017052 cobalt Inorganic materials 0.000 description 1
- 239000010941 cobalt Substances 0.000 description 1
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 239000011261 inert gas Substances 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
- 230000002040 relaxant effect Effects 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
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- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
- H01L21/2003—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy characterised by the substrate
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- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
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- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823807—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78684—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising semiconductor materials of Group IV not being silicon, or alloys including an element of the group IV, e.g. Ge, SiN alloys, SiC alloys
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- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
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- Thin Film Transistor (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Description
(第1実施形態)
図1は、本実施形態のCMOSデバイスの断面構成図である。この図に示すように、表面が面方位(110)のSi単結晶層からなるp型のSi基板(基板11)には、NMOS領域(第1の素子領域)AとPMOS領域(第2の素子領域)Bとが設けられている。基板11上には、基板11の表面の面方位(110)を維持した状態で緩和SiGe層12が設けられている。この緩和SiGe層12は、ここでの図示は省略したが、例えば上層に向けてSi層中のGe組成比が0からxとなるまで徐々に多くなるように、Si層中にGeを混入した傾斜SiGe層と、この傾斜SiGe層上に設けられたSi層中のGe組成比がxのSi1-xGex層とで構成されることとする。
図6に本実施形態のCMOSトランジスタの断面構成図を示す。この図に示すように、本実施形態では、第1実施形態における基板11に表面が(100)の面方位のSi単結晶層からなるp型のSi基板を用い、この基板11上に、PMOS領域(第1の素子領域)B’とNMOS領域(第2の素子領域)A’とが設けられた例について説明する。なお、第1実施形態と同様の構成には同一の番号を付して説明することとする。
Claims (5)
- Si基板上に設けられた緩和SiGe層上に絶縁層を介して設けられたNMOSトランジスタ領域である第1の素子領域と、前記緩和SiGe層上に設けられたPMOSトランジスタ領域である第2の素子領域とを備えた半導体装置であって、
前記第1の素子領域の基板上に設けられるとともに、前記基板の表面と異なり、面方位が(100)の引っ張り歪み状態の歪みSi層からなる第1の半導体層と、
前記第2の素子領域の基板上に設けられるとともに、前記基板の表面と同じく面方位(110)の圧縮歪み状態の歪みSiGe層からなる第2の半導体層とを備え、
前記緩和SiGe層を、
前記Si基板の表面の面方位(110)を維持した状態で、かつ、上層に向けてSi層中のGe組成比が0からXとなるまで徐々に多くなるように、Si層中にGeを混入した傾斜SiGe層と、この傾斜SiGe層上に設けられたSi層中のGe組成比がXのSi1-xGex層とで構成した
ことを特徴とする半導体装置。 - 前記歪みSiGe層は、前記緩和SiGe層のSi1-xGex層よりも高いGe組成比を有するSi1-yGey層からなることを特徴とする請求項1記載の半導体装置。
- Si基板上に設けられた緩和SiGe層上に絶縁層を介して設けられたPMOSトランジスタ領域である第1の素子領域と、前記緩和SiGe層上に設けられたNMOSトランジスタ領域である第2の素子領域とを備えた半導体装置であって、
前記第1の素子領域の基板上に設けられるとともに、前記基板の表面と異なり、面方位が(110)の圧縮歪み状態の歪みSiGe層からなる第1の半導体層と、
前記第2の素子領域の基板上に設けられるとともに、前記基板の表面と同じく面方位(100)の引っ張り歪み状態の歪みSi層からなる第2の半導体層とを備え、
前記緩和SiGe層を、
前記Si基板の表面の面方位(100)を維持した状態で、かつ、上層に向けてSi層中のGe組成比が0からXとなるまで徐々に多くなるように、Si層中にGeを混入した傾斜SiGe層と、この傾斜SiGe層上に設けられたSi層中のGe組成比がXのSi1-xGex層とで構成した
ことを特徴とする半導体装置。 - NMOSトランジスタ領域である第1の素子領域と、PMOSトランジスタ領域である第2の素子領域とを同一のSi基板に備えた半導体装置の製造方法であって、
Si基板上に、上層に向けてSiに対するGeの組成比を0からxまで徐々に増大させた傾斜SiGe層をエピタキシャル成長させた後、この傾斜SiGe層上に、SiとGeの組成比が1−X:XのSi1-xGex層をエピタキシャル成長させて緩和SiGe層を形成する工程と、
前記Si基板上に絶縁層を形成するとともに、前記Si基板の表面と異なり、面方位が(100)の引っ張り歪み状態の歪みSi層からなる第1の半導体層を前記絶縁層上に貼り合わせる工程と、
前記第2の素子領域の前記絶縁層および前記第1の半導体層を除去して前記緩和SiGe層を露出する工程と、
露出された第2の素子領域の緩和SiGe層上に、前記緩和SiGe層の表面の面方位(110)を維持した状態で、圧縮歪み状態の歪みSiGe層からなる第2の半導体層をエピタキシャル成長させる工程とを有する
ことを特徴とする半導体装置の製造方法。 - 前記歪みSiGe層は、前記緩和SiGe層のSi1-xGex層よりも高いGe組成比を有するSi1-yGey層としたことを特徴とする請求項4記載の半導体装置の製造方法。
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JP2004294562A JP4604637B2 (ja) | 2004-10-07 | 2004-10-07 | 半導体装置および半導体装置の製造方法 |
US11/241,108 US7538390B2 (en) | 2004-10-07 | 2005-09-30 | Semiconductor device with PMOS and NMOS transistors |
US12/425,476 US7871878B2 (en) | 2004-10-07 | 2009-04-17 | Method of fabricating PMOS and NMOS transistor on the same substrate |
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US20080121932A1 (en) | 2006-09-18 | 2008-05-29 | Pushkar Ranade | Active regions with compatible dielectric layers |
US7385257B2 (en) * | 2006-04-26 | 2008-06-10 | International Business Machines Corporation | Hybrid orientation SOI substrates, and method for forming the same |
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US8168548B2 (en) * | 2006-09-29 | 2012-05-01 | Tokyo Electron Limited | UV-assisted dielectric formation for devices with strained germanium-containing layers |
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FR2918793B1 (fr) * | 2007-07-11 | 2009-10-09 | Commissariat Energie Atomique | Procede de fabrication d'un substrat semiconducteur-sur- isolant pour la microelectronique et l'optoelectronique. |
JP2009076731A (ja) * | 2007-09-21 | 2009-04-09 | Renesas Technology Corp | 半導体装置およびその製造方法 |
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JP2000286418A (ja) * | 1999-03-30 | 2000-10-13 | Hitachi Ltd | 半導体装置および半導体基板 |
JP2001044425A (ja) * | 1999-07-30 | 2001-02-16 | Hitachi Ltd | 半導体装置 |
JP2001160594A (ja) * | 1999-09-20 | 2001-06-12 | Toshiba Corp | 半導体装置 |
JP2001338988A (ja) * | 2000-05-25 | 2001-12-07 | Hitachi Ltd | 半導体装置及びその製造方法 |
JP2002359367A (ja) * | 2001-05-31 | 2002-12-13 | Sharp Corp | 半導体基板、その製造方法及び半導体装置 |
JP2003017671A (ja) * | 2001-06-29 | 2003-01-17 | Mitsubishi Materials Silicon Corp | 半導体基板及び電界効果型トランジスタ並びにこれらの製造方法 |
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JPS59177957A (ja) * | 1983-03-28 | 1984-10-08 | Fujitsu Ltd | チツプ実装方法 |
JP3326427B2 (ja) * | 1996-09-17 | 2002-09-24 | 松下電器産業株式会社 | 半導体装置及びその製造方法 |
US6633066B1 (en) * | 2000-01-07 | 2003-10-14 | Samsung Electronics Co., Ltd. | CMOS integrated circuit devices and substrates having unstrained silicon active layers |
US6940089B2 (en) * | 2001-04-04 | 2005-09-06 | Massachusetts Institute Of Technology | Semiconductor device structure |
US6974735B2 (en) * | 2001-08-09 | 2005-12-13 | Amberwave Systems Corporation | Dual layer Semiconductor Devices |
US20050274978A1 (en) * | 2004-05-27 | 2005-12-15 | Antoniadis Dimitri A | Single metal gate material CMOS using strained si-silicon germanium heterojunction layered substrate |
US7253045B1 (en) * | 2004-07-13 | 2007-08-07 | Advanced Micro Devices, Inc. | Selective P-channel VT adjustment in SiGe system for leakage optimization |
JP4604637B2 (ja) * | 2004-10-07 | 2011-01-05 | ソニー株式会社 | 半導体装置および半導体装置の製造方法 |
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Patent Citations (8)
Publication number | Priority date | Publication date | Assignee | Title |
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JPH04372166A (ja) * | 1991-06-21 | 1992-12-25 | Matsushita Electric Ind Co Ltd | 半導体装置の製造方法 |
JPH09219524A (ja) * | 1996-02-09 | 1997-08-19 | Toshiba Corp | 半導体装置及びその製造方法 |
JP2000286418A (ja) * | 1999-03-30 | 2000-10-13 | Hitachi Ltd | 半導体装置および半導体基板 |
JP2001044425A (ja) * | 1999-07-30 | 2001-02-16 | Hitachi Ltd | 半導体装置 |
JP2001160594A (ja) * | 1999-09-20 | 2001-06-12 | Toshiba Corp | 半導体装置 |
JP2001338988A (ja) * | 2000-05-25 | 2001-12-07 | Hitachi Ltd | 半導体装置及びその製造方法 |
JP2002359367A (ja) * | 2001-05-31 | 2002-12-13 | Sharp Corp | 半導体基板、その製造方法及び半導体装置 |
JP2003017671A (ja) * | 2001-06-29 | 2003-01-17 | Mitsubishi Materials Silicon Corp | 半導体基板及び電界効果型トランジスタ並びにこれらの製造方法 |
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US7871878B2 (en) | 2011-01-18 |
US20060076622A1 (en) | 2006-04-13 |
US7538390B2 (en) | 2009-05-26 |
JP2006108468A (ja) | 2006-04-20 |
US20090221134A1 (en) | 2009-09-03 |
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