TWI483315B - 用於製造受應力之ｍｏｓ裝置之方法 - Google Patents

用於製造受應力之ｍｏｓ裝置之方法 Download PDF

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TWI483315B
TWI483315B TW095133589A TW95133589A TWI483315B TW I483315 B TWI483315 B TW I483315B TW 095133589 A TW095133589 A TW 095133589A TW 95133589 A TW95133589 A TW 95133589A TW I483315 B TWI483315 B TW I483315B
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recess
germanium
single crystal
layer
substrate
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TW200739745A (en
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Frank Wirbeleit
Linda R Black
Igor Peidous
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Globalfoundries Us Inc
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Description

用於製造受應力之MOS裝置之方法
本發明大體上係關於用於製造受應力之MOS裝置之方法，尤係關於用於製造受應力之NMOS及CMOS裝置之方法。
現今積體電路(IC)大多藉由利用複數個內部連接之場效電晶體(FET)(亦稱為金屬氧化半導體場效電晶體(MOSFET)，或僅稱為MOS電晶體)而實行。MOS電晶體包括作為控制電極的閘極電極和彼此隔開能讓電流在其間流動的源極及汲極電極。施加至該閘極電極之控制電壓透過該源極及汲極電極間的通道來控制電流的流動。
與雙載子電晶體(bipolar transistor)對照，MOS電晶體為主載子元件(majority carrier device)。通常由互導(transconductance)(gm )定義之MOS電晶體的增益係與該電晶體通道之該主載子的遷移率成比例。由於載流能力(the current carrying capability)因而MOS電晶體效能與該電晶體通道中之該主載子的遷移率成比例。電洞(P通道MOS(PMOS)電晶體之主載子)的遷移率能藉由對該通道施加壓縮縱向應力(compressive longitudinal stress)而增加。眾所皆知壓縮縱向應力係能藉由在該電晶體通道終端嵌入例如矽鍺(SiGe)之材料而施加至矽MOS電晶體。然而，電子(N通道MOS(NMOS)電晶體之主載子)的遷移率則藉由此類壓縮縱向應力而降低。欲增加電子之遷移率，則必須施加張應力(tensile stress)至該MOS電晶體之通道。
因此，希望提供一種製造具有增強主載子遷移率之NMOS電晶體的方法。亦希望提供一種用於製造CMOS裝置的方法，其中該NMOS及PMOS電晶體皆具有增強的主載子遷移率。再者，透過後續的詳述及附加的申請專利範圍結合隨附圖式及前述的技術背景，本發明其他希望的特徵及特性將變得明顯。
根據本發明之一個實施例，一種方法包括提供具有表面及緊鄰該表面之通道的單晶半導體基板的步驟。具有第一邊緣及第二邊緣的閘極電極係形成覆於該單晶半導體基板上。該基板係經過非等向性蝕刻而形成與該第一邊緣對齊之第一凹處及與該第二邊緣對齊之第二凹處。該基板進一步經過等向性蝕刻而在該基板中形成在該通道下方延伸之第三凹處。在該第三凹處中填入膨脹材料以在該通道施加向上力，而在該第一凹處及該第二凹處中填入接觸材料。將導電率決定離子注入於該接觸材料中以分別形成與該第一邊緣及該第二邊緣對齊之源極區域及汲極區域。
下列詳述僅作例示性，而非意於限定本發明或本發明之應用及使用。再者，本發明並非意於藉由任何前述之技術領域、先前技術及發明內容或下列詳述所提出之明示的或隱含的理論而受到限制。
第1圖至第9圖係根據本發明之各種實施例說明一種受應力之MOS裝置30及用於製造此種MOS裝置的方法步驟。在此圖示實施例中，受應力裝置30在此為由單一NMOS電晶體31及單一PMOS電晶體33圖示之CMOS裝置。透過下列敘述將變得清楚，本發明之各種實施例尤其係針對增強NMOS電晶體之該通道中電子的遷移率。然而，根據本發明之一個實施例，具有增強遷移率之NMOS電晶體與亦具有增強遷移率之PMOS一起製造以實現具有優秀特性的CMOS裝置。熟習該技術領域者可了解到本發明係可應用在單通道NMOS裝置或CMOS裝置。由根據本發明而製造之受應力之MOS裝置所形成的積體電路能包括大量的裝置(例如裝置30)，並亦可包括受應力及非受應力之P通道MOS電晶體和受應力及非受應力之N通道MOS電晶體兩者。
製造MOS電晶體的步驟係為習知，故為求簡潔，許多習知步驟在此僅簡單提出或完全省略而不提供該習知製程的細節。雖然該用語“MOS裝置”能適當地涉及具有金屬閘極及氧化閘極絕緣層的裝置，但該用語在全文中將用於關於任何包括位於閘極絕緣層(不論是氧化物或其他材料)上方的導電閘極電極(不論是金屬或其他導電材料)，其中該閘極絕緣層係依次位於半導體基板上方。
如第1圖之剖面圖所示，根據本發明之實施例，受應力之MOS裝置30之製造係由提供具有表面32之半導體基板36開始。該半導體基板可以是任何單晶半導體材料，但最好是單晶矽基板，其中該用語“矽基板”在此係用以包含在半導體產業常用的極純的矽材料。為求容易討論但不做限定用，半導體基板36在此係稱作矽基板。熟習該技術領域者將可以了解到半導體基板36亦可以由其他半導體材料形成，例如在矽晶格中含有約10到30之間的原子量百分比的鍺的矽鍺(SiGe)。矽基板36可以是一大塊矽晶圓或是在絕緣層35(一般習知稱為絕緣層上矽或SOI)上的薄薄一層矽層34，其中該絕緣層35依次由矽載子晶圓37(但最好如在此所圖示，不做限定，為SOI晶圓)所支撐。不論是由單晶矽或某些其他單晶半導體材料所形成，如果該基板為SOI基板，則形成基板36及(特別是)薄層34的該單晶材料之特徵將在於與該材料之結晶結構有關的晶格常數。欲製造CMOS裝置，部分薄矽層34將摻雜P型雜質摻雜物(P井區(well)38)用以製造N通道MOS電晶體，而其他部分將摻雜N型雜質摻雜物(N井區39)用以製造P通道MOS電晶體。該P井區及N井區係能藉由例如離子注入摻雜至適當的導電率。淺溝隔離(shallow trench isolation,STI)40或其他形式的電子隔離形成於該半導體基板中，且最好延伸穿越薄矽層34到絕緣層35以電性隔離所實行之該電路功能所需的個別裝置。眾所皆知，有許多製程能用來形成該STI，故該製程在此將不做詳述。大體而言，STI包括蝕刻入該半導體基板之表面的淺溝，且該淺溝隨後係填入絕緣材料。在該淺溝填入絕緣材料後，該表面通常藉由化學機械研磨平坦化(chemical mechanical planarization,CMP)作平坦化處理。該STI一般在矽基板36的P型主動區域42圍出P井區38，及在N型主動區域44圍出N井區39。雖然沒有圖示，如有需要可以有複數個N型主動區域及複數個P型主動區域(全部藉由該STI而彼此電性隔離)以實行所希望的積體電路功能。
再次參照第1圖，一層閘極絕緣層60形成於該薄矽層34表面上。該閘極絕緣層可以是藉由在氧化環境加熱該矽基板而形成的熱成長的二氧化矽，或者可以是沉積的絕緣層，例如氧化矽、氮化矽、高介電常數絕緣體(例如矽酸鉿氧化合物(HfSiO))或之類等等。沉積的絕緣層可以藉由化學氣相沉積(chemical vapor deposition,CVD)、低壓化學氣相沉積(low pressure chemical vapor deposition,LPCVD)或電漿強化化學氣相沉積(plasma enhanced chemical vapor deposition,PECVD)來沉積。如第1圖所示，閘極絕緣層60為僅在該矽層表面成長的熱成長二氧化矽。該閘極絕緣層材料典型地厚度為1至10奈米(nm)。假使該半導體基板為除了矽之外的半導體材料，則有利於沉積該閘極絕緣層。另一種做法是，假使該基板為矽鍺，則有利於在該矽鍺表面上磊晶成長一層薄的受應力矽層(未圖示)並熱氧化該受應力矽層以形成二氧化矽閘極絕緣層。根據本發明之一個實施例，一層閘極電極形成材料，例如多晶矽62，係沉積在該閘極絕緣層上方。該多晶矽層最好沉積為未摻雜的多晶矽然後藉由離子注入摻雜雜質。該多晶矽材料可以藉由矽烷的氫還原再藉由LPCVD沉積至例如厚度約100至200奈米。硬遮罩材料(例如氧化矽、氮化矽或氮氧化矽)層64沉積在該多晶矽表面上方。該硬遮罩材料亦可藉由LPCVD沉積至厚度約50奈米。
多晶矽層62及硬遮罩層64經過光微影圖案化(photolithographically patterned)以形成如第2圖之剖面圖所示之MOS電晶體閘極電極66及68。閘極電極66位在薄矽層34之P型主動區域42及P井區38之部分上方，該薄矽層34在表面32將形成NMOS電晶體31的通道70。以相似方式，閘極電極68覆於N型主動區域44及N井區39之部分上，該主動區域44及N井區39亦在表面32形成PMOS電晶體33的通道72。該多晶矽可藉由例如電漿蝕刻以Cl或HBr/O2 化學作用而蝕刻成希望的圖案，且該硬遮罩可藉由例如電漿蝕刻以CHF3 、CF4 或SF6 化學作用而蝕刻成希望的圖案。在該閘極電極圖案化後，根據本發明之一個實施例，藉由在氧化環境中加熱該多晶矽，一層薄氧化矽層74熱成長於閘極電極66之相對側壁75及85上，以及一層薄氧化矽層76熱成長於閘極電極68之相對側壁77及87上。層74及76之厚度可成長至約2至5奈米。閘極電極66及68與層74及76能用作為離子注入遮罩以於該MOS電晶體之任一或兩者上形成源極與汲極延伸區(source and drain extensions)(未圖示)。此外，層74及76保護該閘極電極輪廓(profile)。形成多個源極及汲極區域之可能方法和需求係為習知，但與本發明並不密切相關，故不需在此說明。眾所皆知，圖案化之光阻層能在該PMOS電晶體之該源極及汲極延伸區之注入期間用來遮罩該N井區區域，而另一層圖案化之光阻層能在該NMOS電晶體之該源極及汲極延伸區之注入期間用來遮罩該P－井區區域。
根據本發明之一個實施例，如第3圖所示，側壁間隔物80係分別形成於閘極電極66及68之該相對側壁75、85及77、87上之該薄氧化層上。該側壁間隔物可由氮化矽、氧化矽或之類等等藉由沉積一層該間隔物材料於該閘極電極上方，然後藉由反應性離子蝕刻利用CHF3 、CF4 或SF6 化學作用非等向性蝕刻該層而形成。側壁間隔物80、閘極電極66及68、該閘極電極頂端上之該硬遮罩及STI 40係皆作為蝕刻遮罩，用以蝕刻初始凹處82及84在該矽基板中於N通道閘極電極66之相對兩邊彼此相隔自我對齊，並用以蝕刻凹處86及88於P通道閘極電極68之相對兩邊彼此相隔自我對齊。該凹處相交該通道70及72之端部。該凹處可經由例如反應性離子蝕刻利用Cl或HBr/O2 化學作用而非等向性蝕刻。各個該凹處最好具有約0.04至0.1微米的深度。
如第4圖所示，該方法根據本發明之實施例係藉由沉積另一層之間隔物形成材料90而繼續進行。光阻層92施加在該間隔物形成材料層上並圖案化以留下該光阻層，該光阻層係用以保護PMOS電晶體33及暴露出NMOS電晶體31。如前所述，該間隔物形成材料可以是氮化矽、氧化矽或之類等等藉由例如LPCVD沉積而成。
如第5圖所示，間隔物形成材料層90之暴露部分係非等向性蝕刻以形成側壁間隔物94在初始凹處82及84之垂直邊緣上。間隔物形成材料層之該非等向性蝕刻在保護通道70之邊緣的同時暴露出初始凹處82及84之底部。
如第6圖所示，該初始凹處之該暴露底部係藉由電漿蝕刻利用HBr/Cl與CF4 、氬及氧一起化學作用而等向性地蝕刻以改善等向性。該等向性蝕刻增加該初始凹處之深度並蝕刻通道70下方之側面。最好持續該蝕刻直到凹處96在通道70下方完全延伸為止。假使半導體基板36為SOI基板，則凹處96最好延伸穿越該薄矽層34之厚度到絕緣層35。在蝕刻凹處96期間，側壁間隔物94防止形成通道70之該半導體材料的蝕刻。通道70因此餘留作為覆於凹處96上之半導體材料的橋樑並從該STI在該主動區域之一端延伸至該STI在該主動區域之另一端。
在蝕刻凹處96之後，該方法根據本發明之一個實施例藉由去除側壁間隔物94及光阻層92而繼續進行。眾所皆知，光阻層92亦可在蝕刻凹處96之前去除。剩餘的層90則繼續遮罩PMOS電晶體33。凹處96填入膨脹材料100，例如氮化矽、碳化矽或其他絕緣物(例如沸石)如第7圖所示。根據較佳實施例，膨脹材料100為熱成長的二氧化矽。該膨脹材料填入凹處96並在通道70施加向上力如箭頭101所示。通道70上之該向上力對該通道施加單軸的張應力，而此種張應力增強了NMOS電晶體31之該通道之主載子電子的遷移率。二氧化矽可藉由例如在氧化環境中加熱該通道70之矽而成長以填入凹處96。矽形成通道70之較低部位經過氧化，留下一層矽在該氧化物上面。二氧化矽佔去較該氧化過程所消耗之矽還大之體積。另一種做法是，可藉由例如LPCVD或PECVD沉積膨脹材料(例如氮化矽或任何其他絕緣材料)來填入凹處96。此種沉積材料亦可部分地填入凹處82及84如虛線103所指。在高溫沉積情況中，隨著該材料為後續沉積降溫，該材料膨脹並對該通道施加希望的向上力。另一種做法是，針對那些在低溫沉積的材料，可藉由加熱循環實行該希望的向上力以導致該沉積材料至少部分地形成結晶結構。在沉積該膨脹材料之後，可沉積多晶矽、多晶矽鍺或其他導體或半導體材料110以填入初始凹處82及84。在處理NMOS電晶體31期間，剩餘的間隔物形成層90則保護PMOS電晶體33。
根據本發明之一個實施例，在沉積材料110之後，去除剩餘的間隔物形成層90並沉積及光微影圖案化氧化矽或其他絕緣物112之遮罩層以提供保護的遮罩層在NMOS電晶體31上，如第8圖之剖面圖所示。具有晶格常數大於該主(host)薄矽層34之晶格常數的應力引發(stressinducing)半導體材料層120係選擇性地磊晶成長以填入緊鄰PMOS電晶體33之通道72的凹處86及88。對主矽材料而言，該應力感應半導體材料層可以是例如具有約10至30原子量百分比的鍺的矽鍺(SiGe)。該SiGe之晶格常數大於矽。一般而言，該應力引發半導體材料層可以是任何假晶(pseudomorphic)材料，該假晶材料能磊晶成長於具有大於該主半導體材料之晶格常數之晶格常數之該半導體基板上。該磊晶成長層120在凹處86及88之側壁及底部形成核心。用於以選擇方式在矽或其他半導體基質(semiconductor host)上磊晶成長SiGe及其他應力引發材料之方法係為習知而在此將不作敘述。持續該磊晶成長直到凹處86及88填滿為止。在該層120之選擇成長期間，遮罩層112保護NMOS電晶體31，故沒有SiGe沉積在該NMOS電晶體。因為矽鍺之晶格常數大於矽，因此層120係對PMOS電晶體33之通道72施加壓縮縱向應力，如箭頭122所指示。此種壓縮縱向應力增加了該PMOS電晶體之通道中主載子電洞的遷移率。
MOS電晶體之源極及汲極區域能在沉積材料110及該選擇磊晶成長層120的過程期間部份地或完整地原地(in－situ)摻雜導電率決定雜質。不然，在凹處82及84沉積材料110、在凹處86及88成長該應力引發材料120及去除遮罩層112之後，在凹處86及88將P型導電率決定離子注入該應力引發材料以形成PMOS電晶體33之源極區域126及汲極區域128，如第9圖所示。相似地，在凹處82及84將N型導電決定離子注入材料110以形成NMOS電晶體31之源極區域130及汲極區域132。能以習知方式利用適當的遮罩(例如圖案化的光阻層)在該P通道源極及汲極區域之注入期間來遮罩NMOS電晶體31及在該N通道源極及汲極區域之注入期間來遮罩PMOS電晶體33。
受應力之MOS裝置30能藉由習知步驟(未圖示)完成，例如沉積一層介電材料，在該介電材料蝕刻開孔以暴露出該源極及汲極區域之部分，並形成延伸穿透該開孔以電性接觸該源極及汲極區域之金屬噴敷(metallization)。亦可應用及圖案化另外的層間介電材料層、額外的內部連接金屬噴敷層及之類等等以實現所實行之積體電路的適當電路功能。
雖然在前面詳述中已提出至少一個例示實施例，但應了解存在著大量的變化。亦應了解到例示實施例僅作範例，並無意限制本發明之範疇、應用性或組態於任何方式。當然，前面詳述將提供熟習該技術領域者方便實行該例示實施例的準則。應了解到在不違背附加的申請專利範圍及其法律等效範圍所提出之本發明的範疇下，係可對元件的功能及配置作各種改變。
30．．．受應力MOS裝置
31．．．NMOS電晶體
32．．．表面
33．．．PMOS電晶體
34．．．薄矽層
35．．．絕緣層
36．．．半導體基板；矽基板
37．．．矽載子晶圓
38．．．P井區
39．．．N井區
40．．．淺溝隔離；STI
42．．．P型主動區域
44．．．N型主動區域
60．．．閘極絕緣層
62．．．多晶矽層
64．．．硬遮罩層
66、68．．．閘極電極
70、72．．．通道
74、76．．．薄氧化矽層
75、77、85、87．．．側壁
80、94．．．側壁間隔物
82、84、86、88、96．．．凹處
90．．．間隔物形成材料；間隔物形成材料層；間隔物形成層
92．．．光阻層
100．．．膨脹材料
101．．．向上力
103．．．填入沉積材料
110．．．半導體材料；材料
112．．．絕緣物；遮罩層
120．．．半導體材料層；磊晶成長層；應力引發材料
122．．．壓縮縱向應力
126、130．．．源極區域
128、132．．．汲極區域
本發明將結合隨附圖式敘述，其中相似之參考符號代表相似的元件，而其中第1圖至第9圖係以剖面圖示意地說明根據本發明之各種實施例的受應力MOS裝置及其製造方法。
30．．．受應力MOS裝置
31．．．NMOS電晶體
33．．．PMOS電晶體
34．．．薄矽層
35．．．絕緣層
37．．．矽載子晶圓
39．．．N井區
40．．．淺溝隔離；STI
44．．．N型主動區域
60．．．閘極絕緣層
64．．．硬遮罩層
66、68．．．閘極電極
72．．．通道
74．．．薄氧化矽層
77、87．．．側壁
80．．．側壁間隔物
82、84、86、88．．．凹處
90．．．間隔物形成材料；間隔物形成材料層；間隔物形成層
100．．．膨脹材料
101．．．向上力
103．．．填入沉積材料
110．．．半導體材料；材料

Claims (17)

  1. 一種用於製造受應力之MOS裝置之方法，包括下列步驟：提供具有表面及緊鄰該表面之通道的單晶半導體基板；形成閘極電極覆於該單晶半導體基板上，該閘極電極具有第一邊緣及第二邊緣；非等向性蝕刻該單晶半導體基板以形成與該第一邊緣對齊之第一凹處及與該第二邊緣對齊之第二凹處；施加遮罩層保護該第一凹處；等向性蝕刻該單晶半導體基板以在該單晶半導體基板中形成在該通道下方延伸之第三凹處；熱氧化該單晶半導體基板以在該第三凹處中填入二氧化矽以在該通道施加向上力；去除該遮罩層；在該第一凹處及該第二凹處中填入接觸材料；以及將導電率決定離子(conductivity determing ion)予以離子注入於該接觸材料中以分別形成與該第一邊緣及該第二邊緣對齊之源極區域及汲極區域。
  2. 如申請專利範圍第1項之方法，其中該提供單晶矽半導體基板之該步驟包括：提供絕緣物上覆矽基板之步驟，而該絕緣物上覆矽基板係包括絕緣物上之薄矽層。
  3. 如申請專利範圍第2項之方法，其中該等向性蝕刻步驟包括等向性蝕刻該薄矽層以形成從該通道延伸至該絕 緣物之第三凹處的步驟。
  4. 如申請專利範圍第1項之方法，其中提供單晶矽半導體基板之該步驟包括提供包括選自矽及矽鍺之材料的單晶矽半導體基板的步驟。
  5. 如申請專利範圍第1項之方法，其中該非等向性蝕刻步驟包括下列步驟：非等向性蝕刻該單晶矽半導體基板以形成第一凹處及第二凹處，各個該第一凹處及該第二凹處具有側壁且具有與初始第一深度相等的深度；以及在該第一凹處及該第二凹處之該側壁上形成側壁間隔物。
  6. 如申請專利範圍第5項之方法，其中該等向性蝕刻步驟包括在該側壁間隔物下方等向性蝕刻該單晶半導體基板的步驟。
  7. 如申請專利範圍第1項之方法，其中該提供單晶半導體基板之該步驟包括提供單晶矽基板的步驟，且其中填入該第三凹處之該步驟包括熱氧化該矽基板的步驟。
  8. 如申請專利範圍第1項之方法，其中填入該第三凹處之該步驟包括沉積選自由氧化矽及氮化矽所組成之群組之材料的步驟。
  9. 如申請專利範圍第1項之方法，其中在該第一凹處及該第二凹處中填入接觸材料之該步驟包括沉積選自由矽及矽鍺所組成之群組之半導體材料層的步驟。
  10. 一種用於製造具有矽基板及在該矽基板之表面之矽通 道的受應力之MOS裝置之方法，包括下列步驟：形成閘極電極覆於該通道上；在該矽基板中非等向性蝕刻第一凹處與該閘極電極對齊；進一步等向性蝕刻該矽基板導致該第一凹處在該通道下方延伸；熱氧化該矽基板以在該第一凹處中填入能在該通道施加向上力的二氧化矽；以及沉積多晶矽層以填入該第一凹處中。
  11. 一種用於製造具有矽基板之受應力之MOS裝置之方法，包括下列步驟：在該矽基板中形成N型區域及P型區域，該P型區域包含通道；形成第一閘極電極覆於該N型區域上且形成第二閘極電極覆於該P型區域上，該第二閘極電極覆於該通道上；在該矽基板中非等向性蝕刻第一凹處與該第一閘極電極對齊且在該矽基板中非等向性蝕刻第二凹處與該第二閘極電極對齊；施加遮罩層保護該第一凹處；等向性蝕刻該P型區域以增大該第二凹處且導致該第二凹處之部分在該通道下方延伸；熱氧化該P型區域以將二氧化矽填入在該通道下方延伸之該第二凹處之該部分中； 去除該遮罩層；以及在該第一凹處中選擇性地成長單晶應力引發半導體材料層，該層具有足以填滿該第一凹處之厚度。
  12. 如申請專利範圍第11項之方法，其中該選擇性地成長步驟包括磊晶成長矽鍺層的步驟。
  13. 如申請專利範圍第11項之方法，進一步包括在該第二凹處中填入選自由多晶矽及多晶矽鍺所組成之群組的半導體材料的步驟。
  14. 如申請專利範圍第13項之方法，進一步包括下列步驟：將P型導電率決定離子離子注入於在該第一凹處中之該單晶應力引發半導體材料層中；以及將N型導電率決定離子離子注入於填入該第二凹處中的該半導體材料中。
  15. 如申請專利範圍第11項之方法，其中該非等向性蝕刻步驟包括下列步驟：非等向性蝕刻該P型區域以蝕刻該第二凹處至第一深度，該第二凹處具有側壁；以及在該第二凹處之邊緣上形成側壁間隔物。
  16. 如申請專利範圍第15項之方法，其中該等向性蝕刻步驟包括利用該側壁間隔物作為蝕刻遮罩來等向性蝕刻該P型區域的步驟。
  17. 如申請專利範圍第11項之方法，其中該選擇性地成長步驟包括磊晶成長具有晶格常數大於單晶矽之晶格常數之半導體材料層的步驟。
TW095133589A 2005-09-26 2006-09-12 用於製造受應力之ｍｏｓ裝置之方法 TWI483315B (zh)

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