TWI416632B - 用於製造受應力之ｍｏｓ裝置之方法 - Google Patents

用於製造受應力之ｍｏｓ裝置之方法 Download PDF

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TWI416632B
TWI416632B TW095128099A TW95128099A TWI416632B TW I416632 B TWI416632 B TW I416632B TW 095128099 A TW095128099 A TW 095128099A TW 95128099 A TW95128099 A TW 95128099A TW I416632 B TWI416632 B TW I416632B
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trench
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crystal semiconductor
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Igor Peidous
Mario M Pelella
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    • H01L29/7848—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate the means being located in the source/drain region, e.g. SiGe source and drain
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Description

用於製造受應力之MOS裝置之方法
本發明大體上係關於製造受應力之MOS裝置之方法，且詳言之，係關於製造受應力之MOS裝置並維持該應力和應力引發增加於此等裝置中之方法。
多數之現代積體電路(IC)，係藉由使用複數個互連之場效電晶體(FET)(亦稱之為金屬氧化物半導體場效電晶體或簡稱MOS電晶體)而實施。MOS電晶體包括閘電極作為控制電極、以及分隔開之源極和汲極而於該源極和汲極間能流過電流。施加到該閘電極之控制電壓控制流經該源極和汲極之間通道之電流。
MOS電晶體，相對於雙極(bipolar)電晶體，而為多數載子裝置(majority carrier device)。MOS電晶體之增益(gain)，其通常由互導(transconductance)(gm )所定義，係正比於電晶體通道中多數載子之移動率(mobility)。MOS電晶體之電流載送能力係正比於通道中多數載子之移動率。可藉由施加壓縮之縱向應力於通道而增加於P通道MOS電晶體中多數載子(電洞)的移動率。可藉由施加伸張之橫向應力於通道而增加於N通道MOS電晶體中多數載子(電子)的移動率。於矽MOS電晶體中，能藉由適當地埋置譬如SiGe之應力引發材料於電晶體之矽基板中而施加此等應力於MOS電晶體之通道。該等應力係由於SiGe和主矽材料之間的晶格不匹配而引起。於SiGe中固有的應力再分配入主基板之鄰近區域中，也就是再分配入MOS電晶體之通道區域中。不幸的是，埋置之SiGe技術之其中一個問題是SiGe層的機械穩定性。在升高的溫度，由於錯位(dislocation)產生而使於SiGe層中的固有應力鬆弛(relax)。轉而，應力的減少造成應力引發移動率增加的減少，因此惡化裝置效能。
因此希望提供製造防止應力鬆弛之受應力之MOS裝置之方法。再者，由後續之詳細說明和所附之申請專利範圍，結合伴隨之圖式和上述技術領域和先前技術，本發明之其他希望之特徵和特性將變得清楚。
本發明提供一種在半導體基板中和上製造受應力之MOS裝置之方法。該方法包括下列步驟：形成覆於半導體基板上之閘電極，以及於該半導體基板中蝕刻第一溝槽和第二溝槽，該第一溝槽和第二溝槽形成為對準於該閘電極。選擇性地生長應力引發材料於第一溝槽和第二溝槽中，並將導電率判定雜質離子植入於應力引發材料中以在該第一溝槽中形成源極區域和在該第二溝槽中形成汲極區域。於該離子植入步驟後，沈積機械硬材料層覆於該應力引發材料上以維持於基板中引發之應力。
下列之詳細說明僅為例示性質，並不意欲限制本發明或本發明之應用和使用。再者，並不意欲由呈現於前面技術領域、先前技術、發明內容或下列詳細說明中所表示或暗示之任何理論而限定本發明。
第1至6圖顯示依照本發明之各種實施例之受應力之MOS裝置30及製造此種MOS裝置之方法步驟。於此例示實施例中，受應力之MOS裝置30由單一P通道MOS電晶體而予例示。從譬如裝置30之受應力之MOS裝置所形成之積體電路能包括大量之此等電晶體，且亦可包括未受應力之P通道MOS電晶體及受應力和未受應力之N通道MOS電晶體。
於製造MOS電晶體之各種步驟為已知，因此為了簡潔之目的，許多習知的步驟於此將僅簡短描述、或將其整個省略而不提供已知製程之細節。雖然術語“MOS裝置”適當地指為具有金屬閘電極和氧化物閘極絕緣體之裝置，但是該術語將用於全文中指任何包括位於閘極絕緣體(不管是否為氧化物或其他的絕緣體)之上之導電閘電極(不管是否為金屬或其他的導電材料)半導體裝置，該閘極絕緣體遂位於半導體基板之上。
如第1圖中所顯示，依照本發明之實施例之受應力之MOS裝置30之製造開始於提供半導體基板36。半導體基板較佳是單晶矽基板，其中此處所用之術語“矽基板”包含了一般用於半導體工業之相對純之矽材料。此處半導體基板36將可替代地稱為矽基板或為半導體基板，其係為了容易討論而不作為限制。矽基板36可以是大塊(bulk)矽晶圓、或是於絕緣層上之矽薄層(通常已知為絕緣體上覆矽(silicon－on－insulator或SOI)，該絕緣層遂由矽載體晶圓所支持，但是此處所顯示為大塊矽晶圓，而沒有限制。較佳的情況是，矽晶圓具有(100)或(110)方向(orientation)，以及至少晶圓之其中將要製造MOS裝置30之部分用N型雜質摻雜物摻雜(例如，N井(well))。N井能例如藉由離子植入而摻雜至適當的導電率(conductivity)。形成淺溝槽隔離(STI)(未圖示)於半導體基板中以電性隔離個別之裝置，如者所執行的電路功能所需。如已知的，有許多方法可用來形成STI，因此此處不須詳細描述該方法。一般而言，STI包括蝕刻入半導體基板之表面中之淺溝槽，接著用絕緣材料填充該淺溝槽。於淺溝槽填充有絕緣材料後，該表面通常被平坦化，例如，藉由化學機械平坦法(CMP)。
閘極絕緣體層60形成在矽基板36之表面。閘極絕緣體可以是藉由在氧化環境中加熱矽基板而形成之熱生長二氧化矽、或者可以是譬如氧化矽、氮化矽、例如HfSiO之高介電常數絕緣體、等等之沉積之絕緣體。可藉由化學氣相沉積(CVD)、低壓化學氣相沉積(LPCVD)、或電漿增強型化學氣相沉積(PECVD)來沉積沉積之絕緣體。閘極絕緣體材料典型為1至10奈米(nm)厚度。依照本發明之一個實施例，沈積多晶矽層62於閘極絕緣體層上。該多晶矽層較佳沉積為未摻雜之多晶矽，且後續藉由離子植入而被雜質摻雜。譬如氧化矽、氮化矽、或氧氮化矽之硬遮罩材料層64能沉積在多晶矽之表面上。多晶矽材料能藉由減少氫之矽烷(silane)之LPCVD而沉積至大約100 nm之厚度。硬遮罩材料亦能藉由LPCVD而沉積至大約50 nm之厚度。
硬遮罩層64和下方多晶矽層62被光微影圖案化以形成P通道MOS電晶體閘電極66，如第2圖中所示。閘電極66覆於將形成P通道MOS電晶體30之通道68之半導體基板36之部分上。能藉由例如於Cl或HBr/O2 化學中之電漿蝕刻而蝕刻多晶矽於所希望之圖案，以及能藉由例如於CHF3 、CHF4 、或SF6 化學中之電漿蝕刻而蝕刻硬遮罩。依照本發明之一個實施例，於圖案化閘電極之後，接著藉由於氧化環境中加熱多晶矽而熱生長氧化矽薄層70於閘電極66之相對側壁72上。層70能生長至大約2至5 nm之厚度。閘電極66和層70能使用為離子植入遮罩以形成MOS電晶體之源極和汲極延伸區(未顯示)。對於形成多個源極和汲極區域之可能需要條件和方法為已知，但與本發明並沒有密切關係，因此於此處無需說明。
依照本發明之一個實施例，如第3圖中所顯示，側壁間隔件80形成在閘電極66之相對側壁72上。此側壁間隔件能藉由沉積一層氮化矽、氧化矽、等等之間隔件材料於閘電極之上、並接著藉由例如反應性離子蝕刻來非等向性蝕刻該層而形成。側壁間隔件80、閘電極66、及於該閘電極之頂部上之硬遮罩用作為蝕刻遮罩來蝕刻於矽基板中由P通道閘電極66間隔開並自行對準於該P通道閘電極66之溝槽82和84。該等溝槽相交於通道68之端部。該等溝槽能藉由例如用Cl或HBr/O2 化學之電漿蝕刻來蝕刻。較佳的情況是，各溝槽具有深度為大約0.04至0.2 μ m。
如第4圖中所例示，用應力引發材料層90填充溝槽。該應力引發材料可以是能夠生長於具有與矽之晶格常數不同之晶格常數之矽基板上之任何的單晶材料。二種並置之材料之晶格常數差異產生在該二種材料之間介面處之應力，該應力再分配於主材料中。較佳的情況是，應力引發材料引起矽主體(silicon host)彈性地變形，使得矽受應力，但是維持著實質上無缺陷完美結晶。缺陷能引起應力之減少或減緩。應力引發材料能夠是例如具有大約10至25原子百分比之鍺之單晶矽鍺(SiGe)、或者是含有大約1至4原子百分比之代替的碳和較佳是少於大約2原子百分之代替的碳之單晶矽。較佳的情況是藉由選擇性生長製程而磊晶生長應力引發材料。以選擇性方式磊晶生長這些材料於矽主體上之方法為已知，而於此處無須說明。例如，於SiGe之情況，SiGe具有較矽之晶格常數為大之晶格常數，且此情況造成於電晶體通道68中之壓縮之縱向應力。壓縮之縱向應力增加通道68中電洞之移動率，而因此增進P通道MOS電晶體之效能。
於應力引發材料生長於溝槽82和84後，接著將P型導電率決定離子植入於應力引發材料中(如由箭號86所指示)以形成P通道MOS電晶體30之源極區域92和汲極區域94，如第5圖中所示。欲變成電性主動的(electrically active)，對植入之離子必須進行退火，而此種退火通常於完成植入後立刻執行。然而，升高的溫度引起於SiGe或其他的應力引發材料中固有的應力鬆弛，這是由於在表面上集結(nucleate)之錯位產生和於SiGe之表面處產生梯階(step)之關係。
依照本發明之實施例，如第6圖中所示，藉由沉積具有高機械強度之層96於應力引發材料之表面上而防止於通道68中應力的鬆弛。高機械強度之層延緩梯階形成(step formation)並防止錯位集結和傳播於應力引發材料之表面處。於離子植入之退火或任何其他高溫步驟之前，敷設高機械強度之層。敷設層96之後，裝置能經受高溫且將維持應力。層96可以是能夠沉積於相對低溫且具有楊氏係數(Young’s modulus)大於而較佳是遠大於應力引發材料之楊氏係數。舉例而言，用於具有楊氏係數大約為150 GPa之SiGe，氮化矽(楊氏係數大約350 GPa)、碳化矽(楊氏係數介於大約400與750 Gpa之間)和鑽石狀碳(楊氏係數高達800 GPa)為適用於層96之材料。如此處所使用者，低溫係指低於大約600℃之任何溫度，而高溫係指高於大約900℃之任何溫度。能藉由CVD、LPCVD、或PECVD而沉積層96。例如，能藉由PECVD於大約450℃溫度藉由二氯矽烷和氨之電漿增強反應而沉積氮化矽層。類似情況，能藉由使用氣相SiCl4 和甲烷於550℃而沉積碳化矽，以及能使用Ar、H2 、SiH4 和C2 H2 之混合氣體於200℃而沉積PECVD鑽石狀碳。依照本發明之替代實施例(未圖示)，首先在高機械強度之層96下方提供具有厚度例如2至5nm之墊氧化物層可能是有利的。該墊氧化物層用來防止例如在氮化矽和下方半導體材料之間的任何反應。
能夠藉由已知的步驟(未顯示)，譬如在層96之上沉積介電質材料層、蝕刻開口穿過該介電質材料和層96以暴露出源極和汲極區域之部分、以及形成延伸穿過開口以與該源極和汲極區域電性接觸之金屬化(metallization)，而完成受應力之MOS裝置30。進一步之層間介電質材料層、額外之互連金屬化層、等等亦可應用並圖案化以達成所執行積體電路之適當的電路功能。
雖然於本發明之上述詳細說明中已呈現了至少一個實施範例，但是應該了解到存在有許多之變化。亦應該了解到實施範例或諸實施範例僅是作實例用，並不意欲限制本發明之範圍、應用、或配置於任何方式。確切地說，以上之詳細說明將提供熟悉此項技術者施行該實施範例或諸實施範例之方便的路途指引。應了解到在功能和元件的配置可以作各種之改變而不脫離本發明提出於所附申請專利範圍中及其合法均等之範圍。
30．．．MOS裝置
36．．．半導體基板、矽基板
60．．．閘極絕緣體層
62．．．多晶矽層
64．．．硬遮罩層、硬遮罩材料層
66．．．閘電極
68．．．通道
70．．．氧化矽薄層
72．．．側壁
80．．．側壁間隔件
82、84．．．溝槽
86．．．箭號
90．．．應力引發材料層
92．．．源極區域
94．．．汲極區域
96．．．高機械強度之層
以上結合下列圖式而說明本發明，其中相似的元件符號表示相似的元件，以及其中：第1至6圖示意地顯示依照本發明之各種實施例之受應力之MOS裝置及其製造方法之剖面圖。
30．．．MOS裝置
36．．．半導體基板、矽基板
66．．．閘電極
68．．．通道
82、84．．．溝槽
90．．．應力引發材料層
92．．．源極區域
94．．．汲極區域
96．．．高機械強度之層

Claims (13)

  1. 一種於半導體基板中和上製造受應力之MOS裝置之方法，包括下列步驟：形成閘電極覆於該半導體基板上；於該半導體基板中蝕刻第一溝槽和第二溝槽，該第一溝槽和第二溝槽形成為對準於該閘電極；於該第一溝槽和該第二溝槽中選擇性地生長應力引發材料；離子植入導電率決定雜質離子於該應力引發材料中以於該第一溝槽中形成源極區域及於該第二溝槽中形成汲極區域；以及於該離子植入導電率決定雜質離子於該應力引發材料中以形成該源極區域和該汲極區域之步驟後以及在包含加熱至溫度大於大約600℃之任何步驟之前形成機械硬材料層覆於且接觸該應力引發材料之表面，以於後續加熱步驟期間防止錯位集結於該應力引發材料之該表面處。
  2. 如申請專利範圍第1項之方法，其中該選擇性地生長步驟包括磊晶生長單晶SiGe層之步驟。
  3. 如申請專利範圍第2項之方法，其中，形成機械硬材料層之該步驟包括沉積具有楊氏係數遠大於單晶SiGe之楊氏係數之材料層之步驟。
  4. 如申請專利範圍第3項之方法，其中，形成機械硬材料層之該步驟包括形成選自由氮化矽、碳化矽、和鑽 石狀碳所組成之群之材料之層之步驟。
  5. 如申請專利範圍第1項之方法，其中，選擇性地生長應力引發材料之該步驟包括選擇性地生長具有第一楊氏係數為特徵之應力引發材料之步驟，以及其中形成機械硬材料層之該步驟包括形成具有較該第一楊氏係數為大之第二楊氏係數為特徵之機械硬材料層之步驟。
  6. 如申請專利範圍第1項之方法，其中，形成機械硬材料層之該步驟包括形成選自由氮化矽、碳化矽、和鑽石狀碳所組成之群之材料之層之步驟。
  7. 一種製造受應力之MOS裝置之方法，包括下列步驟：提供單晶半導體基板；蝕刻溝槽進入該單晶半導體基板中；用晶格不匹配該單晶半導體基板之單晶半導體材料選擇性地填充該溝槽，該單晶半導體材料具有第一楊氏係數；以及沉積具有大於該第一楊氏係數之第二楊氏係數之材料膜而與形成源極區域和汲極區域之該單晶半導體材料接觸，沉積材料膜之該步驟發生於該單晶半導體材料被加熱至溫度大於大約600℃之前，以於後續加熱步驟期間防止錯位集結於該單晶半導體材料之表面處。
  8. 如申請專利範圍第7項之方法，其中，提供單晶基板之該步驟包括提供單晶矽基板，且選擇性地填充該溝槽之該步驟包括用選自由單晶SiGe和含有至少2%碳之單晶矽所組成之群之單晶材料來選擇性地填充該溝 槽之步驟。
  9. 如申請專利範圍第8項之方法，其中，沉積材料膜之該步驟包括沉積選自由氮化矽、碳化矽、和鑽石狀碳所組成之群之材料之層之步驟。
  10. 一種製造受應力之MOS裝置之方法，包括下列步驟：提供單晶半導體基板；藉由磊晶生長應力引發單晶半導體材料於該單晶半導體基板上而於該單晶半導體基板中產生應力狀況，該應力引發單晶半導體材料具有與該單晶半導體基板不匹配之晶格；以及在該應力引發單晶半導體材料受到溫度超過大約900℃之前，藉由沉積機械硬材料膜接觸且於形成源極區域和汲極區域之該應力引發單晶半導體材料之表面上而維持於該單晶半導體基板中之應力狀況，以於後續加熱步驟期間防止錯位集結於該應力引發單晶半導體材料之該表面處。
  11. 如申請專利範圍第10項之方法，其中，提供單晶半導體基板之該步驟包括提供單晶矽基板之步驟，以及其中產生應力狀況之該步驟包括於該單晶矽基板上選擇性地生長單晶SiGe之磊晶層之步驟。
  12. 如申請專利範圍第10項之方法，其中，維持該應力之該步驟包括沉積選自由氮化矽、碳化矽、和鑽石狀碳所組成之群之材料之層之步驟。
  13. 如申請專利範圍第10項之方法，復包括離子植入導電 率決定離子於該單晶SiGe中以形成該受應力之MOS裝置之該源極和汲極區域之步驟。
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Families Citing this family (35)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7253125B1 (en) 2004-04-16 2007-08-07 Novellus Systems, Inc. Method to improve mechanical strength of low-k dielectric film using modulated UV exposure
US9659769B1 (en) 2004-10-22 2017-05-23 Novellus Systems, Inc. Tensile dielectric films using UV curing
US7510982B1 (en) 2005-01-31 2009-03-31 Novellus Systems, Inc. Creation of porosity in low-k films by photo-disassociation of imbedded nanoparticles
US8282768B1 (en) 2005-04-26 2012-10-09 Novellus Systems, Inc. Purging of porogen from UV cure chamber
US8980769B1 (en) 2005-04-26 2015-03-17 Novellus Systems, Inc. Multi-station sequential curing of dielectric films
US8454750B1 (en) 2005-04-26 2013-06-04 Novellus Systems, Inc. Multi-station sequential curing of dielectric films
US8889233B1 (en) 2005-04-26 2014-11-18 Novellus Systems, Inc. Method for reducing stress in porous dielectric films
US8137465B1 (en) 2005-04-26 2012-03-20 Novellus Systems, Inc. Single-chamber sequential curing of semiconductor wafers
US20070096170A1 (en) * 2005-11-02 2007-05-03 International Business Machines Corporation Low modulus spacers for channel stress enhancement
US20070235763A1 (en) * 2006-03-29 2007-10-11 Doyle Brian S Substrate band gap engineered multi-gate pMOS devices
DE102006032195A1 (de) * 2006-07-12 2008-01-24 Robert Bosch Gmbh Verfahren zur Herstellung von MEMS-Strukturen
US7851232B2 (en) * 2006-10-30 2010-12-14 Novellus Systems, Inc. UV treatment for carbon-containing low-k dielectric repair in semiconductor processing
US8465991B2 (en) 2006-10-30 2013-06-18 Novellus Systems, Inc. Carbon containing low-k dielectric constant recovery using UV treatment
US10037905B2 (en) 2009-11-12 2018-07-31 Novellus Systems, Inc. UV and reducing treatment for K recovery and surface clean in semiconductor processing
US8242028B1 (en) 2007-04-03 2012-08-14 Novellus Systems, Inc. UV treatment of etch stop and hard mask films for selectivity and hermeticity enhancement
US8211510B1 (en) 2007-08-31 2012-07-03 Novellus Systems, Inc. Cascaded cure approach to fabricate highly tensile silicon nitride films
US9456925B2 (en) * 2007-09-06 2016-10-04 Alcon Lensx, Inc. Photodisruptive laser treatment of the crystalline lens
US7906817B1 (en) 2008-06-06 2011-03-15 Novellus Systems, Inc. High compressive stress carbon liners for MOS devices
US7998881B1 (en) 2008-06-06 2011-08-16 Novellus Systems, Inc. Method for making high stress boron-doped carbon films
US9050623B1 (en) 2008-09-12 2015-06-09 Novellus Systems, Inc. Progressive UV cure
US7629271B1 (en) * 2008-09-19 2009-12-08 Applied Materials, Inc. High stress diamond like carbon film
JP4952725B2 (ja) 2009-01-14 2012-06-13 ソニー株式会社 不揮発性磁気メモリ装置
US8288292B2 (en) 2010-03-30 2012-10-16 Novellus Systems, Inc. Depositing conformal boron nitride film by CVD without plasma
DE102010046215B4 (de) 2010-09-21 2019-01-03 Infineon Technologies Austria Ag Halbleiterkörper mit verspanntem Bereich, Elektronisches Bauelement und ein Verfahren zum Erzeugen des Halbleiterkörpers.
US8642407B2 (en) * 2010-11-04 2014-02-04 International Business Machines Corporation Devices having reduced susceptibility to soft-error effects and method for fabrication
BR112014005660A2 (pt) * 2011-09-15 2017-04-04 Amedica Corp implantes revestidos e métodos relacionados
CN103165464B (zh) * 2011-12-19 2016-02-17 中芯国际集成电路制造(上海)有限公司 采用e-SiGe的PMOS制造方法
US8815712B2 (en) * 2011-12-28 2014-08-26 Taiwan Semiconductor Manufacturing Company, Ltd. Method for epitaxial re-growth of semiconductor region
US20130175640A1 (en) * 2012-01-06 2013-07-11 Globalfoundries Inc. Stress enhanced mos transistor and methods for fabrication
CN103545211A (zh) * 2012-07-13 2014-01-29 中国科学院微电子研究所 半导体器件制造方法
US10396201B2 (en) 2013-09-26 2019-08-27 Intel Corporation Methods of forming dislocation enhanced strain in NMOS structures
US9530876B2 (en) 2013-12-20 2016-12-27 International Business Machines Corporation Strained semiconductor nanowire
KR102083632B1 (ko) * 2014-04-25 2020-03-03 삼성전자주식회사 반도체 장치 및 그 제조 방법
US9536945B1 (en) * 2015-07-30 2017-01-03 International Business Machines Corporation MOSFET with ultra low drain leakage
US9847221B1 (en) 2016-09-29 2017-12-19 Lam Research Corporation Low temperature formation of high quality silicon oxide films in semiconductor device manufacturing

Citations (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6048756A (en) * 1997-07-31 2000-04-11 Electronics And Telecommunications Research Institute Method for making a silicon-on-insulator MOS transistor using a selective SiGe epitaxy
US6165826A (en) * 1994-12-23 2000-12-26 Intel Corporation Transistor with low resistance tip and method of fabrication in a CMOS process
US6214679B1 (en) * 1999-12-30 2001-04-10 Intel Corporation Cobalt salicidation method on a silicon germanium film
US20030136985A1 (en) * 1999-12-30 2003-07-24 Murthy Anand S. Field effect transistor structure with partially isolated source/drain junctions and methods of making same
US20040014276A1 (en) * 2002-07-16 2004-01-22 Murthy Anand S. Method of making a semiconductor transistor
US6713802B1 (en) * 2003-06-20 2004-03-30 Infineon Technologies Ag Magnetic tunnel junction patterning using SiC or SiN
US20040173815A1 (en) * 2003-03-04 2004-09-09 Yee-Chia Yeo Strained-channel transistor structure with lattice-mismatched zone
US20040259315A1 (en) * 2003-06-09 2004-12-23 Canon Kabushiki Kaisha Semiconductor substrate, semiconductor device, and method of manufacturing the same
US20040262683A1 (en) * 2003-06-27 2004-12-30 Bohr Mark T. PMOS transistor strain optimization with raised junction regions
US20050035369A1 (en) * 2003-08-15 2005-02-17 Chun-Chieh Lin Structure and method of forming integrated circuits utilizing strained channel transistors
US20050035409A1 (en) * 2003-08-15 2005-02-17 Chih-Hsin Ko Structure and method of a strained channel transistor and a second semiconductor component in an integrated circuit
US20050059228A1 (en) * 2003-09-15 2005-03-17 Haowen Bu Integration of pre-S/D anneal selective nitride/oxide composite cap for improving transistor performance
JP2005084603A (ja) * 2003-09-11 2005-03-31 Konica Minolta Medical & Graphic Inc 熱現像画像記録材料

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3201475B2 (ja) * 1998-09-14 2001-08-20 松下電器産業株式会社 半導体装置およびその製造方法
JP4368095B2 (ja) * 2002-08-21 2009-11-18 富士通マイクロエレクトロニクス株式会社 半導体装置及びその製造方法
US7053400B2 (en) 2004-05-05 2006-05-30 Advanced Micro Devices, Inc. Semiconductor device based on Si-Ge with high stress liner for enhanced channel carrier mobility
US7060579B2 (en) * 2004-07-29 2006-06-13 Texas Instruments Incorporated Increased drive current by isotropic recess etch
US7190036B2 (en) * 2004-12-03 2007-03-13 Taiwan Semiconductor Manufacturing Company, Ltd. Transistor mobility improvement by adjusting stress in shallow trench isolation
US7323391B2 (en) * 2005-01-15 2008-01-29 Applied Materials, Inc. Substrate having silicon germanium material and stressed silicon nitride layer
JP2006269673A (ja) * 2005-03-23 2006-10-05 Nec Electronics Corp 半導体装置およびその製造方法
US7282415B2 (en) * 2005-03-29 2007-10-16 Freescale Semiconductor, Inc. Method for making a semiconductor device with strain enhancement
US7642205B2 (en) * 2005-04-08 2010-01-05 Mattson Technology, Inc. Rapid thermal processing using energy transfer layers
US7232730B2 (en) * 2005-04-29 2007-06-19 Taiwan Semiconductor Manufacturing Company, Ltd. Method of forming a locally strained transistor
US7569443B2 (en) * 2005-06-21 2009-08-04 Intel Corporation Complementary metal oxide semiconductor integrated circuit using raised source drain and replacement metal gate

Patent Citations (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6165826A (en) * 1994-12-23 2000-12-26 Intel Corporation Transistor with low resistance tip and method of fabrication in a CMOS process
US6048756A (en) * 1997-07-31 2000-04-11 Electronics And Telecommunications Research Institute Method for making a silicon-on-insulator MOS transistor using a selective SiGe epitaxy
US6214679B1 (en) * 1999-12-30 2001-04-10 Intel Corporation Cobalt salicidation method on a silicon germanium film
US20030136985A1 (en) * 1999-12-30 2003-07-24 Murthy Anand S. Field effect transistor structure with partially isolated source/drain junctions and methods of making same
US20040014276A1 (en) * 2002-07-16 2004-01-22 Murthy Anand S. Method of making a semiconductor transistor
US20040173815A1 (en) * 2003-03-04 2004-09-09 Yee-Chia Yeo Strained-channel transistor structure with lattice-mismatched zone
US20040259315A1 (en) * 2003-06-09 2004-12-23 Canon Kabushiki Kaisha Semiconductor substrate, semiconductor device, and method of manufacturing the same
US6713802B1 (en) * 2003-06-20 2004-03-30 Infineon Technologies Ag Magnetic tunnel junction patterning using SiC or SiN
US20040262683A1 (en) * 2003-06-27 2004-12-30 Bohr Mark T. PMOS transistor strain optimization with raised junction regions
US20050035369A1 (en) * 2003-08-15 2005-02-17 Chun-Chieh Lin Structure and method of forming integrated circuits utilizing strained channel transistors
US20050035409A1 (en) * 2003-08-15 2005-02-17 Chih-Hsin Ko Structure and method of a strained channel transistor and a second semiconductor component in an integrated circuit
JP2005084603A (ja) * 2003-09-11 2005-03-31 Konica Minolta Medical & Graphic Inc 熱現像画像記録材料
US20050059228A1 (en) * 2003-09-15 2005-03-17 Haowen Bu Integration of pre-S/D anneal selective nitride/oxide composite cap for improving transistor performance

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
Shyam Gannavaram et. al., "Low temperature Recessed Junction Selective Silicon Germanium Source/Drain Technology for sub-70nm CMOS", 2000年, IEDM, PP. 437-440 *

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