TWI440097B - 應力增強之ｍｏｓ電晶體及其製造方法 - Google Patents

應力增強之ｍｏｓ電晶體及其製造方法 Download PDF

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TWI440097B
TWI440097B TW096143643A TW96143643A TWI440097B TW I440097 B TWI440097 B TW I440097B TW 096143643 A TW096143643 A TW 096143643A TW 96143643 A TW96143643 A TW 96143643A TW I440097 B TWI440097 B TW I440097B
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sige
concentration
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germanium
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Rohit Pal
Igor Peidous
David Brown
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Advanced Micro Devices Inc
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Description

應力增強之MOS電晶體及其製造方法
本發明大體上係關於M0S電晶體及其製造方法，且尤係關於應力增強之M0S電晶體及此種具有鄰近電晶體通道之嵌入材料之電晶體之製造方法。
現代積體電路(IC)主要藉由使用複數個互連接場效電晶體(FET)(亦稱之為金屬氧化物半導體場效電晶體(MOSFET)，或簡稱為MOS電晶體)而實施。MOS電晶體包含作為控制電極之閘電極(gate electrode)，和間隔開之源電極和汲電極，而電流可在其間流動。施加至閘電極之控制電壓控制通過源電極和汲電極之間之通道之電流之流動。
IC之複雜性和結合入IC中之裝置之數目持續增加。當IC中裝置之數目增加時，個別裝置之尺寸減小。於IC中裝置之尺寸通常由最小特徵尺寸(feature size)所表示，其為最小線寬(line width)或由電路設計規則所允許之最小間隔。當半導體工業進展至最小特徵尺寸為45奈米(nm)和甚至更小時，個別裝置之效能由於尺寸縮小(scaling)而劣化。當設計用來施行這些積體電路之新世代之積體電路和電晶體時，技術人員必須大幅地依賴非習知的元件以提升裝置效能。
MOS電晶體之效能，如由其電流載送能力測量時，正比於電晶體通道中之主要載子移動率。已知施加縱向應力(longi tudinal stress)於MOS電晶體之通道能增加該移動率；壓縮的縱向應力增強主要載子電洞移動率，而拉伸的縱向應力增強主要載子電子移動率。已知例如藉由嵌入鄰近該電晶體通道之矽鍺(即嵌入矽鍺，eSiGe)而產生縱向壓縮應力以增強於P通道MOS(PMOS)電晶體中之電洞移動率。為了製造此種裝置，溝槽或凹部(recess)被蝕刻入矽基板中且於電晶體之源極和汲極區中，以及藉由使用SiGe之選擇性磊晶生長而填滿該溝槽。然而，僅僅增加eSiGe之鍺含量以增加應力不會完全成功，因為增加之鍺含量造成從嵌入區域之表面來的增加之SiGe損失、形成於嵌入區域上之金屬矽化物之聚集而減少對源極和汲極區之接觸電阻、以及當電晶體經受更多於製造IC過程中所遭遇之習知步驟時嵌入材料之增加之應力鬆弛。
因此，希望最佳化用來製造應力增強之MOS電晶體之方法。此外，希望提供最佳化之應力增強之MOS電晶體其避免習知電晶體製造所伴隨之問題。再者，由後續之詳細說明及所附之申請專利範圍，結合所附之圖式和前述技術領域和先前技術，則本發明之其他所希望之特徵和特性將變得清楚。
本發明提供一種具有增強之主要載子移動率(mobility)之應力增強之MOS電晶體。該應力增強之MOS電晶體包括具有表面之半導體基板和位於該表面之通道區。具有第一鍺濃度之第一區域之SiGe係嵌入於半導體基板中。第一區域具有底部和鄰近該通道區之側部。具有少於該第一鍺濃度之第二鍺濃度之第二區域之SiGe係嵌入於該第一區域中，使得該側部具有較該底部為大之厚度。
本發明提供一種用來製造應力增強之M0S電晶體之方法。依照本發明之一個實施例，該方法包括形成閘電極(gate electrode)，該閘電極覆蓋和界定於單晶半導體基板中之通道區。具有面對該通道區之側表面之溝槽被蝕刻入該單晶半導體基板中且鄰近該通道區。溝槽被填滿具有第一濃度之取代原子(substitutional atom)之第二單晶半導體材料和具有第二濃度之取代原子之第三單晶半導體材料。第二單晶半導體材料磊晶生長成具有延著該側表面之壁厚度足以施加較將由具有第二濃度之單晶半導體材料所施加應力(若該溝槽僅被填滿第三單晶半導體材料時)為大之應力於通道區。
下列之詳細說明本質上僅為範例，並不意欲用來限制本發明或本發明之應用和使用。再者，本發明並不意欲受前面之技術領域、先前技術、發明內容、或下列之實施方式中所提出之任何表示或暗示理論所限制。
單晶矽(monocrystalline silicon)為使用於半導體工業用來製造半導體裝置和積體電路最常見的半導體材料，其特徵在於晶格常數，即矽晶體(crystal)之尺寸。藉由取代非矽之原子於晶格中，能夠改變所得到的晶體尺寸和晶格常數。若較大的取代原子(譬如鍺原子)加入至矽晶格中，則晶格常數增加且晶格常數之增加係正比於取代原子之濃度。相似情況，若較小的取代原子(譬如碳原子)加入至矽晶格中，則晶格常數減小。局部地加入大的取代原子至主(host)矽晶格中則於主晶格產生壓縮應力(compressive stress)，而加入小的取代原子至主矽晶格中則於主晶格產生拉伸應力(tensile stress)。
已知增加嵌入SiGe之鍺含量則增加應力，該應力能夠被施加於PMOS電晶體之通道，並由此增加電晶體中之主要載子電洞之移動率。亦已知於嵌入SiGe材料之表面具有低濃度之鍺避免某些由於在該表面具有高的鍺濃度所招致之問題。已嘗試藉由下列製程達成於eSiGe主體(bulk)中有高的鍺濃度和鍺之低表面濃度。溝槽被蝕刻入電晶體之於通道二端之源極和汲極區中。然後藉由矽鍺之選擇性磊晶生長(epitaxial growth)製程填滿該等通道。於反應物流(reactant flow)中鍺之最初濃度為高而引致高鍺濃度SiGe之沉積。於經過磊晶生長週期之中途於反應物流中鍺之濃度減少，而維持著減少濃度之流(flow)直到填滿溝槽為止。結果為高鍺濃度SiGe下層和低鍺濃度SiGe層於該表面。雖然由此種製程產生之裝置避免了會由高的鍺濃度於SiGe之表面所遭受之問題，但是移動率增加不大於會以填滿溝槽之均勻地低鍺濃度嵌入SiGe所期望者。
於磊晶生長製程中，生長之材料層實質地呈現其正生長於其上之表面之形象。觀察到不幸地，高鍺濃度SiGe之選擇性磊晶生長優先從溝槽之底部生長，而因此於溝槽之側壁上SiGe膜之生長率(growth rate)為低，造成於側壁上僅有高鍺濃度SiGe之薄層。也就是說，磊晶生長優先集結於被發現在溝槽之底部的結晶結構上而非在側壁結晶結構上。覆蓋面向電晶體通道之側壁之SiGe膜之厚度在施加應力於通道時為最重要，以及由習知製程所實現之厚度不足以達成所希望之通道應力和所希望之移動率增加。提供依照本發明之各種實施例，提供M0S電晶體和製造此種裝置之方法，其於鄰近通道之區域中達成高鍺濃度SiGe之足夠的厚度以最佳化通道應力和移動率增加。
第1至6圖顯示依照本發明之各種實施例之受應力(stressed)M0S裝置30及用於製造此種M0S裝置之方法步驟之剖面圖。於此例示實施例中，受應力M0S裝置30藉由單一P通道MOS(PMOS)電晶體所例示。從譬如裝置30之受應力M0S裝置所形成之積體電路能夠包含大量之此種電晶體，以及亦可包含未受應力之PMOS電晶體及受應力和未受應力之N通道MOS(NMOS)電晶體。
於M0S電晶體之製造之各種步驟為已知，而為了簡潔之目的，許多習知之步驟於此處將僅簡單提及，或將其整個省略而不提供已知之製程細節。雖然詞彙“M0S裝置”適當地指具有金屬閘電極和氧化物閘極絕緣體之裝置，但是該詞彙將用於整篇文章中以指任何包含導電閘電極(不論金屬或其他導電材料)的半導體裝置，該導電閘電極位於閘極絕緣體(不論氧化物或其他絕緣體)之上，而該閘極絕緣體依次位於半導體基板之上。
如第1圖中所例示，依照本發明之實施例之受應力M0S電晶體30之製造開始於提供半導體基板36，而此種電晶體被製造於該半導體基板36中或上。於製造M0S電晶體30之初始步驟為習知，因此不說明其細節。半導體基板較佳為具有(100)表面結晶方向(surface crystal orientation)之矽基板，其中此處所用之詞彙“矽基板”和“矽層”包含典型用於半導體工業之相當純的單晶矽材料以及與其他元素(譬如鍺、碳等)混合之矽。下文中為了方便半導體基板36將稱為(但不限定為)矽基板，雖然熟悉半導體技術者將了解到能夠使用其他的半導體材料。矽基板36可以是主體矽晶圓(未顯示)，但是較佳為在絕緣層40上之薄的單晶矽層38(一般已知為絕緣層上覆矽(silicon－on－insulator)或SOI)，該絕緣層40依次由載體晶圓42所支撐。薄矽層38典型具有小於大約200奈米(nm)之厚度(取決於被執行之電路功能而定)，以及於某些應用中較佳具有小於大約90奈米之厚度。薄矽層較佳具有至少大約5至40歐姆公分之電阻率。矽可以被N型或P型雜質摻雜，但是較佳為P型摻雜。典型為二氧化矽之介電絕緣層40較佳具有大約50至200奈米之厚度。
形成隔離區48，其延伸通過單晶矽層38至介電絕緣層40。隔離區較佳由眾所周知的淺溝槽隔離(shallow trench isolation，STI)技術形成，其中溝槽被蝕刻入單晶矽層38中，溝槽被填滿譬如沉積之二氧化矽之介電材料，以及藉由化學機械平面化法(chemical mechanical planarization，CMP)去除過多之二氧化矽。當需要時，STI區域48提供各種電路裝置之間之電性隔離，該等電路裝置將被形成於單晶矽層38中。於製造STI區域之前或較佳地於製造STI區域之後，能夠藉由例如離子植入而雜質摻雜矽層38之選定部分。例如，N型井52能夠被N型雜質摻雜以用於PMOS電晶體30之製造。
閘極絕緣體54之層形成於矽層38之表面56上，如第2圖中所示。閘極絕緣體可為於氧化環境中藉由加熱矽基板而形成之熱生長的二氧化矽，或者可以是譬如氧化矽、氮化矽、譬如Hfx Siy Oz 之高介電常數絕緣體、等等之沉積之絕緣體。沉積之絕緣體能夠以已知之方法沉積，例如藉由化學氣相沉積(CVD)、低壓化學氣相沉積(LPCVD)、半大氣壓化學氣相沉積(semi－atmospheric chemical vapor deposition，SACVD)、或電漿輔助化學氣相沉積(plasma enhanced chemical vapor deposition，PECVD)。此處顯示之閘極絕緣體54為熱生長之二氧化矽層，其僅生長在矽層38之表面56上。閘極絕緣體材料典型為1至10奈米厚，而較佳具有1至2奈米之厚度。依照本發明之一個實施例，閘電極形成材料58之層，較佳是多晶矽層，係沉積於閘極絕緣體之層上。亦可沉積譬如金屬和金屬矽化物之其他導電閘電極形成材料(以材料本身或具有適當的雜質摻雜能設定電晶體之所需臨限電壓為條件)。下文中閘電極形成材料將稱為多晶矽，雖然熟悉此項技術者將了解到亦可使用其他的材料。若閘電極材料為多晶矽，則藉由矽烷(silane)之氫還原作用使用LPCVD將該材料典型沉積至大約50至200奈米之厚度，而較佳至大約100奈米之厚度。多晶矽層較佳沉積為非摻雜多晶矽，並後續藉由離子植入而被雜質摻雜。譬如氮化矽層之硬遮罩材料60之層沉積在多晶矽閘電極形成材料之上。該遮罩材料之層(若為氮化矽)能藉由例如PECVD而由二氯矽烷(dichlorosilane)和氨(ammonia)之反應而沉積至大約30至50奈米之厚度。熟悉此項技術者將了解到除了氮化矽之其它介電材料能沉積作為硬遮罩材料。
如第3圖中所示，閘電極形成材料58和硬遮罩材料以光學微影方式被圖案化(pattern)並蝕刻以形成由硬遮罩材料所覆蓋之閘電極62。能藉由例如於Cl和HBr/O2 化學品(chemistry)中之電漿蝕刻而蝕刻多晶矽於所希望之圖案，以及能藉由例如於CHF3 、CF4 、或SF6 化學品中之電漿蝕刻而蝕刻硬遮罩。在圖案化閘電極之後，依照本發明之一個實施例，氧化矽薄層64被熱生長於閘電極62之相對側壁65和66上。薄氧化物能夠具有例如大約2至3奈米之厚度。閘電極62之形成界定通道區68為在閘電極下方之薄矽層38之表面的部分。較佳情況是通道沿著【110】晶向(crystal direction)被定向，而使得電晶體中之電流流動將朝向【110】晶向。薄氧化物層64提供襯裏(liner)以分隔多晶矽閘電極與隨後沉積之間隔件形成材料。
依照本發明之一個實施例之方法繼續，全面性沉積(blanket deposit)氮化矽或其他間隔件形成材料(未圖示)之層和各向異性(anisotropically)蝕刻該層以形成覆蓋相對側壁65和66上之二氧化矽薄層64的間隔件70(如第4圖中所示)。氮化矽層沉積至大約80至250奈米之厚度，較佳藉由使用二氯矽烷和氨作為反應物的LPCVD。側壁間隔件能夠例如藉由使用CF4 或CHF3 化學品之反應性離子蝕刻(reactive ion etching，RIE)而被各向異性蝕刻。使用間隔件70、閘電極62、和STI 48作為遮罩而蝕刻凹部72和74入薄矽層38中。因為側壁間隔件作為蝕刻遮罩，因此凹部自行對準於閘電極62之側壁65和66及通道68，並且與閘電極隔開實質相等於側壁間隔件之厚度之距離(如箭號69所表示)。例如藉由使用HBr/O2 化學物之反應性離子蝕刻(RIE)作各向異性蝕刻凹部72和74至大約400至600奈米之深度(如箭號75所表示)。至少矽層38之薄部分留在溝槽之底表面76下方。
溝槽72和74具有側表面78和80，分別地面對通道68。底表面76實質地平行於薄矽層38的表面，並且具有和薄矽層38的表面56相同的結晶方向。底表面76因此位於沿著(100)晶面(crystal plane)。由於通道68定向於【110】晶向和側表面78和80實質垂直於表面56，該等側表面位於沿著(011)晶面。依照本發明之實施例，藉由選擇性磊晶生長製程將溝槽72和74填滿嵌入之SiGe 82，該選擇性磊晶生長製程提供(011)晶面之生長率高於(100)晶面之生長率。該選擇性磊晶生長集結於側表面上及於底表面上，但是能夠以已知之方式藉由於磊晶生長期間調整生長狀況(譬如反應物流、生長溫度、生長壓力、等等，例如於由Rai－Choudhury,P.、Schroder,D.K發表於電化學協會期刊(Journal of the Electrochemical Society )1973年5月，第120冊，第5號，第664至668頁之“SELECTIVE SILICON EPITAXY AND ORIENTATION DEPENDENCE OF GROWTH)”中討論者而於(011)晶面上達成較高生長率。嵌入之SiGe 82之磊晶生長繼續，以部分填滿溝槽72和74(如第5圖中所示)。嵌入之SiGe 82生長成具有高濃度之鍺，較佳大約25至40原子百分比鍺之間。以此種方式生長之嵌入之SiGe 82於側表面78和80上生長高鍺濃度SiGe之層84較生長於底表面76上之層86為厚。較佳的情況是於側表面78和80上之高鍺含量SiGe具有至少10至30奈米之厚度。
改變選擇性磊晶生長狀況以減少鍺含量，以及溝槽72和74之其餘部分被填滿低濃度嵌入之SiGe 88(如第6圖中所示)。較佳的情況是嵌入之SiGe 88具有大約0至20原子百分比鍺之鍺濃度。溝槽72和74因此被填滿嵌入之SiGe，該嵌入之SiGe具有沿著面對通道68之側表面之高鍺濃度之厚壁和低鍺濃度之表面。
依照本發明之進一步實施例，例示於第5和6圖中之結構藉由於具有垂直(亦即，實質垂直於表面56)電位偏壓的電漿環境中磊晶生長高鍺濃度嵌入之SiGe而達成。朝垂直方向之磊晶生長率(其為於底表面76上之生長率)將藉由電漿蝕刻成分而降低。於側表面上生長高鍺濃度SiGe之所希望之厚度後，能夠改變磊晶生長狀況以降低溝槽再填滿之低鍺濃度部分之鍺濃度。低鍺含量部分之生長能夠用電漿環境或不用電漿環境完成。
依照本發明之進一步實施例，達成所希望之低濃度鍺SiGe之表面和沿著面對電晶體通道之溝槽之側表面之高鍺濃度SiGe之充分厚壁以施加較由低鍺濃度SiGe單獨施加於通道之應力為大之應力之最後結果(如第7至9圖結合第1至4圖中所示)。依照本發明之此實施例之方法開始與第1至4圖中所示相同步驟。如第7圖中所示，溝槽72和74藉由高鍺濃度SiGe層90(較佳大約25至40原子百分比鍺)之選擇性磊晶生長而被再填滿。
方法繼續，全面性沉積氮化矽或其他間隔件形成材料(未圖示)之層，以覆蓋閘電極62、側壁間隔件70、和嵌入之SiGe 90。間隔件材料之層能夠藉由例如LPCVD而沉積至至少10至30奈米之厚度。間隔件材料之層被例如用RIE非等向性蝕刻，以形成覆蓋側壁間隔件70的側壁間隔件92。於替代實施例(未圖示)中，於沉積該間隔件材料之層前，能去除側壁間隔件70，該間隔件材料能沉積至大約30至40奈米之厚度，以及能夠形成具有30至40奈米厚度之單一側壁間隔件。不管是使用二個側壁間隔件或一個較厚側壁間隔件，該側壁間隔件、閘電極、和STI被用作為蝕刻遮罩以及溝槽94和96被蝕刻入嵌入之SiGe90中(如第8圖所示)。溝槽94和96能藉由反應性離子蝕刻而被蝕刻至大約15至25奈米之深度(如箭號95所表示)。溝槽94和96自行對準於通道68，並且與該通道隔開有間隔件之寬度(如箭號97所表示)。
如第9圖中所例示，溝槽94和96被再填滿選擇性生長之低鍺濃度磊晶SiGe 100，較佳具有大約0至20原子百分比之鍺濃度。相似於前面的實施例，電晶體具有低鍺濃度SiGe表面98和面對通道68之高鍺濃度SiGe之厚壁。高鍺濃度SiGe具有足夠的厚度以施加較單獨由低鍺濃度SiGe所施加之應力更多的應力於電晶體之通道。
雖然未例示，但是第6和9圖中所示之結構能用習知之方法完成。習知之步驟包括，例如，去除側壁間隔件70、92並用單一永久側壁間隔件替代他們。永久側壁間隔件用作為離子植入遮罩，並且導電率決定離子(conductivity determining ion)被植入於閘電極之任一側上之矽或SiGe中以形成源極和汲極區域。對於PMOS電晶體，導電率離子能夠是硼離子。熟悉此項技術者將了解到可使用多於一組之側壁間隔件，以及可實施多於一次之離子植入以產生源極和汲極延伸區、產生暈圈植入物(halo implant)、設定臨限電壓、等等。側壁間隔件亦能用來形成對源極和汲極區域之自行對準之金屬矽化物接點(contact)。沉積並加熱矽化物形成金屬之層以引致金屬與暴露之矽或SiGe反應以形成金屬矽化物。不與暴露之矽接觸之金屬(譬如沉積於側壁間隔件或STI上之金屬)不反應並能藉由在H2 O2 /H2 SO4 或HNO3 /HCL溶液中蝕刻而去除。於形成受應力MOS電晶體中，譬如受應力氮化矽之應力襯裏層可沉積在閘電極和金屬矽化物接點之上。於沉積應力襯裏之後接著沉積介電層、平面化介電層、以及蝕刻接觸開口穿過介電層至金屬矽化物接點。然後能藉由形成在接觸開口中之接觸插塞(plug)和藉由互連接金屬沉積和圖案化而製成對源極和汲極區域之電接點。
上述實施例已說明用於製造應力增強之PM0S電晶體之方法。相似之方法可用來製造應力增強之NM0S電晶體，並且任一結構或二者結構之製造可整合成用於製造包含受應力的和非受應力的PM0S和NMOS電晶體二者之CMOS積體電路之方法。製造應力增強之NM0S電晶體相似於上述之方法，除了薄矽層被P型雜質摻雜、源極和汲極區域用N型導電率決定離子雜質摻雜、和磊晶生長於源極和汲極區域中之嵌入之材料應具有譬如碳之取代原子而使得生長材料之晶格常數小於主材料之晶格常數以在電晶體通道上產生縱向拉張應力(tensional stress)。
雖然於本發明之上述詳細說明中已提出至少一個範例實施例，但是應該了解到存在有許多之變化。亦應該了解到該範例實施例或諸範例實施例只是例子，而不意欲限制本發明之範圍、應用、或組構於任何方式。而是，以上之詳細說明將提供熟悉此項技術者施行本發明之該範例實施例或諸範例實施例之方便的路途指引。應了解到在元件之功能和配置可以作各種之改變而不脫離所附之申請專利範圍與其合法之均等者提出之本發明之範圍。
30．．．受應力M0S裝置(PMOS電晶體)
36．．．半導體基板
38．．．單晶矽層
40．．．介電絕緣層
42．．．晶圓
48．．．隔離區(STI)
52．．．N型井
54．．．閘極絕緣體
56．．．表面
58．．．閘電極形成材料
60．．．硬遮罩材料
62．．．閘電極
64．．．氧化矽薄層
65、66．．．相對側
68．．．通道
69、75．．．箭號
70．．．側壁間隔件
72、74．．．凹部(溝槽)
76．．．底表面
78、80．．．側表面
82．．．SiGe
84．．．厚層
86．．．層
88．．．嵌入之SiGe
90．．．高鍺濃度SiGe層、嵌入之SiGe
92．．．側壁間隔件
94、96．．．溝槽
95、97．．．箭號
98．．．表面
上文中結合下列之圖式而說明本發明，其中相似之元件符號表示相似之元件，且其中：第1至6圖顯示依照本發明之各種實施例之受應力M0S電晶體及其製造方法步驟之剖面圖；以及第7至9圖，結合第1至4圖，顯示依照本發明之替代實施例之受應力M0S電晶體及其製造方法步驟之剖面圖。
30．．．受應力M0S裝置(PMOS電晶體)
38．．．單晶矽層
40．．．介電絕緣層
42．．．晶圓
48．．．隔離區(STI)
54．．．閘極絕緣體
56．．．表面
60．．．硬遮罩材料
62．．．閘電極
65、66．．．相對側
68．．．通道
70．．．側壁間隔件
72、74．．．凹部(溝槽)
76．．．底表面
78、80．．．側表面
82．．．SiGe
84．．．厚層
86．．．層
88．．．嵌入之SiGe

Claims (20)

  1. 一種用於製造應力增強之MOS裝置之方法，該MOS裝置具有位於半導體基板之表面的通道區，該方法包括下列步驟：蝕刻溝槽入該半導體基板中且鄰近該通道區，各該溝槽具有面對該通道區的側表面、和底表面；磊晶生長具有第一濃度之鍺之第一層之SiGe於該等溝槽中，以部分填滿該等溝槽，該第一層之SiGe於該側表面上具有第一生長率，而於該底表面上具有小於該第一生長率之第二生長率；以及磊晶生長具有小於該第一濃度之第二濃度之鍺之第二層之SiGe以填滿該等溝槽。
  2. 如申請專利範圍第1項之方法，其中，該半導體基板為包括具有(100)結晶表面方向之矽之基板，該通道區係沿著【110】晶向被定向，該側表面具有(011)結晶表面方向，以及其中，該磊晶生長第一層之步驟包括調整磊晶生長狀況之步驟以相較於(100)結晶表面上之磊晶生長率而增強於(011)結晶表面上之磊晶生長率。
  3. 如申請專利範圍第1項之方法，其中，該磊晶生長第一層之步驟包括於具有實質垂直於該半導體基板之電位偏壓的電漿環境中磊晶生長第一層之步驟。
  4. 如申請專利範圍第1項之方法，其中，該磊晶生長第一層之步驟包括磊晶生長包括25至40原子百分比鍺之SiGe之層之步驟。
  5. 申請專利範圍第4項之方法，其中，該磊晶生長第二層之步驟包括磊晶生長包括0至20原子百分比鍺之SiGe之層之步驟。
  6. 如申請專利範圍第1項之方法，復包括下列步驟：形成閘極絕緣體覆蓋該通道區；形成閘電極覆蓋該閘極絕緣體；形成側壁間隔件於該閘電極上；以及其中，該蝕刻溝槽之步驟包括蝕刻溝槽對準於該等側壁間隔件之步驟。
  7. 一種用於製造應力增強之MOS電晶體之方法，包括下列步驟：形成閘極絕緣體覆蓋半導體基板；形成閘電極覆蓋該閘極絕緣體，該閘電極具有第一邊緣和第二邊緣；蝕刻第一溝槽和第二溝槽入該半導體基板中，該第一溝槽對準於該第一邊緣並與該第一邊緣隔開第一距離，而該第二溝槽對準於該第二邊緣並與該第二邊緣隔開該第一距離；磊晶生長具有第一濃度之鍺之第一層之SiGe於該第一溝槽和該第二溝槽中；該第一層具有厚度足以填滿該第一溝槽和該第二溝槽；蝕刻第三溝槽和第四溝槽入該第一層中，該第三溝槽對準於該第一側並與該第一側隔開第二距離，該第二距離大於該第一距離，而該第四溝槽對準於該第二側並 與該第二側隔開該第二距離；以及磊晶生長具有第二濃度之鍺之第二層之SiGe於該第三溝槽和該第四溝槽中，該第二濃度小於該第一濃度，且該第二層之SiGe具有第二厚度足以填滿該第三溝槽和該第四溝槽。
  8. 如申請專利範圍第7項之方法，復包括下列步驟：形成第一側壁間隔件於該第一邊緣和該第二邊緣上，該等第一側壁間隔件具有第一厚度；以及其中，該蝕刻第一溝槽和第二溝槽之步驟包括使用該等第一側壁間隔件作為蝕刻遮罩來蝕刻第一溝槽和第二溝槽之步驟。
  9. 如申請專利範圍第8項之方法，復包括下列步驟：形成第二側壁間隔件覆蓋該等第一側壁間隔件；以及其中，該蝕刻第三溝槽和第四溝槽之步驟包括使用該等第二側壁間隔件作為蝕刻遮罩來蝕刻該第三溝槽和該第四溝槽之步驟。
  10. 如申請專利範圍第8項之方法，復包括下列步驟：於該蝕刻該第一溝槽和該第二溝槽之步驟後去除該等第一側壁間隔件；形成第二側壁間隔件於該第一邊緣和該第二邊緣上，該等第二側壁間隔件具有大於該第一厚度之第二厚度；以及其中，該蝕刻第三溝槽和第四溝槽之步驟包括使用 該等第二側壁間隔件作為蝕刻遮罩來蝕刻該第三溝槽和該第四溝槽之步驟。
  11. 如申請專利範圍第7項之方法，其中，該磊晶生長第一層之步驟包括磊晶生長包括25至40原子百分比鍺之SiGe之層之步驟，以及其中，該磊晶生長第二層之步驟包括磊晶生長包括小於20原子百分比鍺之第二層之SiGe之步驟。
  12. 一種用於在具有第一晶格常數之單晶半導體基板中和上製造應力增強之MOS電晶體之方法，該方法包括下列步驟：形成閘電極，該閘電極覆蓋並界定於該單晶半導體基板中之通道區；蝕刻溝槽入該單晶半導體基板中且鄰近該通道區，該溝槽具有面對該通道區之側表面、和底表面；用具有第一濃度之取代原子之第二單晶半導體材料和具有第二濃度之該取代原子之第三單晶半導體材料填滿該溝槽，該第二單晶半導體材料具有沿著該側表面之壁厚度足以施加較具有該第二濃度之單晶半導體材料所施加應力為大之應力於該通道區。
  13. 如申請專利範圍第12項之方法，其中，該填滿該溝槽之步驟包括用具有不同於該第一晶格常數之第二晶格常數之單晶材料填滿該溝槽之步驟。
  14. 如申請專利範圍第12項之方法，其中，該單晶半導體基板包括單晶矽基板，以及其中，該填滿該溝槽之步驟 包括用具有第一濃度之鍺之單晶SiGe之後用具有小於該第一濃度之第二濃度之鍺之SiGe填滿該溝槽之步驟。
  15. 如申請專利範圍第12項之方法，其中，該填滿該溝槽之步驟包括用包括具有鍺含量為25至40原子百分比之SiGe之第二單晶半導體材料和用包括具有鍺含量小於20原子百分比之SiGe之第三單晶半導體材料來填滿該溝槽之步驟。
  16. 如申請專利範圍第12項之方法，其中，該填滿該溝槽之步驟包括用包括具有沿著該側表面有至少10nm之壁厚度之SiGe之第二單晶半導體材料來填滿該溝槽。
  17. 如申請專利範圍第12項之方法，其中，該填滿該溝槽之步驟包括下列步驟：磊晶生長具有第一濃度之鍺之第一SiGe來填滿該溝槽；蝕刻第二溝槽入該第一SiGe中，該第二溝槽與該通道區隔開有該壁厚度；以及磊晶生長具有小於該第一濃度之第二濃度之鍺之第二SiGe來填滿該第二溝槽。
  18. 如申請專利範圍第17項之方法，其中，該填滿該溝槽之步驟包括磊晶生長具有25至40原子百分比之鍺濃度之SiGe之步驟，以及該填滿該第二溝槽之步驟包括磊晶生長具有小於20原子百分比之鍺濃度之SiGe之步驟。
  19. 如申請專利範圍第12項之方法，其中，該填滿該溝槽之步驟包括下列步驟：用相較於該底表面具有沿著該側表面之加速的生長率的磊晶生長製程來起始該第二單晶半導體材料之生長；降低該取代原子之濃度；以及磊晶生長該第三單晶半導體材料以完成該溝槽之填滿。
  20. 一種應力增強之MOS電晶體，包括：具有表面之半導體基板；位於該半導體基板之該表面之通道區域；具有第一鍺濃度之第一區域之SiGe，嵌入於該半導體基板中且具有底部和鄰近該通道區之側部，其中，該側部具有大於該底部之厚度；具有小於該第一鍺濃度之第二鍺濃度之第二區域之SiGe，嵌入於該第一區域中。
TW096143643A 2006-11-21 2007-11-19 應力增強之ｍｏｓ電晶體及其製造方法 TWI440097B (zh)

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CN101578690B (zh) 2011-10-12
JP2010510684A (ja) 2010-04-02
CN101578690A (zh) 2009-11-11
WO2008063543A3 (en) 2008-07-17
KR101386711B1 (ko) 2014-04-18
WO2008063543A2 (en) 2008-05-29
EP2095408A2 (en) 2009-09-02
US7534689B2 (en) 2009-05-19
KR20090091788A (ko) 2009-08-28
TW200832566A (en) 2008-08-01
DE602007008611D1 (de) 2010-09-30
ATE478434T1 (de) 2010-09-15
US20080119031A1 (en) 2008-05-22
EP2095408B1 (en) 2010-08-18
JP5283233B2 (ja) 2013-09-04

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