CN101578690A - 应力增强的mos晶体管及其制造方法 - Google Patents

应力增强的mos晶体管及其制造方法 Download PDF

Info

Publication number
CN101578690A
CN101578690A CNA2007800427664A CN200780042766A CN101578690A CN 101578690 A CN101578690 A CN 101578690A CN A2007800427664 A CNA2007800427664 A CN A2007800427664A CN 200780042766 A CN200780042766 A CN 200780042766A CN 101578690 A CN101578690 A CN 101578690A
Authority
CN
China
Prior art keywords
sige
groove
epitaxial growth
concentration
stress
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CNA2007800427664A
Other languages
English (en)
Other versions
CN101578690B (zh
Inventor
R·帕尔
I·佩多斯
D·布朗
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Innovation Core Making Co ltd
Original Assignee
Advanced Micro Devices Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Micro Devices Inc filed Critical Advanced Micro Devices Inc
Publication of CN101578690A publication Critical patent/CN101578690A/zh
Application granted granted Critical
Publication of CN101578690B publication Critical patent/CN101578690B/zh
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
    • H01L29/7848—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate the means being located in the source/drain region, e.g. SiGe source and drain
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/04—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/04—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes
    • H01L29/045—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes by their particular orientation of crystalline planes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66636—Lateral single gate silicon transistors with source or drain recessed by etching or first recessed by etching and then refilled
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02524—Group 14 semiconducting materials
    • H01L21/02532—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/02636—Selective deposition, e.g. simultaneous growth of mono- and non-monocrystalline semiconductor materials
    • H01L21/02639—Preparation of substrate for selective deposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823807—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823814—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
    • H01L29/161—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table including two or more of the elements provided for in group H01L29/16, e.g. alloys
    • H01L29/165—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table including two or more of the elements provided for in group H01L29/16, e.g. alloys in different semiconductor regions, e.g. heterojunctions

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Manufacturing & Machinery (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Recrystallisation Techniques (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Element Separation (AREA)
  • Thin Film Transistor (AREA)

Abstract

本发明提供一种应力增强的MOS晶体管(30)及其制造方法。于一个实施例中，该方法包括形成栅极电极(62)，该栅极电极覆盖和界定于单晶半导体衬底(38)中的沟道区(68)。具有面对该沟道区之侧表面(78、80)之沟槽(72、74)被蚀刻入该单晶半导体衬底中且邻近该沟道区。沟槽被填满具有第一浓度的取代原子的第二单晶半导体材料(82、90)和具有第二浓度的取代原子之第三单晶半导体材料(88、100)。第二单晶半导体材料(82、90)外延生长成具有延着该侧表面之壁厚度足以施加较将由具有第二浓度的单晶半导体材料所施加应力(假如该沟槽仅被填满第三单晶半导体材料时)为大之应力于沟道区(68)。

Description

应力增强的MOS晶体管及其制造方法
技术领域
本发明大体上系关于MOS晶体管及其制造方法，且尤系关于应力增强的MOS晶体管及此种具有邻近晶体管沟道之嵌入材料之晶体管之制造方法。
背景技术
现代集成电路(IC)主要藉由使用复数个互连接场效晶体管(FET)(亦称之为金属氧化物半导体场效晶体管(MOSFET)，或简称为MOS晶体管)而实施。MOS晶体管包含作为控制电极之栅极电极(gateelectrode)，和间隔开之源电极和汲电极，而电流可在其间流动。施加至栅极电极之控制电压控制通过源电极和汲电极之间的沟道之电流之流动。
IC之复杂性和结合入IC中之器件之数目持续增加。当IC中器件之数目增加时，个别器件之尺寸减小。于IC中器件之尺寸通常由最小特征尺寸(feature size)所表示，其为最小线宽(line width)或由电路设计规则所允许之最小间隔。当半导体工业进展至最小特征尺寸为45奈米(nm)和甚至更小时，个别器件之效能由于尺寸缩小(scaling)而劣化。当设计用来施行这些集成电路之新世代之集成电路和晶体管时，技术人员必须大幅地依赖非习知的组件以提升器件效能。
MOS晶体管之效能，如由其电流载送能力测量时，正比于晶体管沟道中之主要载子移动率。已知施加纵向应力(longitudinal stress)于MOS晶体管的沟道能增加该移动率；压缩的纵向应力增强主要载子电洞移动率，而拉伸的纵向应力增强主要载子电子移动率。已知例如藉由嵌入邻近该晶体管沟道的硅锗(即嵌入硅锗，eSiGe)而产生纵向压缩应力以增强于P沟道MOS(PMOS)晶体管中之电洞移动率。为了制造此种器件，沟槽或凹部(recess)被蚀刻入硅衬底中且于晶体管之源极和汲极区中，以及藉由使用SiGe之选择性外延生长而填满该沟槽。然而，仅仅增加eSiGe的锗含量以增加应力不会完全成功，因为增加的锗含量造成从嵌入区域的表面来的增加的SiGe损失、形成于嵌入区域上之金属硅化物之聚集而减少对源极和汲极区之接触电阻、以及当晶体管经受更多于制造IC过程中所遭遇之习知步骤时嵌入材料之增加之应力松弛。
因此，希望最佳化用来制造应力增强的MOS晶体管的方法。此外，希望提供最佳化之应力增强的MOS晶体管其避免习知晶体管制造所伴随之问题。再者，由后续之详细说明及所附之申请专利范围，结合所附之图式和前述技术领域和先前技术，则本发明之其它所希望之特征和特性将变得清楚。
发明内容
本发明提供一种具有增强的主要载子移动率(mobility)之应力增强的MOS晶体管。该应力增强的MOS晶体管包括具有表面的半导体衬底和位于该表面的沟道区。具有第一锗浓度的SiGe的第一区域系嵌入于半导体衬底中。第一区域具有底部和邻近该沟道区的侧部。具有少于该第一锗浓度的第二锗浓度的SiGe的第二区域系嵌入于该第一区域中，使得该侧部具有较该底部为大之厚度。
本发明提供一种用来制造应力增强的MOS晶体管的方法。依照本发明之一个实施例，该方法包括形成栅极电极(gate electrode)，该栅极电极覆盖和界定于单晶半导体衬底中的沟道区。具有面对该沟道区之侧表面之沟槽被蚀刻入该单晶半导体衬底中且邻近该沟道区。沟槽被填满具有第一浓度的取代原子(substitutional atom)的第二单晶半导体材料和具有第二浓度的取代原子的第三单晶半导体材料。第二单晶半导体材料外延生长成具有延着该侧表面之壁厚度足以施加较将由具有第二浓度的单晶半导体材料所施加应力(若该沟槽仅被填满第三单晶半导体材料时)为大之应力于沟道区。
附图说明
上文中结合下列之图式而说明本发明，其中相似之组件符号表示相似之组件，且其中：
图1至图6显示依照本发明之各种实施例之受应力MOS晶体管及其制造方法步骤之剖面图；以及
图7至图9，结合图1至图4，显示依照本发明之替代实施例之受应力MOS晶体管及其制造方法步骤之剖面图。
具体实施方式
下列之详细说明本质上仅为范例，并不意欲用来限制本发明或本发明之应用和使用。再者，本发明并不意欲受前面之技术领域、先前技术、发明内容、或下列之实施方式中所提出之任何表示或暗示理论所限制。
单晶硅(monocrystalline silicon)为使用于半导体工业用来制造半导体器件和集成电路最常见的半导体材料，其特征在于晶格常数，即硅晶体(crystal)之尺寸。藉由取代非硅之原子于晶格中，能够改变所得到的晶体尺寸和晶格常数。若较大的取代原子(譬如锗原子)加入至硅晶格中，则晶格常数增加且晶格常数之增加系正比于取代原子之浓度。相似情况，若较小的取代原子(譬如碳原子)加入至硅晶格中，则晶格常数减小。局部地加入大的取代原子至主(host)硅晶格中则于主晶格产生压缩应力(compressive stress)，而加入小的取代原子至主硅晶格中则于主晶格产生拉伸应力(tensile stress)。
已知增加嵌入SiGe的锗含量则增加应力，该应力能够被施加于PMOS晶体管的沟道，并由此增加晶体管中之主要载子电洞之移动率。亦已知于嵌入SiGe材料的表面具有低浓度的锗避免某些由于在该表面具有高的锗浓度所招致之问题。已尝试藉由下列制程达成于eSiGe主体(bulk)中有高的锗浓度和锗之低表面浓度。沟槽被蚀刻入晶体管之于沟道二端之源极和汲极区中。然后藉由硅锗之选择性外延生长(epitaxialgrowth)制程填满这些沟道。于反应物流(reactant flow)中锗之最初浓度为高而引致高锗浓度SiGe之沉积。于经过外延生长周期之中途于反应物流中锗之浓度减少，而维持着减少浓度的流(flow)直到填满沟槽为止。结果为高锗浓度SiGe下层和低锗浓度SiGe层于该表面。虽然由此种制程产生之器件避免了会由高的锗浓度于SiGe的表面所遭受之问题，但是移动率增加不大于会以填满沟槽之均匀地低锗浓度嵌入SiGe所期望者。
于外延生长制程中，生长之材料层实质地呈现其正生长于其上的表面之形象。观察到不幸地，高锗浓度SiGe之选择性外延生长优先从沟槽之底部生长，而因此于沟槽之侧壁上SiGe膜之生长率(growth rate)为低，造成于侧壁上仅有高锗浓度SiGe之薄层。也就是说，外延生长优先集结于被发现在沟槽之底部的结晶结构上而非在侧壁结晶结构上。覆盖面向晶体管沟道的侧壁的SiGe膜的厚度在施加应力于沟道时为最重要，以及由习知制程所实现之厚度不足以达成所希望的沟道应力和所希望之移动率增加。提供依照本发明之各种实施例，提供MOS晶体管和制造此种器件的方法，其于邻近沟道之区域中达成高锗浓度SiGe之足够的厚度以最佳化沟道应力和移动率增加。
图1至图6显示依照本发明之各种实施例之受应力(stressed)MOS器件30及用于制造此种MOS器件的方法步骤之剖面图。于此例示实施例中，受应力MOS器件30藉由单一P沟道MOS(PMOS)晶体管所例示。从譬如器件30之受应力MOS器件所形成之集成电路能够包含大量之此种晶体管，以及亦可包含未受应力之PMOS晶体管及受应力和未受应力之N沟道MOS(NMOS)晶体管。
于MOS晶体管之制造之各种步骤为已知，而为了简洁之目的，许多习知的步骤于此处将仅简单提及，或将其整个省略而不提供已知之制程细节。虽然词汇“MOS器件”适当地指具有金属栅极电极和氧化物栅极绝缘体之器件，但是该词汇将用于整篇文章中以指任何包含导电栅极电极(不论金属或其它导电材料)的半导体器件，该导电栅极电极位于栅极绝缘体(不论氧化物或其它绝缘体)之上，而该栅极绝缘体依次位于半导体衬底之上。
如图1中所例示，依照本发明之实施例之受应力MOS晶体管30之制造开始于提供半导体衬底36，而此种晶体管被制造于该半导体衬底36中或上。于制造MOS晶体管30之初始步骤为习知，因此不说明其细节。半导体衬底较佳为具有(100)表面结晶方向(surface crystalorientation)的硅衬底，其中此处所用之词汇“硅衬底”和“硅层”包含典型用于半导体工业之相当纯的单晶硅材料以及与其它元素(譬如锗、碳等)混合的硅。下文中为了方便半导体衬底36将称为(但不限定为)硅衬底，虽然熟悉半导体技术者将了解到能够使用其它的半导体材料。硅衬底36可以是主体硅晶圆(未显示)，但是较佳为在绝缘层40上之薄的单晶硅层38(一般已知为绝缘层上覆硅(silicon-on-insulator)或SOI)，该绝缘层40依次由载体晶圆42所支撑。薄硅层38典型具有小于大约200奈米(nm)之厚度(取决于被执行之电路功能而定)，以及于某些应用中较佳具有小于大约90奈米之厚度。薄硅层较佳具有至少大约5至40欧姆公分之电阻率。硅可以被N型或P型杂质掺杂，但是较佳为P型掺杂。典型为二氧化硅之介电绝缘层40较佳具有大约50至200奈米之厚度。
形成隔离区48，其延伸通过单晶硅层38至介电绝缘层40。隔离区较佳由众所周知的浅沟槽隔离(shallow trench isolation，STI)技术形成，其中沟槽被蚀刻入单晶硅层38中，沟槽被填满譬如沉积之二氧化硅之介电材料，以及藉由化学机械平面化法(chemical mechanicalplanarization，CMP)去除过多之二氧化硅。当需要时，STI区域48提供各种电路器件之间之电性隔离，这些电路器件将被形成于单晶硅层38中。于制造STI区域之前或较佳地于制造STI区域之后，能够藉由例如离子植入而杂质掺杂硅层38之选定部分。例如，N型井52能够被N型杂质掺杂以用于PMOS晶体管30之制造。
栅极绝缘体54之层形成于硅层38的表面56上，如图2中所示。栅极绝缘体可为于氧化环境中藉由加热硅衬底而形成之热生长的二氧化硅，或者可以是譬如氧化硅、氮化硅、譬如HfxSiyOz之高介电常数绝缘体、等等之沉积之绝缘体。沉积之绝缘体能够以已知的方法沉积，例如藉由化学气相沉积(CVD)、低压化学气相沉积(LPCVD)、半大气压化学气相沉积(semi-atmospheric chemical vapor deposition，SACVD)、或等离子体辅助化学气相沉积(plasma enhanced chemical vapordeposition，PECVD)。此处显示之栅极绝缘体54为热生长之二氧化硅层，其仅生长在硅层38的表面56上。栅极绝缘体材料典型为1至10奈米厚，而较佳具有1至2奈米之厚度。依照本发明之一个实施例，栅极电极形成材料58之层，较佳是多晶硅层，系沉积于栅极绝缘体之层上。亦可沉积譬如金属和金属硅化物之其它导电栅极电极形成材料(以材料本身或具有适当的杂质掺杂能设定晶体管之所需临限电压为条件)。下文中栅极电极形成材料将称为多晶硅，虽然熟悉此项技术者将了解到亦可使用其它的材料。若栅极电极材料为多晶硅，则藉由硅烷(silane)之氢还原作用使用LPCVD将该材料典型沉积至大约50至200奈米之厚度，而较佳至大约100奈米之厚度。多晶硅层较佳沉积为非掺杂多晶硅，并后续藉由离子植入而被杂质掺杂。譬如氮化硅层之硬屏蔽材料60之层沉积在多晶硅栅极电极形成材料之上。该屏蔽材料之层(若为氮化硅)能藉由例如PECVD而由二氯硅烷(dichlorosilane)和氨(ammonia)之反应而沉积至大约30至50奈米之厚度。熟悉此项技术者将了解到除了氮化硅之其它介电材料能沉积作为硬屏蔽材料。
如图3中所示，栅极电极形成材料58和硬屏蔽材料以光学微影方式被图案化(pattern)并蚀刻以形成由硬屏蔽材料所覆盖之栅极电极62。能藉由例如于Cl和HBr/O2化学品(chemistry)中之等离子体蚀刻而蚀刻多晶硅于所希望之图案，以及能藉由例如于CHF3、CF4、或SF6化学品中之等离子体蚀刻而蚀刻硬屏蔽。在图案化栅极电极之后，依照本发明之一个实施例，氧化硅薄层64被热生长于栅极电极62之相对侧壁65和66上。薄氧化物能够具有例如大约2至3奈米之厚度。栅极电极62之形成界定沟道区68为在栅极电极下方之薄硅层38的表面的部分。较佳情况是沟道沿着【110】晶向(crystal direction)被定向，而使得晶体管中之电流流动将朝向【110】晶向。薄氧化物层64提供衬里(liner)以分隔多晶硅栅极电极与随后沉积之间隔件形成材料。
依照本发明之一个实施例的方法继续，全面性沉积(blanket deposit)氮化硅或其它间隔件形成材料(未图标)之层和各向异性(anisotropically)蚀刻该层以形成覆盖相对侧壁65和66上之二氧化硅薄层64的间隔件70(如图4中所示)。氮化硅层沉积至大约80至250奈米之厚度，较佳藉由使用二氯硅烷和氨作为反应物的LPCVD。侧壁间隔件能够例如藉由使用CF4或CHF3化学品之反应性离子蚀刻(reactive ion etching，RIE)而被各向异性蚀刻。使用间隔件70、栅极电极62、和STI 48作为屏蔽而蚀刻凹部72和74入薄硅层38中。因为侧壁间隔件作为蚀刻屏蔽，因此凹部自行对准于栅极电极62之侧壁65和66及沟道68，并且与栅极电极隔开实质相等于侧壁间隔件之厚度之距离(如箭号69所表示)。例如藉由使用HBr/O2化学物之反应性离子蚀刻(RIE)作各向异性蚀刻凹部72和74至大约400至600奈米之深度(如箭号75所表示)。至少硅层38之薄部分留在沟槽之底表面76下方。
沟槽72和74具有侧表面78和80，分别地面对沟道68。底表面76实质地平行于薄硅层38的表面，并且具有和薄硅层38的表面56相同的结晶方向。底表面76因此位于沿着(100)晶面(crystal plane)。由于沟道68定向于【110】晶向和侧表面78和80实质垂直于表面56，这些侧表面位于沿着(011)晶面。依照本发明之实施例，藉由选择性外延生长制程将沟槽72和74填满嵌入的SiGe 82，该选择性外延生长制程提供(011)晶面之生长率高于(100)晶面之生长率。该选择性外延生长集结于侧表面上及于底表面上，但是能够以已知之方式藉由于外延生长期间调整生长状况(譬如反应物流、生长温度、生长压力、等等，例如于由Rai-Choudhury，P.、Schroder，D.K发表于电化学协会期刊(Journalof the Electrochemical Society)1973年5月，第120册，第5号，第664至668页之“SELECTIVE SILICON EPITAXY AND ORIENTATIONDEPENDENCE OF GROWTH)”中讨论者而于(011)晶面上达成较高生长率。嵌入的SiGe 82的外延生长继续，以部分填满沟槽72和74(如图5中所示)。嵌入的SiGe 82生长成具有高浓度的锗，较佳大约25至40原子百分比锗之间。以此种方式生长之嵌入的SiGe 82于侧表面78和80上生长高锗浓度SiGe之层84较生长于底表面76上之层86为厚。较佳的情况是于侧表面78和80上之高锗含量SiGe具有至少10至30奈米之厚度。
改变选择性外延生长状况以减少锗含量，以及沟槽72和74之其余部分被填满低浓度嵌入的SiGe 88(如图6中所示)。较佳的情况是嵌入的SiGe 88具有大约0至20原子百分比锗的锗浓度。沟槽72和74因此被填满嵌入的SiGe，该嵌入的SiGe具有沿着面对沟道68之侧表面之高锗浓度的厚壁和低锗浓度的表面。
依照本发明之进一步实施例，例示于图5和图6中之结构藉由于具有垂直(亦即，实质垂直于表面56)电位偏压的等离子体环境中外延生长高锗浓度嵌入的SiGe而达成。朝垂直方向的外延生长率(其为于底表面76上之生长率)将藉由等离子体蚀刻成分而降低。于侧表面上生长高锗浓度SiGe之所希望之厚度后，能够改变外延生长状况以降低沟槽再填满之低锗浓度部分的锗浓度。低锗含量部分之生长能够用等离子体环境或不用等离子体环境完成。
依照本发明之进一步实施例，达成所希望之低浓度锗SiGe的表面和沿着面对晶体管沟道之沟槽之侧表面之高锗浓度SiGe之充分厚壁以施加较由低锗浓度SiGe单独施加于沟道之应力为大之应力之最后结果(如图7至图9结合图1至图4中所示)。依照本发明之此实施例的方法开始与图1至图4中所示相同步骤。如图7中所示，沟槽72和74藉由高锗浓度SiGe层90(较佳大约25至40原子百分比锗)之选择性外延生长而被再填满。
方法继续，全面性沉积氮化硅或其它间隔件形成材料(未图标)之层，以覆盖栅极电极62、侧壁间隔件70、和嵌入的SiGe 90。间隔件材料之层能够藉由例如LPCVD而沉积至至少10至30奈米之厚度。间隔件材料之层被例如用RIE非等向性蚀刻，以形成覆盖侧壁间隔件70的侧壁间隔件92。于替代实施例(未图标)中，于沉积该间隔件材料之层前，能去除侧壁间隔件70，该间隔件材料能沉积至大约30至40奈米之厚度，以及能够形成具有30至40奈米厚度之单一侧壁间隔件。不管是使用二个侧壁间隔件或一个较厚侧壁间隔件，该侧壁间隔件、栅极电极、和STI被用作为蚀刻屏蔽以及沟槽94和96被蚀刻入嵌入的SiGe90中(如图8所示)。沟槽94和96能藉由反应性离子蚀刻而被蚀刻至大约15至25奈米之深度(如箭号95所表示)。沟槽94和96自行对准于沟道68，并且与该沟道隔开有间隔件之宽度(如箭号97所表示)。
如图9中所例示，沟槽94和96被再填满选择性生长之低锗浓度外延SiGe 100，较佳具有大约0至20原子百分比的锗浓度。相似于前面的实施例，晶体管具有低锗浓度SiGe表面98和面对沟道68之高锗浓度SiGe之厚壁。高锗浓度SiGe具有足够的厚度以施加较单独由低锗浓度SiGe所施加之应力更多的应力于晶体管的沟道。
虽然未例示，但是图6和图9中所示之结构能用习知的方法完成。习知的步骤包括，例如，去除侧壁间隔件70、92并用单一永久侧壁间隔件替代他们。永久侧壁间隔件用作为离子植入屏蔽，并且导电率决定离子(conductivity determining ion)被植入于栅极电极之任一侧上的硅或SiGe中以形成源极和汲极区域。对于PMOS晶体管，导电率离子能够是硼离子。熟悉此项技术者将了解到可使用多于一组之侧壁间隔件，以及可实施多于一次之离子植入以产生源极和汲极延伸区、产生晕圈植入物(halo implant)、设定临限电压、等等。侧壁间隔件亦能用来形成对源极和汲极区域之自行对准之金属硅化物接点(contact)。沉积并加热硅化物形成金属之层以引致金属与暴露的硅或SiGe反应以形成金属硅化物。不与暴露的硅接触之金属(譬如沉积于侧壁间隔件或STI上之金属)不反应并能藉由在H2O2/H2SO4或HNO3/HCL溶液中蚀刻而去除。于形成受应力MOS晶体管中，譬如受应力氮化硅之应力衬里层可沉积在栅极电极和金属硅化物接点之上。于沉积应力衬里之后接着沉积介电层、平面化介电层、以及蚀刻接触开口穿过介电层至金属硅化物接点。然后能藉由形成在接触开口中之接触插塞(plug)和藉由互连接金属沉积和图案化而制成对源极和汲极区域之电接点。
上述实施例已说明用于制造应力增强的PMOS晶体管的方法。相似的方法可用来制造应力增强的NMOS晶体管，并且任一结构或二者结构之制造可整合成用于制造包含受应力的和非受应力的PMOS和NMOS晶体管二者之CMOS集成电路的方法。制造应力增强的NMOS晶体管相似于上述的方法，除了薄硅层被P型杂质掺杂、源极和汲极区域用N型导电率决定离子杂质掺杂、和外延生长于源极和汲极区域中之嵌入之材料应具有譬如碳之取代原子而使得生长材料之晶格常数小于主材料之晶格常数以在晶体管沟道上产生纵向拉张应力(tensionalstress)。
虽然于本发明之上述详细说明中已提出至少一个范例实施例，但是应该了解到存在有许多之变化。亦应该了解到该范例实施例或诸范例实施例只是例子，而不意欲限制本发明之范围、应用、或组构于任何方式。而是，以上之详细说明将提供熟悉此项技术者施行本发明之该范例实施例或诸范例实施例之方便的路途指引。应了解到在组件之功能和配置可以作各种之改变而不脱离所附之申请专利范围与其合法之均等者提出之本发明之范围。

Claims (8)

1、一种用于制造应力增强的MOS器件(30)的方法，该MOS器件具有位于半导体衬底(38)的表面(56)的沟道区(68)，该方法包括下列步骤：
蚀刻沟槽(72、74)进入该半导体衬底中且邻近该沟道区，每个该沟槽具有面对该沟道区的侧表面(78、80)、和底表面(76)；
在衬底沟槽中外延生长具有第一浓度的锗的SiGe的第一层(82)，以部分填满这些沟槽，该SiGe的第一层在该侧表面上具有第一生长率，而在该底表面上具有小于该第一生长率的第二生长率；以及
外延生长具有小于该第一浓度的第二浓度的锗的SiGe的第二层(88)以填满这些沟槽。
2、如权利要求1所述的方法，其中，该半导体衬底(38)为包括具有<100>结晶表面方向的硅的衬底，该沟道区(68)沿着<110>晶向被定向，该侧表面(78、80)具有<011>结晶表面方向，以及其中，该外延生长第一层的步骤包括调整外延生长状况的步骤以相比于<100>结晶表面上的外延生长率而增强<011>结晶表面上的外延生长率。
3、如权利要求1所述的方法，其中，外延生长第一层(82)的步骤包括在具有实质垂直于该半导体衬底的电位偏压的等离子体环境中外延生长第一层的步骤。
4、一种用于制造应力增强的MOS晶体管(30)的方法，包括下列步骤：
形成栅极绝缘体(54)覆盖半导体衬底(38)；
形成栅极电极(62)覆盖该栅极绝缘体，该栅极电极具有第一边缘(65)和第二边缘(66)；
蚀刻第一沟槽(72)和第二沟槽(74)进入该半导体衬底中，该第一沟槽对准于该第一边缘并与该第一边缘隔开第一距离(69)，而该第二沟槽对准于该第二边缘并与该第二边缘隔开该第一距离；
在该第一沟槽和该第二沟槽中外延生长具有第一浓度的锗的SiGe的第一层(90)；该第一层具有厚度足以填满该第一沟槽和该第二沟槽；
蚀刻第三沟槽(94)和第四沟槽(96)进入该第一层中，该第三沟槽对准于该第一侧并与该第一侧隔开第二距离(97)，该第二距离大于该第一距离，而该第四沟槽对准于该第二侧并与该第二侧隔开该第二距离；以及
在该第三沟槽和该第四沟槽中外延生长具有第二浓度的锗的SiGe的第二层(100)，该第二浓度小于该第一浓度，且该第二层的SiGe具有第二厚度(95)足以填满该第三沟槽和该第四沟槽。
5、如权利要求4所述的方法，其中，该外延生长第一层(90)的步骤包括外延生长包括25至40原子百分比锗的SiGe的层的步骤，以及其中，该外延生长第二层(100)的步骤包括外延生长SiGe的第二层的步骤，SiGe的第二层包括小于20原子百分比的锗。
6、一种应力增强的MOS晶体管(30)，包括：
具有表面(56)的半导体衬底(38)；
位于该半导体衬底的该表面的沟道区域(68)；
具有第一锗浓度的SiGe的第一区域(82)，嵌入于该半导体衬底中且具有底部(86)和邻近该沟道区的侧部(84)，且其中，该侧部具有大于该底部的厚度；
SiGe的第二区域(88)，嵌入于该第一区域中，且具有小于该第一锗浓度的第二锗浓度。
7、如权利要求6所述的应力MOS晶体管，其中，该SiGe的第一区域(82)具有25至40原子百分比的锗浓度。
8、如权利要求7所述的应力MOS晶体管，其中，该SiGe的第二区域(88)具有小于20原子百分比的锗浓度。
CN2007800427664A 2006-11-21 2007-11-16 应力增强的mos晶体管及其制造方法 Expired - Fee Related CN101578690B (zh)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US11/562,209 2006-11-21
US11/562,209 US7534689B2 (en) 2006-11-21 2006-11-21 Stress enhanced MOS transistor and methods for its fabrication
PCT/US2007/024034 WO2008063543A2 (en) 2006-11-21 2007-11-16 Stress enhanced mos transistor and methods for its fabrication

Publications (2)

Publication Number Publication Date
CN101578690A true CN101578690A (zh) 2009-11-11
CN101578690B CN101578690B (zh) 2011-10-12

Family

ID=39327099

Family Applications (1)

Application Number Title Priority Date Filing Date
CN2007800427664A Expired - Fee Related CN101578690B (zh) 2006-11-21 2007-11-16 应力增强的mos晶体管及其制造方法

Country Status (9)

Country Link
US (1) US7534689B2 (zh)
EP (1) EP2095408B1 (zh)
JP (1) JP5283233B2 (zh)
KR (1) KR101386711B1 (zh)
CN (1) CN101578690B (zh)
AT (1) ATE478434T1 (zh)
DE (1) DE602007008611D1 (zh)
TW (1) TWI440097B (zh)
WO (1) WO2008063543A2 (zh)

Cited By (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101373788B (zh) * 2007-04-27 2011-02-16 台湾积体电路制造股份有限公司 半导体结构
CN102487073A (zh) * 2010-12-03 2012-06-06 台湾积体电路制造股份有限公司 具有提高的载体迁移率的源极/漏极应力源及其制造方法
CN102945793A (zh) * 2012-12-03 2013-02-27 上海集成电路研发中心有限公司 一种外延生长锗硅应力层的预清洗方法
CN103219340A (zh) * 2012-01-23 2013-07-24 台湾积体电路制造股份有限公司 用于具有线端延长的晶体管的结构和方法
CN103314434A (zh) * 2011-01-19 2013-09-18 国际商业机器公司 具有源极/漏极缓冲区的应力沟道fet
CN103594338A (zh) * 2012-08-16 2014-02-19 中芯国际集成电路制造(上海)有限公司 一种半导体器件的制造方法
CN103632969A (zh) * 2012-08-21 2014-03-12 中芯国际集成电路制造(上海)有限公司 晶体管的形成方法
CN103779213A (zh) * 2012-10-18 2014-05-07 中芯国际集成电路制造(上海)有限公司 一种半导体器件及其制造方法
CN104979207A (zh) * 2014-04-04 2015-10-14 中芯国际集成电路制造(上海)有限公司 Mos晶体管的制作方法
CN103594338B (zh) * 2012-08-16 2016-11-30 中芯国际集成电路制造(上海)有限公司 一种半导体器件的制造方法
CN104241130B (zh) * 2013-06-09 2018-04-27 中芯国际集成电路制造(上海)有限公司 Pmos晶体管及其形成方法、半导体器件及其形成方法

Families Citing this family (61)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7696019B2 (en) * 2006-03-09 2010-04-13 Infineon Technologies Ag Semiconductor devices and methods of manufacturing thereof
US8278176B2 (en) 2006-06-07 2012-10-02 Asm America, Inc. Selective epitaxial formation of semiconductor films
US7504301B2 (en) * 2006-09-28 2009-03-17 Advanced Micro Devices, Inc. Stressed field effect transistor and methods for its fabrication
US7544997B2 (en) * 2007-02-16 2009-06-09 Freescale Semiconductor, Inc. Multi-layer source/drain stressor
JP4896789B2 (ja) * 2007-03-29 2012-03-14 株式会社東芝 半導体装置の製造方法
US20080237634A1 (en) * 2007-03-30 2008-10-02 International Business Machines Corporation Crystallographic recess etch for embedded semiconductor region
FR2914783A1 (fr) * 2007-04-03 2008-10-10 St Microelectronics Sa Procede de fabrication d'un dispositif a gradient de concentration et dispositif correspondant.
US8344447B2 (en) 2007-04-05 2013-01-01 Taiwan Semiconductor Manufacturing Company, Ltd. Silicon layer for stopping dislocation propagation
US20080303060A1 (en) * 2007-06-06 2008-12-11 Jin-Ping Han Semiconductor devices and methods of manufacturing thereof
US7759199B2 (en) * 2007-09-19 2010-07-20 Asm America, Inc. Stressor for engineered strain on channel
KR101369907B1 (ko) * 2007-10-31 2014-03-04 주성엔지니어링(주) 트랜지스터 및 그 제조 방법
US7960229B2 (en) * 2008-04-10 2011-06-14 Globalfoundries Inc. Metal oxide semiconductor transistor with reduced gate height, and related fabrication methods
KR101561059B1 (ko) * 2008-11-20 2015-10-16 삼성전자주식회사 반도체 소자 및 그 제조 방법
DE102008063427B4 (de) * 2008-12-31 2013-02-28 Advanced Micro Devices, Inc. Verfahren zum selektiven Herstellen eines Transistors mit einem eingebetteten verformungsinduzierenden Material mit einer graduell geformten Gestaltung
US20100207175A1 (en) * 2009-02-16 2010-08-19 Advanced Micro Devices, Inc. Semiconductor transistor device having an asymmetric embedded stressor configuration, and related manufacturing method
US8305829B2 (en) 2009-02-23 2012-11-06 Taiwan Semiconductor Manufacturing Company, Ltd. Memory power gating circuit for controlling internal voltage of a memory array, system and method for controlling the same
US8305790B2 (en) 2009-03-16 2012-11-06 Taiwan Semiconductor Manufacturing Company, Ltd. Electrical anti-fuse and related applications
DE102009015748B4 (de) * 2009-03-31 2014-05-22 Globalfoundries Dresden Module One Limited Liability Company & Co. Kg Verringern des Silizidwiderstands in SiGe-enthaltenden Drain/Source-Gebieten von Transistoren
US8957482B2 (en) 2009-03-31 2015-02-17 Taiwan Semiconductor Manufacturing Company, Ltd. Electrical fuse and related applications
US8912602B2 (en) 2009-04-14 2014-12-16 Taiwan Semiconductor Manufacturing Company, Ltd. FinFETs and methods for forming the same
US8461015B2 (en) 2009-07-08 2013-06-11 Taiwan Semiconductor Manufacturing Company, Ltd. STI structure and method of forming bottom void in same
US8264032B2 (en) 2009-09-01 2012-09-11 Taiwan Semiconductor Manufacturing Company, Ltd. Accumulation type FinFET, circuits and fabrication method thereof
US8629478B2 (en) 2009-07-31 2014-01-14 Taiwan Semiconductor Manufacturing Company, Ltd. Fin structure for high mobility multiple-gate transistor
US8472227B2 (en) 2010-01-27 2013-06-25 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated circuits and methods for forming the same
US9484462B2 (en) 2009-09-24 2016-11-01 Taiwan Semiconductor Manufacturing Company, Ltd. Fin structure of fin field effect transistor
US8623728B2 (en) 2009-07-28 2014-01-07 Taiwan Semiconductor Manufacturing Company, Ltd. Method for forming high germanium concentration SiGe stressor
US8759943B2 (en) 2010-10-08 2014-06-24 Taiwan Semiconductor Manufacturing Company, Ltd. Transistor having notched fin structure and method of making the same
US8440517B2 (en) 2010-10-13 2013-05-14 Taiwan Semiconductor Manufacturing Company, Ltd. FinFET and method of fabricating the same
US8497528B2 (en) 2010-05-06 2013-07-30 Taiwan Semiconductor Manufacturing Company, Ltd. Method for fabricating a strained structure
US8980719B2 (en) 2010-04-28 2015-03-17 Taiwan Semiconductor Manufacturing Company, Ltd. Methods for doping fin field-effect transistors
US8482073B2 (en) 2010-03-25 2013-07-09 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated circuit including FINFETs and methods for forming the same
US8298925B2 (en) 2010-11-08 2012-10-30 Taiwan Semiconductor Manufacturing Company, Ltd. Mechanisms for forming ultra shallow junction
US8264021B2 (en) 2009-10-01 2012-09-11 Taiwan Semiconductor Manufacturing Company, Ltd. Finfets and methods for forming the same
US8415718B2 (en) * 2009-10-30 2013-04-09 Taiwan Semiconductor Manufacturing Company, Ltd. Method of forming epi film in substrate trench
US9040393B2 (en) 2010-01-14 2015-05-26 Taiwan Semiconductor Manufacturing Company, Ltd. Method of forming semiconductor structure
US20110215376A1 (en) * 2010-03-08 2011-09-08 International Business Machines Corporation Pre-gate, source/drain strain layer formation
US8395213B2 (en) * 2010-08-27 2013-03-12 Acorn Technologies, Inc. Strained semiconductor using elastic edge relaxation of a stressor combined with buried insulating layer
US8377780B2 (en) * 2010-09-21 2013-02-19 International Business Machines Corporation Transistors having stressed channel regions and methods of forming transistors having stressed channel regions
US9006052B2 (en) * 2010-10-11 2015-04-14 International Business Machines Corporation Self aligned device with enhanced stress and methods of manufacture
US8603924B2 (en) 2010-10-19 2013-12-10 Taiwan Semiconductor Manufacturing Company, Ltd. Methods of forming gate dielectric material
US8642407B2 (en) * 2010-11-04 2014-02-04 International Business Machines Corporation Devices having reduced susceptibility to soft-error effects and method for fabrication
US9048181B2 (en) 2010-11-08 2015-06-02 Taiwan Semiconductor Manufacturing Company, Ltd. Mechanisms for forming ultra shallow junction
US8741725B2 (en) * 2010-11-10 2014-06-03 International Business Machines Corporation Butted SOI junction isolation structures and devices and method of fabrication
US8769446B2 (en) 2010-11-12 2014-07-01 Taiwan Semiconductor Manufacturing Company, Ltd. Method and device for increasing fin device density for unaligned fins
US8877602B2 (en) 2011-01-25 2014-11-04 Taiwan Semiconductor Manufacturing Company, Ltd. Mechanisms of doping oxide for forming shallow trench isolation
US8592915B2 (en) 2011-01-25 2013-11-26 Taiwan Semiconductor Manufacturing Company, Ltd. Doped oxide for shallow trench isolation (STI)
US9029227B2 (en) * 2011-03-01 2015-05-12 Globalfoundries Singapore Pte. Ltd. P-channel flash with enhanced band-to-band tunneling hot electron injection
US8431453B2 (en) 2011-03-31 2013-04-30 Taiwan Semiconductor Manufacturing Company, Ltd. Plasma doping to reduce dielectric loss during removal of dummy layers in a gate structure
US8809170B2 (en) 2011-05-19 2014-08-19 Asm America Inc. High throughput cyclical epitaxial deposition and etch process
US8754448B2 (en) * 2011-11-01 2014-06-17 United Microelectronics Corp. Semiconductor device having epitaxial layer
US20140057399A1 (en) * 2012-08-24 2014-02-27 International Business Machines Corporation Using Fast Anneal to Form Uniform Ni(Pt)Si(Ge) Contacts on SiGe Layer
KR20140042460A (ko) * 2012-09-28 2014-04-07 삼성전자주식회사 반도체 소자
US8906759B2 (en) * 2013-02-25 2014-12-09 International Business Machines Corporation Silicon nitride gate encapsulation by implantation
US9012964B2 (en) * 2013-08-09 2015-04-21 Taiwan Semiconductor Manufacturing Company, Ltd. Modulating germanium percentage in MOS devices
US20150372100A1 (en) * 2014-06-19 2015-12-24 GlobalFoundries, Inc. Integrated circuits having improved contacts and methods for fabricating same
US9343300B1 (en) * 2015-04-15 2016-05-17 Globalfoundries Inc. Methods of forming source/drain regions for a PMOS transistor device with a germanium-containing channel region
US9806194B2 (en) * 2015-07-15 2017-10-31 Samsung Electronics Co., Ltd. FinFET with fin having different Ge doped region
JP6584348B2 (ja) * 2016-03-07 2019-10-02 東京エレクトロン株式会社 凹部の埋め込み方法および処理装置
CN108987399A (zh) * 2017-06-05 2018-12-11 中芯国际集成电路制造(上海)有限公司 半导体装置及其制造方法
WO2019066965A1 (en) * 2017-09-29 2019-04-04 Intel Corporation DEVICE, METHOD AND SYSTEM FOR FAVORING CHANNEL STRESS IN AN NMOS TRANSISTOR
US10461155B2 (en) * 2017-11-14 2019-10-29 Globalfoundries Inc. Epitaxial region for embedded source/drain region having uniform thickness

Family Cites Families (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5181089A (en) * 1989-08-15 1993-01-19 Matsushita Electric Industrial Co., Ltd. Semiconductor memory device and a method for producing the same
JP2877108B2 (ja) * 1996-12-04 1999-03-31 日本電気株式会社 半導体装置およびその製造方法
JPH10326837A (ja) * 1997-03-25 1998-12-08 Toshiba Corp 半導体集積回路装置の製造方法、半導体集積回路装置、半導体装置、及び、半導体装置の製造方法
US5970352A (en) * 1998-04-23 1999-10-19 Kabushiki Kaisha Toshiba Field effect transistor having elevated source and drain regions and methods for manufacturing the same
US6426532B1 (en) * 1998-06-30 2002-07-30 Sharp Kabushiki Kaisha Semiconductor device and method of manufacture thereof
JP2000243958A (ja) * 1999-02-24 2000-09-08 Toshiba Corp 半導体装置およびその製造方法
KR20000065719A (ko) * 1999-04-08 2000-11-15 김영환 반도체 소자 및 그 제조방법
US6274894B1 (en) * 1999-08-17 2001-08-14 Advanced Micro Devices, Inc. Low-bandgap source and drain formation for short-channel MOS transistors
US6805962B2 (en) * 2002-01-23 2004-10-19 International Business Machines Corporation Method of creating high-quality relaxed SiGe-on-insulator for strained Si CMOS applications
US6657223B1 (en) * 2002-10-29 2003-12-02 Advanced Micro Devices, Inc. Strained silicon MOSFET having silicon source/drain regions and method for its fabrication
US6949482B2 (en) 2003-12-08 2005-09-27 Intel Corporation Method for improving transistor performance through reducing the salicide interface resistance
US7129488B2 (en) * 2003-12-23 2006-10-31 Sharp Laboratories Of America, Inc. Surface-normal optical path structure for infrared photodetection
KR100549005B1 (ko) * 2004-02-27 2006-02-02 삼성전자주식회사 선택적 에피성장층을 채택하여 비대칭 소오스/드레인트랜지스터를 제조하는 방법 및 그것에 의해 제조된비대칭 소오스/드레인 트랜지스터
JP4369359B2 (ja) * 2004-12-28 2009-11-18 富士通マイクロエレクトロニクス株式会社 半導体装置
US7238580B2 (en) * 2005-01-26 2007-07-03 Freescale Semiconductor, Inc. Semiconductor fabrication process employing stress inducing source drain structures with graded impurity concentration
WO2006083546A2 (en) 2005-01-31 2006-08-10 Advanced Micro Devices, Inc. In situ formed halo region in a transistor device
US7545023B2 (en) * 2005-03-22 2009-06-09 United Microelectronics Corp. Semiconductor transistor
US7226820B2 (en) * 2005-04-07 2007-06-05 Freescale Semiconductor, Inc. Transistor fabrication using double etch/refill process
US7442589B2 (en) * 2006-01-17 2008-10-28 Honeywell International Inc. System and method for uniform multi-plane silicon oxide layer formation for optical applications

Cited By (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7989901B2 (en) 2007-04-27 2011-08-02 Taiwan Semiconductor Manufacturing Company, Ltd. MOS devices with improved source/drain regions with SiGe
CN101373788B (zh) * 2007-04-27 2011-02-16 台湾积体电路制造股份有限公司 半导体结构
US8569846B2 (en) 2007-04-27 2013-10-29 Taiwan Semiconductor Manufacturing Company, Ltd. MOS devices with improved source/drain regions with SiGe
CN102487073A (zh) * 2010-12-03 2012-06-06 台湾积体电路制造股份有限公司 具有提高的载体迁移率的源极/漏极应力源及其制造方法
CN102487073B (zh) * 2010-12-03 2016-05-04 台湾积体电路制造股份有限公司 具有提高的载体迁移率的源极/漏极应力源及其制造方法
CN103314434B (zh) * 2011-01-19 2016-01-20 国际商业机器公司 具有源极/漏极缓冲区的应力沟道fet
CN103314434A (zh) * 2011-01-19 2013-09-18 国际商业机器公司 具有源极/漏极缓冲区的应力沟道fet
CN103219340A (zh) * 2012-01-23 2013-07-24 台湾积体电路制造股份有限公司 用于具有线端延长的晶体管的结构和方法
CN103594338A (zh) * 2012-08-16 2014-02-19 中芯国际集成电路制造(上海)有限公司 一种半导体器件的制造方法
CN103594338B (zh) * 2012-08-16 2016-11-30 中芯国际集成电路制造(上海)有限公司 一种半导体器件的制造方法
CN103632969A (zh) * 2012-08-21 2014-03-12 中芯国际集成电路制造(上海)有限公司 晶体管的形成方法
CN103779213A (zh) * 2012-10-18 2014-05-07 中芯国际集成电路制造(上海)有限公司 一种半导体器件及其制造方法
CN102945793A (zh) * 2012-12-03 2013-02-27 上海集成电路研发中心有限公司 一种外延生长锗硅应力层的预清洗方法
CN104241130B (zh) * 2013-06-09 2018-04-27 中芯国际集成电路制造(上海)有限公司 Pmos晶体管及其形成方法、半导体器件及其形成方法
CN104979207A (zh) * 2014-04-04 2015-10-14 中芯国际集成电路制造(上海)有限公司 Mos晶体管的制作方法
CN104979207B (zh) * 2014-04-04 2019-04-26 中芯国际集成电路制造(上海)有限公司 Mos晶体管的制作方法

Also Published As

Publication number Publication date
US20080119031A1 (en) 2008-05-22
TWI440097B (zh) 2014-06-01
CN101578690B (zh) 2011-10-12
TW200832566A (en) 2008-08-01
EP2095408B1 (en) 2010-08-18
KR101386711B1 (ko) 2014-04-18
ATE478434T1 (de) 2010-09-15
WO2008063543A3 (en) 2008-07-17
JP5283233B2 (ja) 2013-09-04
WO2008063543A2 (en) 2008-05-29
DE602007008611D1 (de) 2010-09-30
EP2095408A2 (en) 2009-09-02
US7534689B2 (en) 2009-05-19
KR20090091788A (ko) 2009-08-28
JP2010510684A (ja) 2010-04-02

Similar Documents

Publication Publication Date Title
CN101578690B (zh) 应力增强的mos晶体管及其制造方法
CN101233605B (zh) 用于制造受应力的mos器件的方法
CN101213654B (zh) 用于形成具有不同特性之接触绝缘层及硅化物区域之技术
CN101233606B (zh) 用于制造受应力的mos器件的方法
US7704840B2 (en) Stress enhanced transistor and methods for its fabrication
TWI446453B (zh) 受應力之場效電晶體以及其製造方法
US20080220579A1 (en) Stress enhanced mos transistor and methods for its fabrication
US7601574B2 (en) Methods for fabricating a stress enhanced MOS transistor
CN101281926B (zh) 半导体结构
US7238580B2 (en) Semiconductor fabrication process employing stress inducing source drain structures with graded impurity concentration
US7994010B2 (en) Process for fabricating a semiconductor device having embedded epitaxial regions
KR20060026447A (ko) 회로 디바이스를 포함하는 장치 및 그 장치의 제조 방법
CN101373788A (zh) 半导体结构
US9064961B2 (en) Integrated circuits including epitaxially grown strain-inducing fills doped with boron for improved robustness from delimination and methods for fabricating the same
CN102292811A (zh) 具有外延成长的应力引发源极与漏极区的金氧半导体装置的制造方法
US7416931B2 (en) Methods for fabricating a stress enhanced MOS circuit
JP2006165480A (ja) 半導体装置
US20110306170A1 (en) Novel Method to Improve Performance by Enhancing Poly Gate Doping Concentration in an Embedded SiGe PMOS Process
US20130175640A1 (en) Stress enhanced mos transistor and methods for fabrication
CN117080248A (zh) 半导体器件制备方法

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant
TR01 Transfer of patent right

Effective date of registration: 20181123

Address after: New Hampshire

Patentee after: Innovation Core Making Co.,Ltd.

Address before: California, USA

Patentee before: ADVANCED MICRO DEVICES, Inc.

TR01 Transfer of patent right
CF01 Termination of patent right due to non-payment of annual fee

Granted publication date: 20111012

CF01 Termination of patent right due to non-payment of annual fee