CN103314434B - 具有源极/漏极缓冲区的应力沟道fet - Google Patents

具有源极/漏极缓冲区的应力沟道fet Download PDF

Info

Publication number
CN103314434B
CN103314434B CN201280004994.3A CN201280004994A CN103314434B CN 103314434 B CN103314434 B CN 103314434B CN 201280004994 A CN201280004994 A CN 201280004994A CN 103314434 B CN103314434 B CN 103314434B
Authority
CN
China
Prior art keywords
drain
source
fet
substrate
stressor material
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201280004994.3A
Other languages
English (en)
Other versions
CN103314434A (zh
Inventor
J·B·约翰逊
R·穆拉丽达
P·J·欧尔迪吉斯
V·C·昂塔路斯
修凯
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Core Usa Second LLC
GlobalFoundries Inc
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Publication of CN103314434A publication Critical patent/CN103314434A/zh
Application granted granted Critical
Publication of CN103314434B publication Critical patent/CN103314434B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0843—Source or drain regions of field-effect devices
    • H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823412—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823418—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823807—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823814—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1203—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
    • H01L29/161—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table including two or more of the elements provided for in group H01L29/16, e.g. alloys
    • H01L29/165—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table including two or more of the elements provided for in group H01L29/16, e.g. alloys in different semiconductor regions, e.g. heterojunctions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66636—Lateral single gate silicon transistors with source or drain recessed by etching or first recessed by etching and then refilled
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
    • H01L29/7848—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate the means being located in the source/drain region, e.g. SiGe source and drain

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Thin Film Transistor (AREA)

Abstract

一种用于形成具有源极/漏极缓冲区（501）的应力沟道场效应晶体管（FET）的方法包括：在位于所述衬底（201）上的栅极叠层（202/203）两侧在所述衬底中蚀刻腔（301）；在所述腔中沉积源极/漏极缓冲材料（401）；蚀刻所述源极/漏极缓冲材料以形成与所述FET的沟道区（502）相邻的垂直源极/漏极缓冲区；以及在所述腔中与所述垂直源极/漏极缓冲区相邻地以及在所述垂直源极/漏极缓冲区上方沉积源极/漏极应力源材料（601）。

Description

具有源极/漏极缓冲区的应力沟道FET
技术领域
本公开总体上涉及半导体制造领域，更具体地，涉及形成具有应力沟道区（stressedchannelregion）的场效应晶体管（FET）器件。
背景技术
半导体器件衬底内的机械应力可用于调整器件性能。例如，在硅（Si）技术中，FET的沟道可以沿着硅的{110}面取向。在这种布置中，当沟道处于膜方向上的压应力下和/或处于沟道的法线方向上的张应力下时空穴迁移率增强，而当硅膜处于沟道法线方向上的张应力下时电子迁移率增强。因此，可以有利地在p型FET（PFET）或n型FET（NFET）的沟道区中产生压应力和/或张应力，以增强这种器件的性能。
产生受到所需应力的沟道区的一种可能方法是：对于PFET，在FET器件的源极/漏极区中的应力腔中形成嵌入的硅锗（SiGe）源极/漏极应力源材料（stressormaterial），或者对于NFET在所述应力腔中形成嵌入的碳化硅（SiC）源极/漏极应力源材料，以在位于源极区和漏极区之间的沟道区中引起压应变或张应变。可以原位地重掺杂源极/漏极应力源材料，以避免可使得沟道应力劣化的对应力源的注入损伤。尽管沟道应力随着应力源与沟道的邻近程度的减小而增加，但是重掺杂的源极/漏极应力源材料与FET沟道的紧密邻近可使得完成的应力沟道FET器件的静电学性能劣化。特别地，与沟道区紧密邻近的重掺杂的源极/漏极材料可加剧短沟道效应以及穿通问题，并且还可增加FET工作期间的寄生泄漏、结电容和源自带间隧穿的浮体效应。
发明内容
在一方面中，一种用于形成具有源极/漏极缓冲区的应力沟道场效应晶体管（FET）的方法包括：在位于衬底上的栅极叠层的两侧在所述衬底中蚀刻腔；在所述腔中沉积源极/漏极缓冲材料；蚀刻所述源极/漏极缓冲材料以形成与所述FET的沟道区相邻的垂直源极/漏极缓冲区；以及在所述腔中与所述垂直源极/漏极缓冲区相邻地以及在所述垂直源极/漏极缓冲区上方，沉积源极/漏极应力源材料。
在一方面中，一种应力沟道场效应晶体管（FET）包括：衬底；位于所述衬底上的栅极叠层；在所述栅极叠层下方且位于所述衬底中的沟道区；在所述沟道区的两侧且位于所述衬底中的腔内的源极/漏极应力源材料；以及在所述源极/漏极应力源材料与所述衬底之间且位于所述衬底中的所述腔内的垂直源极/漏极缓冲区，其中所述源极/漏极应力源材料在所述源极/漏极缓冲区上方邻接所述沟道区。
通过本示例性实施例的技术实现另外的特征。本文中详细描述了其它实施例，这些实施例被认为是要求保护的发明的一部分。为了更好地理解示例性实施例的特征，参考说明书和附图。
附图说明
现在参考附图，其中在若干图中相似的部件标以相似的附图标记：
图1示例出制造具有源极/漏极缓冲区的嵌入的应力源沟道FET的方法的实施例的流程图。
图2是示例出具有栅极和分隔物（spacer）的衬底的实施例的示意性框图。
图3是示例出在蚀刻出嵌入的应力源腔之后图2的器件的实施例的示意性框图。
图4是示例出在嵌入的应力源腔中沉积源极/漏极缓冲材料之后图3的器件的实施例的示意性框图。
图5是示例出在蚀刻源极/漏极缓冲材料而形成源极/漏极缓冲区之后图4的器件的实施例的示意性框图。
图6是示例出在与源极/漏极缓冲区相邻地在应力阱中沉积源极/漏极嵌入应力源材料（embeddedstressormaterial）之后图5的器件的实施例的示意性框图。
图7是示例出包括源极/漏极缓冲区的FET的嵌入应力源FET的实施例的示意性框图。
具体实施方式
提供了包含源极/漏极缓冲区的应力沟道FET器件以及制造包含源极/漏极缓冲区的应力沟道FET器件的方法的实施例，其中在下文中详细描述示例性实施例。在沟道和嵌入的源极/漏极应力源材料之间的源极/漏极缓冲区的形成用于减小在工作期间应力沟道FET中的结电容和漏电流，同时允许源极/漏极应力源材料相对紧密地邻近沟道，这增加了FET器件中嵌入的应力源材料的量以及由应力源材料在沟道中引起的应力的量。在各种实施例中，源极/漏极缓冲区可以是轻掺杂的或未掺杂的SiGe或SiC。
图1示例出形成具有源极/漏极缓冲区的应力沟道FET的方法100的实施例。方法100可以用于在各种实施例中形成NFET或PFET。参考图2-7讨论图1。在框101中，提供如图2所示的起始器件。器件200包括位于衬底201上的、具有栅极电介质层202和栅电极203的栅极叠层结构以及围绕栅极叠层结构的分隔物204。在各种实施例中，栅极叠层结构202/203可以是任何适当类型的FET栅极，包括但不限于高k/金属栅极、多晶硅、或者通过替换栅极工艺制造的FET的伪栅极。在一些实施例中，分隔物204可以是诸如氮化物或氧化物的电介质材料。分隔物204用于在方法100的执行期间保护栅极叠层结构202/203；在图1所示的实施例中，分隔物204覆盖栅极叠层结构202/203的顶部。衬底201在一些实施例中可以是硅衬底，或者在其它实施例中可以是包括在掩埋氧化物（BOX）层之上的顶部硅层的绝缘体上硅（SOI）衬底。在框101中蚀刻器件200的衬底201，从而在衬底201中形成嵌入的应力源腔301，如图3中的器件300所示。在栅极叠层结构202/203和分隔物204的两侧在衬底201中蚀刻出嵌入的应力源腔301。在各种实施例中，框101的蚀刻可以包括反应离子（RIE）蚀刻，并且可以是各向异性蚀刻或者各向异性和各向同性蚀刻的组合，以便设定所需的与FET的栅极边缘的邻近程度。在一些实施例中，衬底201中嵌入的应力源腔301的深度可以是约30到约80纳米（nm）。在衬底201包括SOI的实施例中，嵌入的应力源腔301的底部可以几乎与衬底201的BOX邻接；然而，在应力源腔301的底部与BOX之间需要一些半导体材料以便于后续的外延生长。在一些实施例中，在蚀刻了嵌入的应力源腔301之后，位于腔301底部的衬底201的部分可以可选地被掺杂。该可选的掺杂可以包括用硼掺杂以形成PFET，或者用磷掺杂以形成NFET。
在框102中，在嵌入的应力源腔301中沉积源极/漏极缓冲材料401，得到如图4所示的器件400。源极/漏极缓冲材料401可以包括未掺杂的SiGe或轻掺杂硼的SiGe以形成PFET，或者可以包括未掺杂的SiC或者轻掺杂磷的SiC以形成PFET。源极/漏极缓冲材料401的沉积是外延的。在一些实施例中，源极/漏极缓冲材料401也可以形成在分隔物204上。在一些实施例中，沉积的源极/漏极缓冲材料401可以具有约5nm到约15nm的厚度。
在框103中，蚀刻所沉积的源极/漏极缓冲材料401，在应力源腔301中得到垂直的源极/漏极缓冲区501，如图5所示。源极/漏极缓冲区的位置与衬底201中的FET沟道区502相邻。源极/漏极缓冲区501的顶部凹陷以暴露位于栅极202/203和分隔物204下方的衬底501的沟道区502的一部分。在一些实施例中，框103的蚀刻可以包括各向异性RIE，并且可以到达栅极叠层结构202/203和分隔物204下方约5nm到约15nm的深度。在图4所示的实施例中，从嵌入的应力源腔301的底部去除所有所沉积的源极/漏极缓冲材料401；然而，在一些实施例中，在框103的RIE蚀刻之后可以在嵌入的应力源腔301的底部保留一些沉积的源极/漏极缓冲材料。
在框104中，在嵌入的应力源腔301中与源极/漏极缓冲区501相邻地以及可选地在源极/漏极缓冲区501上方，沉积源极/漏极应力源材料601，得到如图6所示的器件600。源极/漏极应力源材料601包括重掺杂的材料，例如用于PFET的掺硼的SiGe（特别地，原位掺杂的硼或者ISDB、SiGe）或者用于NFET的掺磷的SiC。源极/漏极应力源材料601可以被沉积为晶体材料，并且可以通过外延沉积来沉积。源极/漏极应力源材料601可以过充满（overfill）嵌入的应力源腔301，如图6的实施例中所示；在一些实施例中，该过充满可以是比衬底201的顶部高出约0nm到约30nm。
源极/漏极应力源材料601仅在源极/漏极缓冲区501上方邻接衬底201的沟道部分502；在一些实施例中，源极/漏极嵌入的应力源材料601与衬底201之间的该接触区域的深度可以是在衬底201中与栅极叠层结构202/203的底部相距约5nm到约15nm。沟道502与源极/漏极应力源材料601之间的这种相对短的接触区域减小了FET700在工作期间的漏电流和结电容，同时在衬底201的沟道部分中引起应力以提高沟道502的迁移率。
最后，在框105中，在框104中沉积源极/漏极嵌入应力源材料601之后，在分隔物覆盖栅极顶部的实施例中，可以从栅极叠层结构202/203顶部去除分隔物204的一部分（以及在框102或104器件可能已沉积在分隔物204的顶部上的任何其它材料）。然后，可以在栅极叠层结构202/203的顶上形成栅极接触701，以形成完成的应力沟道FET700，如图7所示。在栅极202/203包括伪栅极的实施例中，可以去除伪栅极，并且在形成栅极接触之前形成替换伪栅极的替换栅极以形成完成的FET。
示例性实施例的技术效果和益处包括具有相对高的沟道迁移率和相对低的漏电流和结电容的FET。
本文中所用的术语，仅仅是为了描述特定的实施例，而不意图限定本发明。本文中所用的单数形式的“一”和“该”，旨在也包括复数形式，除非上下文中明确地另行指出。还要知道，“包含”一词在本说明书中使用时，说明存在所指出的特征、整体、步骤、操作、单元和/或组件，但是并不排除存在或增加一个或多个其它特征、整体、步骤、操作、单元和/或组件，以及/或者它们的组合。
下面的权利要求中的所有装置或步骤加功能要素的对应结构、材料、动作和等价物旨在包括用于与具体地要求保护的其他要求保护的要素组合地执行功能的任何结构、材料或动作。本发明的说明书是为了示例和说明的目的而给出的，而不旨在以所公开的形式穷举或限制本发明。只要不脱离本发明的范围和精神，多种修改和变化对于本领域的普通技术人员而言是显而易见的。为了最好地解释本发明的原理和实际应用，且为了使本领域的其他普通技术人员能够理解本发明的具有适于所预期的特定用途的各种修改的各种实施例，选择和描述了实施例。

Claims (19)

1.一种用于形成具有源极/漏极缓冲区的应力沟道场效应晶体管(FET)的方法，该方法包括：
在位于衬底上的栅极叠层的两侧在所述衬底中蚀刻腔；
在所述腔中沉积源极/漏极缓冲材料；
蚀刻所述源极/漏极缓冲材料以形成与所述FET的沟道区相邻的垂直源极/漏极缓冲区，其中所述源极/漏极缓冲区被蚀刻为，使得位于所述栅极叠层下方的所述衬底的所述沟道区在所述源极/漏极缓冲区的顶部上暴露；以及
在所述腔中与所述垂直源极/漏极缓冲区相邻地以及在所述垂直源极/漏极缓冲区上方，沉积源极/漏极应力源材料。
2.根据权利要求1的方法，其中所述衬底包括绝缘体上硅(SOI)衬底，并且其中所述腔位于所述SOI衬底的顶部硅层中。
3.根据权利要求1的方法，其中在所述衬底中蚀刻所述腔包括各向异性和各向同性反应离子蚀刻的组合以及各向异性反应离子蚀刻中的一种。
4.根据权利要求1的方法，其中所述腔被蚀刻到在所述衬底中30纳米到80纳米的深度。
5.根据权利要求1的方法，还包括在蚀刻所述腔之后对位于所述腔的底部的所述衬底的部分进行掺杂。
6.根据权利要求1的方法，其中沉积所述源极/漏极缓冲材料包括外延沉积。
7.根据权利要求1的方法，其中所沉积的所述源极/漏极缓冲材料具有5nm到15nm的厚度。
8.根据权利要求1的方法，其中在所述FET包括p型FET的情况下，所述源极/漏极缓冲材料包括未掺杂的硅锗，并且在所述FET包括n型FET的情况下，所述源极/漏极缓冲材料包括未掺杂的碳化硅。
9.根据权利要求1的方法，其中在所述FET包括p型FET的情况下，所述源极/漏极缓冲材料包括用硼轻掺杂的硅锗，并且在所述FET包括n型FET的情况下，所述源极/漏极缓冲材料包括用磷轻掺杂的碳化硅。
10.根据权利要求1的方法，其中蚀刻所述源极/漏极缓冲材料以形成所述源极/漏极缓冲区包括各向异性和各向同性蚀刻的组合以及各向异性反应离子蚀刻中的一种。
11.根据权利要求1的方法，其中所述衬底的暴露的沟道区具有在所述栅极叠层的底部下方在所述衬底中5纳米到15纳米的深度。
12.根据权利要求1的方法，其中所沉积的所述源极/漏极应力源材料在所述源极/漏极缓冲区上方与所述衬底的暴露的沟道区邻接。
13.根据权利要求1的方法，其中沉积所述源极/漏极应力源材料包括外延沉积。
14.根据权利要求1的方法，其中在所述FET包括p型FET的情况下，所述源极/漏极应力源材料包括重掺杂有硼的硅锗，并且在所述FET包括n型FET的情况下，所述源极/漏极应力源材料包括重掺杂有磷的碳化硅。
15.根据权利要求14的方法，其中所述源极/漏极应力源材料是原位掺杂的。
16.一种应力沟道场效应晶体管(FET)，包括：
衬底；
位于所述衬底上的栅极叠层；
在所述栅极叠层下方且位于所述衬底中的沟道区；
在所述沟道区的两侧且位于所述衬底中的腔内的源极/漏极应力源材料；以及
在所述源极/漏极应力源材料与所述衬底之间且位于所述衬底中的所述腔内的垂直源极/漏极缓冲区，其中所述源极/漏极应力源材料在所述源极/漏极缓冲区上方邻接所述沟道区。
17.根据权利要求16的FET，其中在所述FET包括p型FET的情况下，所述垂直源极/漏极缓冲区包括未掺杂的或轻掺杂有硼的硅锗，并且在所述FET包括n型FET的情况下，所述垂直源极/漏极缓冲区包括未掺杂的或轻掺杂有磷的碳化硅。
18.根据权利要求16的FET，其中在所述FET包括p型FET的情况下，所述源极/漏极应力源材料包括重掺杂有硼的硅锗，并且在所述FET包括n型FET的情况下，所述源极/漏极应力源材料包括重掺杂有磷的碳化硅。
19.根据权利要求16的FET，其中，下述区域具有在所述栅极叠层的底部下方5纳米到15纳米的深度：在该区域中，所述源极/漏极应力源材料在所述垂直源极/漏极缓冲区上方与所述沟道区邻接。
CN201280004994.3A 2011-01-19 2012-01-16 具有源极/漏极缓冲区的应力沟道fet Active CN103314434B (zh)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US13/009,029 2011-01-19
US13/009,029 US8361847B2 (en) 2011-01-19 2011-01-19 Stressed channel FET with source/drain buffers
PCT/US2012/021407 WO2012099808A1 (en) 2011-01-19 2012-01-16 Stressed channel fet with source/drain buffers

Publications (2)

Publication Number Publication Date
CN103314434A CN103314434A (zh) 2013-09-18
CN103314434B true CN103314434B (zh) 2016-01-20

Family

ID=46490113

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201280004994.3A Active CN103314434B (zh) 2011-01-19 2012-01-16 具有源极/漏极缓冲区的应力沟道fet

Country Status (6)

Country Link
US (2) US8361847B2 (zh)
JP (1) JP2014506726A (zh)
CN (1) CN103314434B (zh)
DE (1) DE112012000510B4 (zh)
GB (1) GB2500848B (zh)
WO (1) WO2012099808A1 (zh)

Families Citing this family (28)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102842493A (zh) * 2011-06-20 2012-12-26 中国科学院微电子研究所 一种半导体结构及其制造方法
US9246004B2 (en) * 2011-11-15 2016-01-26 Taiwan Semiconductor Manufacturing Company, Ltd. Strained structures of semiconductor devices
US9018690B2 (en) 2012-09-28 2015-04-28 Silicon Storage Technology, Inc. Split-gate memory cell with substrate stressor region, and method of making same
US8633516B1 (en) * 2012-09-28 2014-01-21 Taiwan Semiconductor Manufacturing Company, Ltd. Source/drain stack stressor for semiconductor device
CN103730363B (zh) * 2012-10-11 2016-08-03 中国科学院微电子研究所 半导体结构及其制造方法
US8841189B1 (en) 2013-06-14 2014-09-23 International Business Machines Corporation Transistor having all-around source/drain metal contact channel stressor and method to fabricate same
CN103474459B (zh) * 2013-09-06 2016-01-27 北京大学深圳研究生院 隧穿场效应晶体管
US9324841B2 (en) * 2013-10-09 2016-04-26 Globalfoundries Inc. Methods for preventing oxidation damage during FinFET fabrication
US9716176B2 (en) 2013-11-26 2017-07-25 Samsung Electronics Co., Ltd. FinFET semiconductor devices including recessed source-drain regions on a bottom semiconductor layer and methods of fabricating the same
CN104701164A (zh) * 2013-12-04 2015-06-10 中芯国际集成电路制造(上海)有限公司 半导体器件和半导体器件的制作方法
US9276113B2 (en) 2014-03-10 2016-03-01 International Business Corporation Structure and method to make strained FinFET with improved junction capacitance and low leakage
KR20150105866A (ko) * 2014-03-10 2015-09-18 삼성전자주식회사 스트레서를 갖는 반도체 소자 및 그 형성 방법
US10008568B2 (en) * 2015-03-30 2018-06-26 Taiwan Semiconductor Manufacturing Co., Ltd. Structure and formation method of semiconductor device structure
US9768254B2 (en) * 2015-07-30 2017-09-19 International Business Machines Corporation Leakage-free implantation-free ETSOI transistors
US9577038B1 (en) 2015-12-15 2017-02-21 International Business Machines Corporation Structure and method to minimize junction capacitance in nano sheets
CN108292674B (zh) * 2015-12-24 2022-05-13 英特尔公司 形成掺杂源极/漏极触点的方法及由其形成的结构
US9825157B1 (en) 2016-06-29 2017-11-21 Globalfoundries Inc. Heterojunction bipolar transistor with stress component
CN107785313B (zh) * 2016-08-26 2021-06-08 中芯国际集成电路制造(上海)有限公司 半导体结构及其形成方法
US10964796B2 (en) 2017-02-08 2021-03-30 Globalfoundries U.S. Inc. Heterojunction bipolar transistors with stress material for improved mobility
CN108417537B (zh) * 2017-02-10 2021-09-07 中芯国际集成电路制造(上海)有限公司 Sram存储器及其形成方法
CN108417489B (zh) * 2017-02-10 2020-11-27 中芯国际集成电路制造(上海)有限公司 Sram存储器及其形成方法
US10879365B2 (en) 2017-03-31 2020-12-29 Intel Corporation Transistors with non-vertical gates
US9954102B1 (en) * 2017-04-20 2018-04-24 International Business Machines Corporation Vertical field effect transistor with abrupt extensions at a bottom source/drain structure
US10263077B1 (en) * 2017-12-22 2019-04-16 Commissariat A L'energie Atomique Et Aux Energies Alternatives Method of fabricating a FET transistor having a strained channel
KR102471539B1 (ko) 2017-12-27 2022-11-25 삼성전자주식회사 반도체 장치 및 그 제조 방법
US11296225B2 (en) 2018-06-29 2022-04-05 Taiwan Semiconductor Manufacturing Company, Ltd. FinFET device and method of forming same
CN113540237A (zh) * 2020-04-14 2021-10-22 中芯国际集成电路制造(上海)有限公司 半导体结构及其形成方法
CN113380896B (zh) * 2021-05-20 2023-04-25 惠科股份有限公司 薄膜晶体管的制备方法、薄膜晶体管及显示面板

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101578690A (zh) * 2006-11-21 2009-11-11 先进微装置公司 应力增强的mos晶体管及其制造方法

Family Cites Families (27)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3454700B2 (ja) * 1998-01-20 2003-10-06 富士通株式会社 情報記憶装置及びその制御方法
US6019839A (en) * 1998-04-17 2000-02-01 Applied Materials, Inc. Method and apparatus for forming an epitaxial titanium silicide film by low pressure chemical vapor deposition
US20020048884A1 (en) * 2000-02-22 2002-04-25 Quek Shyue Fong Vertical source/drain contact semiconductor
DE10246718A1 (de) * 2002-10-07 2004-04-22 Infineon Technologies Ag Feldeffekttransistor mit lokaler Source-/Drainisolation sowie zugehöriges Herstellungsverfahren
US6921913B2 (en) 2003-03-04 2005-07-26 Taiwan Semiconductor Manufacturing Co., Ltd. Strained-channel transistor structure with lattice-mismatched zone
US7303949B2 (en) 2003-10-20 2007-12-04 International Business Machines Corporation High performance stress-enhanced MOSFETs using Si:C and SiGe epitaxial source/drain and method of manufacture
US7923782B2 (en) 2004-02-27 2011-04-12 International Business Machines Corporation Hybrid SOI/bulk semiconductor transistors
US7494885B1 (en) * 2004-04-05 2009-02-24 Advanced Micro Devices, Inc. Disposable spacer process for field effect transistor fabrication
KR100547597B1 (ko) * 2004-08-09 2006-01-31 삼성전자주식회사 리페어시 동일한 데이터 토폴로지를 갖는 오픈 비트라인셀 구조의 메모리 장치 및 그 동작 방법
US7135372B2 (en) 2004-09-09 2006-11-14 Taiwan Semiconductor Manufacturing Company, Ltd. Strained silicon device manufacturing method
US8105908B2 (en) * 2005-06-23 2012-01-31 Applied Materials, Inc. Methods for forming a transistor and modulating channel stress
DE102005052055B3 (de) 2005-10-31 2007-04-26 Advanced Micro Devices, Inc., Sunnyvale Eingebettete Verformungsschicht in dünnen SOI-Transistoren und Verfahren zur Herstellung desselben
CN1959959B (zh) 2005-10-31 2010-04-21 中芯国际集成电路制造(上海)有限公司 使用应变硅用于集成pmos和nmos晶体管的单掩模设计方法和结构
US8017487B2 (en) * 2006-04-05 2011-09-13 Globalfoundries Singapore Pte. Ltd. Method to control source/drain stressor profiles for stress engineering
US7750416B2 (en) * 2006-05-03 2010-07-06 Taiwan Semiconductor Manufacturing Company, Ltd. Modifying work function in PMOS devices by counter-doping
US7618866B2 (en) 2006-06-09 2009-11-17 International Business Machines Corporation Structure and method to form multilayer embedded stressors
US7592231B2 (en) * 2006-08-01 2009-09-22 United Microelectronics Corp. MOS transistor and fabrication thereof
US7605407B2 (en) 2006-09-06 2009-10-20 Taiwan Semiconductor Manufacturing Company, Ltd. Composite stressors with variable element atomic concentrations in MOS devices
US7554110B2 (en) 2006-09-15 2009-06-30 Taiwan Semiconductor Manufacturing Company, Ltd. MOS devices with partial stressor channel
US20080220579A1 (en) * 2007-03-07 2008-09-11 Advanced Micro Devices, Inc. Stress enhanced mos transistor and methods for its fabrication
US7759199B2 (en) 2007-09-19 2010-07-20 Asm America, Inc. Stressor for engineered strain on channel
JP5410012B2 (ja) * 2007-09-28 2014-02-05 ローム株式会社 半導体装置
JP2009111046A (ja) * 2007-10-29 2009-05-21 Sony Corp 半導体装置および半導体装置の製造方法
KR101107204B1 (ko) * 2008-12-29 2012-01-25 주식회사 하이닉스반도체 반도체 소자의 트랜지스터 형성 방법
DE102009006884B4 (de) * 2009-01-30 2011-06-30 Advanced Micro Devices, Inc., Calif. Verfahren zur Herstellung eines Transistorbauelementes mit In-Situ erzeugten Drain- und Source-Gebieten mit einer verformungsinduzierenden Legierung und einem graduell variierenden Dotierstoffprofil und entsprechendes Transistorbauelement
WO2010086154A1 (en) * 2009-01-30 2010-08-05 5Advanced Micro Devices, Inc In situ formed drain and source regions including a strain inducing alloy and a graded dopant profile
JP2010219152A (ja) * 2009-03-13 2010-09-30 Toshiba Corp 半導体装置およびその製造方法

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101578690A (zh) * 2006-11-21 2009-11-11 先进微装置公司 应力增强的mos晶体管及其制造方法

Also Published As

Publication number Publication date
WO2012099808A1 (en) 2012-07-26
GB2500848A (en) 2013-10-02
US8921939B2 (en) 2014-12-30
US8361847B2 (en) 2013-01-29
CN103314434A (zh) 2013-09-18
GB201312793D0 (en) 2013-08-28
DE112012000510B4 (de) 2014-06-18
GB2500848B (en) 2014-10-22
US20130140636A1 (en) 2013-06-06
JP2014506726A (ja) 2014-03-17
US20120181549A1 (en) 2012-07-19
DE112012000510T5 (de) 2013-12-05

Similar Documents

Publication Publication Date Title
CN103314434B (zh) 具有源极/漏极缓冲区的应力沟道fet
US9761722B1 (en) Isolation of bulk FET devices with embedded stressors
US8828813B2 (en) Replacement channels
US8445334B1 (en) SOI FinFET with recessed merged Fins and liner for enhanced stress coupling
US9105662B1 (en) Method and structure to enhance gate induced strain effect in multigate device
US8729638B2 (en) Method for making FINFETs and semiconductor structures formed therefrom
US8728885B1 (en) Methods of forming a three-dimensional semiconductor device with a nanowire channel structure
US8872172B2 (en) Embedded source/drains with epitaxial oxide underlayer
US20080048217A1 (en) Semiconductor device and method of fabricating the same
CN103632973B (zh) 半导体器件及其制造方法
US8441045B2 (en) Semiconductor device and method for manufacturing the same
CN102931232B (zh) Nmos晶体管及其形成方法
US20140374807A1 (en) METHOD OF DEVICE ISOLATION IN CLADDING Si THROUGH IN SITU DOPING
US8816392B2 (en) Semiconductor device having gate structures to reduce the short channel effects
CN103779229A (zh) 半导体结构及其制造方法
US9666717B2 (en) Split well zero threshold voltage field effect transistor for integrated circuits
US10644103B2 (en) Semiconductor devices having charged punch-through stopper layer to reduce punch-through and methods of manufacturing the same
US9362400B1 (en) Semiconductor device including dielectrically isolated finFETs and buried stressor
CN104916540A (zh) 一种应变沟道晶体管及其制备方法
TW201431007A (zh) 半導體裝置結構及形成互補式金屬氧化物半導體積體電路結構之方法
US9059291B2 (en) Semiconductor-on-insulator device including stand-alone well implant to provide junction butting
US8969164B2 (en) Semiconductor structure and method for manufacturing the same
CN102856376B (zh) 一种半导体结构及其制造方法
CN102856375B (zh) 一种半导体结构及其制造方法
CN104465752A (zh) Nmos晶体管结构及其制造方法

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant
TR01 Transfer of patent right
TR01 Transfer of patent right

Effective date of registration: 20171102

Address after: Grand Cayman, Cayman Islands

Patentee after: GLOBALFOUNDRIES INC.

Address before: American New York

Patentee before: Core USA second LLC

Effective date of registration: 20171102

Address after: American New York

Patentee after: Core USA second LLC

Address before: American New York

Patentee before: International Business Machines Corp.