CN101233606A - 用于制造受应力的mos器件的方法 - Google Patents

用于制造受应力的mos器件的方法 Download PDF

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CN101233606A
CN101233606A CNA2006800283979A CN200680028397A CN101233606A CN 101233606 A CN101233606 A CN 101233606A CN A2006800283979 A CNA2006800283979 A CN A2006800283979A CN 200680028397 A CN200680028397 A CN 200680028397A CN 101233606 A CN101233606 A CN 101233606A
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stress
crystal semiconductor
semiconductor substrate
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CN101233606B (zh
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I·佩多斯
M·M·佩莱拉
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GlobalFoundries US Inc
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    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
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    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66613—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation
    • H01L29/66628—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation recessing the gate by forming single crystalline semiconductor material at the source or drain location
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    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
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    • H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
    • H01L29/7848—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate the means being located in the source/drain region, e.g. SiGe source and drain
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    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/938—Lattice strain control or utilization

Abstract

本发明提供一种在半导体衬底中和上制造受应力之MOS器件(stressed MOS device)(30)之方法。该方法包括下列步骤：形成覆于半导体衬底上之栅电极(gate electrode)(66)，以及于该半导体衬底(36)中刻蚀第一沟槽(82)和第二沟槽(84)，该第一沟槽和第二沟槽形成为对准于该栅电极(66)。选择性地生长应力引发材料(stress inducing material)(90)于第一沟槽和第二沟槽中，并将导电率判定杂质离子植入于应力引发材料(90)中以在该第一沟槽(82)中形成源极区域(92)和在该第二沟槽(84)中形成漏极区域(94)。于该离子植入步骤后，沉积机械硬材料层(96)在该应力引发材料上以维持于衬底中引发之应力。

Description

用于制造受应力的MOS器件的方法
技术领域
本发明大体上系关于制造受应力之MOS器件之方法，且详言之，系关于制造受应力之MOS器件并维持该应力和应力引发增加于此等器件中之方法。
背景技术
多数之现代集成电路(IC)，系藉由使用复数个互连之场效晶体管(FET)(亦称之为金属氧化物半导体场效晶体管或简称MOS晶体管)而实施。MOS晶体管包括栅电极作为控制电极、以及分隔开之源极和漏极而于该源极和漏极间能流过电流。施加到该栅电极之控制电压控制流经该源极和漏极之间沟道之电流。
MOS晶体管，相对于双极(bipolar)晶体管，而为多数载子器件(majority carrier device)。MOS晶体管之增益(gain)，其通常由互导(transconductance)(gm)所定义，系正比于晶体管沟道中多数载子之移动率(mobility)。MOS晶体管之电流载送能力系正比于沟道中多数载子之移动率。可藉由施加压缩之纵向应力于沟道而增加于P沟道MOS晶体管中多数载子(电洞)的移动率。可藉由施加伸张之横向应力于沟道而增加于N沟道MOS晶体管中多数载子(电子)的移动率。于硅MOS晶体管中，能藉由适当地埋置譬如SiGe之应力引发材料于晶体管之硅衬底中而施加此等应力于MOS晶体管之沟道。该等应力系由于SiGe和主硅材料之间的晶格不匹配而引起。于SiGe中固有的应力再分配入主衬底之邻近区域中，也就是再分配入MOS晶体管之沟道区域中。不幸的是，埋置之SiGe技术之其中一个问题是SiGe层的机械稳定性。在升高的温度，由于错位(dislocation)产生而使于SiGe层中的固有应力松弛(relax)。转而，应力的减少造成应力引发移动率增加的减少，因此恶化器件效能。
因此希望提供制造防止应力松弛之受应力之MOS器件之方法。再者，由后续之详细说明和所附之权利要求，结合伴随之图式和上述技术领域和先前技术，本发明之其它希望之特征和特性将变得清楚。
发明内容
本发明提供一种在半导体衬底中和上制造受应力之MOS器件之方法。该方法包括下列步骤：形成覆于半导体衬底上之栅电极，以及于该半导体衬底中刻蚀第一沟槽和第二沟槽，该第一沟槽和第二沟槽形成为对准于该栅电极。选择性地生长应力引发材料于第一沟槽和第二沟槽中，并将导电率判定杂质离子植入于应力引发材料中以在该第一沟槽中形成源极区域和在该第二沟槽中形成漏极区域。于该离子植入步骤后，沉积机械硬材料层覆于该应力引发材料上以维持于衬底中引发之应力。
附图说明
以上结合下列图式而说明本发明，其中相似的组件符号表示相似的组件，以及其中：
，图1至6示意地显示依照本发明之各种实施例之受应力之MOS器件及其制造方法之剖面图。
具体实施方式
下列之详细说明仅为例示性质，并不意欲限制本发明或本发明之应用和使用。再者，并不意欲由呈现于前面技术领域、先前技术、发明内容或下列详细说明中所表示或暗示之任何理论而限定本发明。
第1至6图显示依照本发明之各种实施例之受应力之MOS器件30及制造此种MOS器件之方法步骤。于此例示实施例中，受应力之MOS器件30由单一P沟道MOS晶体管而予例示。从譬如器件30之受应力之MOS器件所形成之集成电路能包括大量之此等晶体管，且亦可包括未受应力之P沟道MOS晶体管及受应力和未受应力之N沟道MOS晶体管。
于制造MOS晶体管之各种步骤为已知，因此为了简洁之目的，许多习知的步骤于此将仅简短描述、或将其整个省略而不提供已知制程之细节。虽然术语“MOS器件”适当地指为具有金属栅电极和氧化物栅极绝缘体之器件，但是该术语将用于全文中指任何包括位于栅极绝缘体(不管是否为氧化物或其它的绝缘体)之上之导电栅电极(不管是否为金属或其它的导电材料)半导体器件，该栅极绝缘体遂位于半导体衬底之上。
如图1中所显示，依照本发明之实施例之受应力之MOS器件30之制造开始于提供半导体衬底36。半导体衬底较佳是单晶硅衬底，其中此处所用之术语“硅衬底”包含了一般用于半导体工业之相对纯之硅材料。此处半导体衬底36将可替代地称为硅衬底或为半导体衬底，其系为了容易讨论而不作为限制。硅衬底36可以是大块(bulk)硅芯片、或是于绝缘层上之硅薄层(通常已知为绝缘体上覆硅(silicon-on-insulator或SOI)，该绝缘层遂由硅载体芯片所支持，但是此处所显示为大块硅芯片，而没有限制。较佳的情况是，硅芯片具有(100)或(110)方向(orientation)，以及至少芯片之其中将要制造MOS器件30之部分用N型杂质掺杂物掺杂(例如，N井(well))。N井能例如藉由离子植入而掺杂至适当的导电率(conductivity)。形成浅沟槽隔离(STI)(未图标)于半导体衬底中以电性隔离个别之器件，如者所执行的电路功能所需。如已知的，有许多方法可用来形成STI，因此此处不须详细描述该方法。一般而言，STI包括刻蚀入半导体衬底之表面中之浅沟槽，接着用绝缘材料填充该浅沟槽。于浅沟槽填充有绝缘材料后，该表面通常被平坦化，例如，藉由化学机械平坦法(CMP)。
栅极绝缘体层60形成在硅衬底36之表面。栅极绝缘体可以是藉由在氧化环境中加热硅衬底而形成之热生长二氧化硅、或者可以是譬如氧化硅、氮化硅、例如HfSiO之高介电常数绝缘体、等等之沉积之绝缘体。可藉由化学气相沉积(CVD)、低压化学气相沉积(LPCVD)、或电浆增强型化学气相沉积(PECVD)来沉积沉积之绝缘体。栅极绝缘体材料典型为1至10奈米(nm)厚度。依照本发明之一个实施例，沉积多晶硅层62于栅极绝缘体层上。该多晶硅层较佳沉积为未掺杂之多晶硅，且后续藉由离子植入而被杂质掺杂。譬如氧化硅、氮化硅、或氧氮化硅之硬掩模材料层64能沉积在多晶硅之表面上。多晶硅材料能藉由减少氢之硅烷(silane)之LPCVD而沉积至大约100nm之厚度。硬掩模材料亦能藉由LPCVD而沉积至大约50nm之厚度。
硬掩模层64和下方多晶硅层62被光微影图案化以形成P沟道MOS晶体管栅电极66，如图2中所示。栅电极66覆于将形成P沟道MOS晶体管30之沟道68之半导体衬底36之部分上。能藉由例如于Cl或HBr/O2化学中之电浆刻蚀而刻蚀多晶硅于所希望之图案，以及能藉由例如于CHF3、CHF4、或SF6化学中之电浆刻蚀而刻蚀硬掩模。依照本发明之一个实施例，于图案化栅电极之后，接着藉由于氧化环境中加热多晶硅而热生长氧化硅薄层70于栅电极66之相对侧壁72上。层70能生长至大约2至5nm之厚度。栅电极66和层70能使用为离子植入掩模以形成MOS晶体管之源极和漏极延伸区(未显示)。对于形成多个源极和漏极区域之可能需要条件和方法为已知，但与本发明并没有密切关系，因此于此处无需说明。
依照本发明之一个实施例，如图3中所显示，侧壁间隔件80形成在栅电极66之相对侧壁72上。此侧壁间隔件能藉由沉积一层氮化硅、氧化硅、等等之间隔件材料于栅电极之上、并接着藉由例如反应性离子刻蚀来非等向性刻蚀该层而形成。侧壁间隔件80、栅电极66、及于该栅电极之顶部上之硬掩模用作为刻蚀掩模来刻蚀于硅衬底中由P沟道栅电极66间隔开并自行对准于该P沟道栅电极66之沟槽82和84。该等沟槽相交于沟道68之端部。该等沟槽能藉由例如用Cl或HBr/O2化学之电浆刻蚀来刻蚀。较佳的情况是，各沟槽具有深度为大约0.04至0.2μm。
如图4中所例示，用应力引发材料层90填充沟槽。该应力引发材料可以是能够生长于具有与硅之晶格常数不同之晶格常数之硅衬底上之任何的单晶材料。二种并置之材料之晶格常数差异产生在该二种材料之间接口处之应力，该应力再分配于主材料中。较佳的情况是，应力引发材料引起硅主体(silicon host)弹性地变形，使得硅受应力，但是维持着实质上无缺陷完美结晶。缺陷能引起应力之减少或减缓。应力引发材料能够是例如具有大约10至25原子百分比之锗之单晶硅锗(SiGe)、或者是含有大约1至4原子百分比之代替的碳和较佳是少于大约2原子百分之代替的碳之单晶硅。较佳的情况是藉由选择性生长制程而外延生长应力引发材料。以选择性方式外延生长这些材料于硅主体上之方法为已知，而于此处无须说明。例如，于SiGe之情况，SiGe具有较硅之晶格常数为大之晶格常数，且此情况造成于晶体管沟道68中之压缩之纵向应力。压缩之纵向应力增加沟道68中电洞之移动率，而因此增进P沟道MOS晶体管之效能。
于应力引发材料生长于沟槽82和84后，接着将P型导电率决定离子植入于应力引发材料中(如由箭号86所指示)以形成P沟道MOS晶体管30之源极区域92和漏极区域94，如图5中所示。欲变成电性主动的(electrically active)，对植入之离子必须进行退火，而此种退火通常于完成植入后立刻执行。然而，升高的温度引起于SiGe或其它的应力引发材料中固有的应力松弛，这是由于在表面上集结(nucleate)之错位产生和于SiGe之表面处产生梯阶(step)之关系。
依照本发明之实施例，如图6中所示，藉由沉积具有高机械强度之层96于应力引发材料之表面上而防止于沟道68中应力的松弛。高机械强度之层延缓梯阶形成(step formation)并防止错位集结和传播于应力引发材料之表面处。于离子植入之退火或任何其它高温步骤之前，敷设高机械强度之层。敷设层96之后，器件能经受高温且将维持应力。层96可以是能够沉积于相对低温且具有杨氏模量(Young’s modulus)大于而较佳是远大于应力引发材料之杨氏模量。举例而言，用于具有杨氏模量大约为150GPa之SiGe，氮化硅(杨氏模量大约350GPa)、碳化硅(杨氏模量介于大约400与750Gpa之间)和钻石状碳(杨氏模量高达800GPa)为适用于层96之材料。如此处所使用者，低温系指低于大约600℃之任何温度，而高温系指高于大约900℃之任何温度。能藉由CVD、LPCVD、或PECVD而沉积层96。例如，能藉由PECVD于大约450℃温度藉由二氯硅烷和氨之电浆增强反应而沉积氮化硅层。类似情况，能藉由使用气相SiCl4和甲烷于550℃而沉积碳化硅，以及能使用Ar、H2、SiH4和C2H2之混合气体于200℃而沉积PECVD钻石状碳。依照本发明之替代实施例(未图标)，首先在高机械强度之层96下方提供具有厚度例如2至5nm之垫氧化物层可能是有利的。该垫氧化物层用来防止例如在氮化硅和下方半导体材料之间的任何反应。
能够藉由已知的步骤(未显示)，譬如在层96之上沉积介电质材料层、刻蚀开口穿过该介电质材料和层96以暴露出源极和漏极区域之部分、以及形成延伸穿过开口以与该源极和漏极区域电性接触之金属化(metallization)，而完成受应力之MOS器件30。进一步之层间介电质材料层、额外之互连金属化层、等等亦可应用并图案化以达成所执行集成电路之适当的电路功能。
虽然于本发明之上述详细说明中已呈现了至少一个实施范例，但是应该了解到存在有许多之变化。亦应该了解到实施范例或诸实施范例仅是作实例用，并不意欲限制本发明之范围、应用、或配置于任何方式。确切地说，以上之详细说明将提供熟悉此项技术者施行该实施范例或诸实施范例之方便的路途指引。应了解到在功能和组件的配置可以作各种之改变而不脱离本发明提出于所附权利要求中及其合法均等之范围。

Claims (10)

1.一种于半导体衬底(36)中和半导体衬底(36)上制造受应力的MOS器件(30)的方法，包括下列步骤：
形成栅电极(66)覆于所述半导体衬底(36)上；
于所述半导体衬底中刻蚀刻蚀第一沟槽(82)和第二沟槽(84)，所述第一沟槽和第二沟槽与所述栅电极(66)形成队列；
于所述第一沟槽(82)和所述第二沟槽(84)中选择性地生长应力引发材料(90)；
离子注入导电率决定掺杂离子于所述应力引发材料(90)中以于所述第一沟槽(82)中形成源极区域(92)及于所述第二沟槽(84)中形成漏极区域(94)；以及
于所述注入步骤后形成机械硬材料(96)层覆于所述应力引发材料(90)上。
2.如权利要求1所述的方法，其中所述选择性地生长步骤包括外延生长单晶SiGe层的步骤。
3.如权利要求2所述的方法，其中，形成机械硬材料(96)层的所述步骤包括沉积具有杨氏模量大于单晶SiGe的杨氏模量的材料层的步骤。
4.如权利要求1所述的方法，其中，形成机械硬材料(96)层的所述步骤包括在任何包含加热至温度大于大约600℃的步骤前，沉积机械硬材料层和进行离子注入。
5.如权利要求1所述的方法，其中，选择性地生长应力引发材料(90)的所述步骤包括选择性地生长具有第一杨氏模量为特征的应力引发材料的步骤，以及其中形成机械硬材料(96)层的所述步骤包括以形成具有较所述第一杨氏模量更大的第二杨氏模量为特征的机械硬材料(96)层的步骤。
6.如权利要求1所述的方法，其中，形成机械硬材料(96)层的所述步骤包括形成从氮化硅、碳化硅、和钻石状碳所组成的群选出的材料的层的步骤。
7.一种制造受应力的MOS器件(30)的方法，包括下列步骤：
提供单晶半导体衬底(36)；
刻蚀沟槽(82)进入所述单晶半导体衬底中；
用晶格不匹配所述单晶半导体衬底(36)的单晶半导体材料(90)选择性地填充所述沟槽(82)，所述单晶半导体材料(90)具有第一杨氏模量；以及
沉积具有大于所述第一杨氏模量的第二杨氏模量的材料(96)的膜而与所述单晶半导体材料(90)接触，沉积材料(96)的膜的所述步骤发生于所述单晶半导体材料被加热至温度大于大约600℃以前。
8.如权利要求7所述的方法，其中，提供单晶衬底(36)的所述步骤包括提供单晶硅衬底的步骤，以及选择性地填充所述沟槽的所述步骤包括用选自由单晶SiGe和含有至少2％碳的单晶硅所组成的群的单晶材料(90)来选择性地填充所述沟槽的步骤。
9.一种制造受应力的MOS器件(30)的方法，包括下列步骤：
提供单晶半导体衬底(36)；
通过外延生长应力引发单晶半导体材料(90)于所述单晶半导体衬底(36)上而于所述单晶半导体衬底中产生应力状况，所述应力引发单晶半导体材料(90)具有与所述单晶半导体衬底(36)不匹配的晶格；以及
在所述应力引发单晶半导体材料(90)受到超过大约900℃的温度以前，通过沉积机械硬材料(96)的膜于所述应力引发单晶半导体材料(90)上而维持于所述单晶半导体衬底(36)中的应力状况。
10.如权利要求9所述的方法，其中，维持所述应力的步骤包括沉积选自由氮化硅、碳化硅、和钻石状碳所组成的群的材料(96)的层的步骤。
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