CN104752351B - 半导体器件的形成方法 - Google Patents
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Abstract
一种半导体器件的形成方法,包括:提供衬底,并在所述衬底上形成若干栅极结构;在所述栅极结构两侧的衬底中形成沟槽;在所述栅极结构两侧的沟槽中填充用于形成源区或漏区的应力层,所述应力层凸出所述衬底;对所述应力层进行脉冲刻蚀,使所述应力层与所述衬底相互齐平。本发明的技术方案具有以下优点:在形成应力层后,通过对所述应力层进行脉冲刻蚀,使半导体器件中的应力层的过量填充的部分能够尽量被去除;所述脉冲刻蚀能够调节对同一晶圆上不同尺寸的应力层的刻蚀量,从而使高出衬底表面不同高度的应力层被刻蚀的量不同,进而使这些应力层的高度尽量都与衬底表面相互齐平。
Description
技术领域
本发明涉及半导体制造领域。具体涉及一种半导体器件的形成方法。
背景技术
现有的CMOS器件制造中,通常在源漏区的制造中采用应变硅技术,这种技术可以通过物理方法拉伸或是压缩源区或者漏区中的硅的晶格,从而对沟道区提供应力作用,进而提升CMOS器件中沟槽载流子迁移率,进而达到提高CMOS器件电学性能的目的。
在现有的形成CMOS器件的过程中,往往先在衬底上形成栅极结构,然后在栅极结构两侧的衬底中形成沟槽,然后在沟槽中填充应力层,所述应力层在经过掺杂等处理后形成源区或者漏区。但是,现有制作所述源区或者漏区的方法可能会使应力层发生过量填充(over-fill)的现象,也就是说,在所述的沟槽中形成应力层后,应力层的表面高出衬底表面。
一方面,这种现象会导致衬底表面变得不平整进而妨碍到后续的制造步骤的进行,另一方面,过量填充现象还可能会影响到应力层中的应力分布,导致应力层本应产生的应力减弱甚至消失,进而影响整个CMOS器件的性能。
为了克服上述问题,现有的技术趋向于通过刻蚀的方式去除形成的应力层高出衬底的部分,也就是过量填充的部分。
但是,由于在同一片晶圆(wafer)上不同的CMOS器件之间的尺寸可能不同,相应的,这些不同尺寸的CMOS器件中的沟槽的距离或者节距(pitch)也不同。在发生所述的过量填充(over-fill)现象时,在这些不同尺寸的沟槽中形成的应力层高出衬底的表面的高度也可能不同,也就是说,现有技术在克服所述过量填充现象的时候,对于同一片晶圆上的不同尺寸的CMOS器件,要刻蚀掉的应力层的厚度可能不一样,进而导致刻蚀过程难以控制。
所以,以现有的方式对发生了过量填充的应力层的超出衬底的部分进行刻蚀,很容易造成刻蚀后这些不同储存的CMOS器件的应力层相对于衬底表面的高度仍旧不一样,例如,晶圆上一部分CMOS器件的应力层已经被刻蚀至理想的高度,也就是基本与衬底表面齐平,而晶圆另一区域中的其它尺寸的CMOS器件中的应力层可能因刻蚀程度不够而仍旧高出衬底,或者是相反的受到过多的刻蚀而低于衬底表面。
因此,如何控制对应力层的刻蚀,以尽量去除应力层上的过量填充的部分,使经过刻蚀后的原本高出衬底程度不同的应力层均能够与衬底基本齐平,也就是经过刻蚀后的不同尺寸的应力层相对于衬底表面的高度趋于一致,成为本领域技术人员亟待解决的技术问题。
发明内容
本发明解决的问题是提供一种半导体器件的形成方法,使得同一晶圆上不同区域、不同尺寸的半导体器件中形成的应力层相对于衬底的高度基本相同。
为解决上述问题,本发明提供一种半导体器件的形成方法,包括:
提供衬底,并在所述衬底上形成若干栅极结构;
在所述栅极结构两侧的衬底中形成沟槽;
在所述栅极结构两侧的沟槽中填充用于形成源区或漏区的应力层,所述应力层凸出所述衬底;
对所述应力层进行离子掺杂以形成源区以及漏区;
对所述源区以及漏区进行脉冲刻蚀,使所述源区以及漏区与所述衬底相互齐平。
可选的,在衬底中形成若干沟槽的步骤中,使所述沟槽呈∑型;
在形成应力层的步骤中,所述应力层的材料为锗硅。
可选的,在衬底中形成若干沟槽的步骤中,使所述沟槽呈U型;
在形成应力层的步骤中,所述应力层的材料为碳化硅。
可选的,在形成应力层的步骤中,采用外延生长的方式,在所述沟槽中形成所述应力层。
可选的,在离子掺杂的步骤之后,进行脉冲刻蚀之前还包括以下步骤:
对形成的源区以及漏区进行退火。
可选的,在形成应力层的步骤之后,等离子刻蚀的步骤之前,还包括以下步骤:在所述衬底、栅极上形成掩模,并使所述应力层暴露出。
可选的,等离子刻蚀的步骤包括:使刻蚀气体中包括三氟化氯、溴化氢或者氯气。
可选的,使所述等离子刻蚀腔体的气压在10~200毫托的范围内,所述刻蚀设备的功率输出范围在100~2000瓦的范围,偏置功率的范围在0~500瓦的范围,功率输出的脉冲频率在100~10000赫兹的范围内,占空比在90%~0%的范围内。
可选的,所述等离子刻蚀的刻蚀气体中包括溴化氢、氧气以及保护气体。
可选的,溴化氢的流量在50~1000标准毫升每分钟的范围内,氧气的流量在1~50标准毫升每分钟的范围内,保护气体包括氦气以及氩气,氦气的流量在10~500标准毫升每分钟的范围内,氩气的流量在0~500标准毫升每分钟的范围内。
与现有技术相比,本发明的技术方案具有以下优点:
在形成应力层后,通过对所述应力层进行脉冲刻蚀,使半导体器件中的应力层的过量填充的部分能够尽量被去除;所述脉冲刻蚀能够调节对同一晶圆上不同尺寸的应力层的刻蚀量,从而使高出衬底表面不同高度的应力层被刻蚀的量不同,进而使这些应力层的高度尽量都与衬底表面相互齐平。
附图说明
图1是本发明半导体器件的形成方法在一实施例的流程示意图;
图2a以及图3b是图1中各个步骤的半导体器件的结构示意图;
图4为图1中步骤S6脉冲刻蚀中脉冲功率输出方式的示意图。
具体实施方式
在半导体器件的制造过程中可能使源区或是漏区在所述沟槽内过量填充,进而高出衬底;且源区或者漏区凸出衬底的高度也不同。
以CMOS器件为例,现有的做法是在形成所述源区以及漏区后,将凸出衬底的一部分源区或者漏区,也就是源区以及漏区过量填充的部分通过刻蚀的方式去除。但是,由于同一晶圆上的不同的CMOS器件的沟槽的尺寸或者节距可能不同,相应的,在形成应力层后,刻蚀的工艺窗口的尺寸或者节距也不尽相同,所以对这些不同尺寸或者节距的应力层的刻蚀速率也会有差异,导致难以控制对于应力层的刻蚀量。
为此,本发明提供一种半导体器件的形成方法,通过使刻蚀设备产生脉冲输出的功率,以间断的方式对半导体器件的应力层高出衬底的部分进行等离子刻蚀,使各个半导体器件中形成的应力层尽量与能够衬底表面相齐平。
参见图1为本发明在一实施例中的流程示意图,本实施例包括以下步骤:
步骤S1,提供衬底,并在所述衬底上形成若干栅极结构;
步骤S2,在所述栅极结构两侧的衬底中形成沟槽;
步骤S3,在所述栅极结构两侧的沟槽中填充用于形成源区或漏区的应力层,所述应力层凸出所述衬底;
步骤S4,对所述应力层进行离子掺杂以分别形成源区以及漏区;
步骤S5,对掺杂后的源区以及漏区进行退火;
步骤S6,对所述源区以及漏区进行脉冲刻蚀,使所述源区以及漏区与所述衬底相互齐平。
通过上述步骤,使半导体器件中的应力层的过量填充的部分能够尽量被去除,脉冲刻蚀能够调节对同一晶圆上不同尺寸的应力层的刻蚀量,从而使高出衬底表面不同高度的应力层被刻蚀的量不同,进而使这些应力层的高度尽量都与衬底表面相互齐平。
为使本发明的上述目的、特征和优点能够更为明显易懂,下面结合附图对本发明的具体实施例作详细的说明。
参考图2a以及图2b,图2a与图2b为同一晶圆上不同位置的两个CMOS器件的一部分,执行步骤S1,提供衬底100,本实施例中,所述衬底100为硅衬底。
在所述衬底100上形成若干栅极结构,包括本图2a以及图2b中分别示出的栅极结构110、140以及栅极结构210、240。
所述的栅极110、140与栅极210、240可以是尺寸不同的栅极,这些尺寸不同的栅极用于形成尺寸不同的CMOS器件。栅极110、140之间以及栅极210、240之间的距离也用于定义后续步骤中在衬底100中形成的沟槽的尺寸。
形成栅极结构110以及210的方法为本领域常用技术手段,本发明在此不作赘述。另外,所述栅极结构110以及210可以采用多晶硅(poly-Si)或者金属等材料形成,且栅极结构110以及210还可能包括栅介质层或者侧墙,本发明对此不作任何限制。
继续执行步骤S2,在所述栅极结构110以及栅极结构210两侧的衬底中形成沟槽;所述沟槽用于在后续的步骤中形成应力层。具体的,所述沟槽的尺寸或者节距定义了后续形成的源区以及漏区的尺寸或者节距。由于之前的步骤中形成的所述栅极结构110以及210之间的尺寸可以不相同,相应的,在这些栅极110以及210的两侧形成的沟槽的尺寸或者节距也可以是不同的。
在本实施例中,所述半导体器件为N型晶体管,所以所述沟槽采用U型沟槽。所述U型沟槽用于在后续的步骤中填充碳化硅材料的应力层,所述碳化硅材料的应力层用于向N型晶体管的沟道区提供拉伸应力。
需要说明的是,本发明对此不作限制,在本发明也可以用于P型晶体管,相应的沟槽将呈∑型,且所述∑型沟槽中形成应力层的材料为锗硅。
在本步骤中,采用外延生长的方式形成上述的应力层。
继续参考图2a以及图2b,执行步骤S3,在所述沟槽中填充用于形成源区或漏区的应力层,所述应力层因发生了过量填充现象而凸出所述衬底100的表面,其原因通常是由于应力层一般为通过外延生长的方式形成于所述沟槽中,而由于半导体尺寸的减小,沟槽的尺寸或者节距也相应的减小,使应力层的外延生长变得难以控制而高出衬底表面。
另外,由于沟槽的尺寸或者节距不同,外延生长的速率也不同,在发生过量填充现象后,不同尺寸或者节距的沟槽中的应力层发生过量填充现象的程度也不同。
所以,在本实施例中,图2a中的应力层凸出衬底100的高度为h1,图2b中的应力层凸出衬底100的高度为h2。需要说明的是,虽然图2a和图2b中示出的高度h1小于高度h2,但是不应以此限制本发明,所述高度h1与高度h2可能相等,也可能是高度h1大于高度h2,本发明不作限定。
执行步骤S4,对图2a以及2b中的应力层进行离子掺杂以分别形成源区120、漏区130以及源区220、漏区230;本步骤S4的离子掺杂为本领域形成源区、漏区的常用技术手段,本发明对此不做赘述,也不做限定。
继续执行步骤S5,对所述源区120、漏区130以及源区220、漏区230材进行退火。
退火步骤一方面可以激活源区220、漏区230中的掺杂离子,另一方面可以使应力层保持对沟道区产生的应力。由于本实施例中,所述衬底为硅衬底,在U型沟槽中形成碳化硅的应力层,所以经过本步骤S5退火后应力层可以为源区120、漏区130之间的沟道区提供拉应力。
参考图3a以及3b,执行步骤S6,对所述源区120以及漏区130进行脉冲刻蚀,使所述源区120、漏区130以及源区220、漏区230与所述衬底100相互齐平。所述脉冲刻蚀指的是使刻蚀设备的输出功率呈脉冲式输出,也就是说,在整个刻蚀过程中,刻蚀一段时间,之后停止刻蚀一段时间,再之后继续刻蚀一段时间,再停止……反复循环一定次数,以实现间断地进行刻蚀的效果。
参考图4,为本实施例中刻蚀设备产生脉冲输出的功率的示意图,其中横坐标为刻蚀的时间,纵坐标为刻蚀设备的输出功率,从本图4中可以看出,刻蚀设备以脉冲的方式进行功率的输出,也就是说,刻蚀设备以间断地、不连续的方式激发刻蚀气体以对上述的源区120、漏区130以及源区220、漏区230凸出衬底100的部分进行刻蚀。
在本实施例中,使刻蚀设备输出功率的峰值为500瓦,刻蚀设备一开始的输出功率为500瓦,当到了t1时,刻蚀设备输出功率降至0,在下一时刻t2时,刻蚀设备输出功率再次回升至峰值500瓦,0~t2为一个脉冲周期。也就是说,刻蚀设备在0~t1时间内处于工作状态,而在t1~t2时间内处于待机状态。
这样的好处在于,一方面,当出现如本实施例所述的源区120、漏区130高出衬底100的高度h1以及源区220、漏区230高出衬底100的高度h2不同,且源区120、漏区130与源区220、漏区230的尺寸不同,也就是刻蚀过程中的刻蚀面积不同的情况下,采用本发明的等离子刻蚀方式也能够使得所述源区120、漏区130以及源区220、漏区230均基本与所述衬底100相齐平。
具体来说,在通常情况下刻蚀面积的大小会对等离子刻蚀的刻蚀速率造成影响,其原因在于在进行等离子刻蚀的过程中,刻蚀气体与被刻蚀材料之间进行反应生成阻碍刻蚀进行的聚合物(polymer),这些聚合物通常呈气相,而所述聚合物在刻蚀面积不同时的聚集程度不同,聚合物聚集程度较高,则对刻蚀的阻碍较大,刻蚀速率也较慢;聚合物聚集程度较低,则对刻蚀的阻碍较小,刻蚀速率也较快。
结合参考图2a以及图2b,其中,图2a中的栅极110以及140之间的距离较大,开口较大,所形成的源区、漏区的尺寸也较大,刻蚀面积也较大,形成的聚合物比较容易散开,所以聚合物聚集程度较低,相应的,刻蚀速率也相对较快;反之,图2b中的栅极210以及240之间的距离较小,聚合物不容易散开,也就是说聚合物聚集程度较高,所以刻蚀速率相对较慢。
在本发明中,当所述高度h1与高度h2相等时,由于栅极110、140之间的距离与栅极210、240之间的距离不同,形成的源区120、漏区130与源区220、漏区230的尺寸也不同,源区120、漏区130与源区220、漏区230上方的开口尺寸也不同,也就是说,刻蚀面积不同。通过所述脉冲刻蚀,刻蚀设备产生脉冲形式的输出的功率,使刻蚀过程以间断的,非连续的方式进行,在刻蚀一定时间段后将停止刻蚀,此时刻蚀设备暂时停止激发刻蚀气体,使得已经产生在刻蚀表面的聚合物能够有时间离开刻蚀表面,从而降低了聚合物的聚集程度,减小对刻蚀速率的阻碍。然后再进行下一周期的刻蚀,进而使刻蚀面积不同的源区120、漏区130与源区220、漏区230的刻蚀速率基本保持一致,刻蚀后的源区120、漏区130与源区220、漏区230与衬底100相齐平。
同样的,当所述高度h1小于高度h2时,通过脉冲刻蚀可以使源区220、漏区230的刻蚀速率高于源区120、漏区130,使得刻蚀后的源区120、漏区130与源区220、漏区230与衬底100相齐平。同理,当所述高度h1大于或者小于高度h2时,通过调整蚀刻设备输出的脉冲功率、占空比等,也可以使源区120、漏区130与源区220、漏区230的刻蚀速率不同,进而使得刻蚀后的源区120、漏区130与源区220、漏区230均与衬底100相齐平。
在本实施例中,在等离子刻蚀开始之前,先在半导体器件上覆盖刻蚀掩模,并将源区、漏区的部分露出,以避免对半导体器件的其它部分造成影响。
由于本实施的源区、漏区的为材料碳化硅,所以,刻蚀气体中包括三氟化氯、溴化氢或者氯气。但是,本发明对此不做限定,当源区、漏区为其他材料时,可以相应的采用其它刻蚀气体。
以采用溴化氢作为刻蚀气体为例,在本实施例中,溴化氢的流量在50~1000标准毫升每分钟(sccm)的范围内。此外,刻蚀气体中还包括氧气以及保护气体,其中氧气的流量在1~50标准毫升每分钟的范围内,保护气体中包括氦气以及氩气,氦气的流量在10~500标准毫升每分钟的范围内,氩气的流量在0~500标准毫升每分钟的范围内。
另外,在本实施例中,所述等离子刻蚀的气压在10~200毫托的范围内,所述刻蚀设备的功率输出(source power)范围在100~2000瓦的范围,偏置功率(bias power)的范围在0~500瓦的范围,功率输出的脉冲频率在100~10000赫兹的范围内,占空比在90%~0%的范围内。
需要说明的是,在本实施例中的步骤顺序为通过步骤S4形成源区、漏区并通过步骤S5退火,再进行步骤S6的脉冲刻蚀,也就是说所述脉冲刻蚀是对离子掺杂后的应力进行的刻蚀步骤,但是,在本发明的其他实施例中,也可以在步骤S3形成应力层后,先进行脉冲刻蚀,使应力层与衬底齐平,再进行离子掺杂以形成源区、漏区以及对形成的源区、漏区进行退火的步骤,也就是在步骤S3后,先进行步骤S6,再依次进行步骤S4以及步骤S5。
虽然本发明披露如上,但本发明并非限定于此。任何本领域技术人员,在不脱离本发明的精神和范围内,均可作各种更动与修改,因此本发明的保护范围应当以权利要求所限定的范围为准。
Claims (9)
1.一种半导体器件的形成方法,其特征在于,包括:
提供衬底,并在所述衬底上形成若干栅极结构;
在所述栅极结构两侧的衬底中形成沟槽;
在所述栅极结构两侧的沟槽中填充用于形成源区或漏区的应力层,所述应力层凸出所述衬底;其中,在形成应力层的步骤中,采用外延生长的方式,
在所述沟槽中形成所述应力层;
对所述应力层进行脉冲刻蚀,使所述应力层与所述衬底相互齐平;所述脉冲刻蚀为等离子刻蚀。
2.根据权利要求1所述的形成方法,其特征在于:
在衬底中形成若干沟槽的步骤中,使所述沟槽呈∑型;
在形成应力层的步骤中,所述应力层的材料为锗硅。
3.根据权利要求1所述的形成方法,其特征在于:
在衬底中形成若干沟槽的步骤中,使所述沟槽呈U型;
在形成应力层的步骤中,所述应力层的材料为碳化硅。
4.根据权利要求1所述的形成方法,其特征在于,在离子掺杂的步骤之后,进行脉冲刻蚀之前还包括以下步骤:
对所述应力层进行离子掺杂以形成源区以及漏区;
对形成的源区以及漏区进行退火。
5.根据权利要求1所述的形成方法,其特征在于,在形成应力层的步骤之后,等离子刻蚀的步骤之前,还包括以下步骤:在所述衬底、栅极上形成掩模,并使所述应力层暴露出。
6.根据权利要求1所述的形成方法,其特征在于,等离子刻蚀的步骤包括:
使刻蚀气体中包括三氟化氯、溴化氢或者氯气。
7.根据权利要求6所述的形成方法,其特征在于,使所述等离子刻蚀腔体的气压在10~200毫托的范围内,刻蚀设备的功率输出范围在100~2000瓦的范围,偏置功率的范围在0~500瓦的范围,功率输出的脉冲频率在100~10000赫兹的范围内,占空比在90%~0%的范围内。
8.根据权利要求1所述的形成方法,其特征在于,所述等离子刻蚀的刻蚀气体中包括溴化氢、氧气以及保护气体。
9.根据权利要求8所述的形成方法,其特征在于,溴化氢的流量在50~1000标准毫升每分钟的范围内,氧气的流量在1~50标准毫升每分钟的范围内,保护气体包括氦气以及氩气,氦气的流量在10~500标准毫升每分钟的范围内,氩气的流量在0~500标准毫升每分钟的范围内。
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CN102832128A (zh) * | 2011-06-17 | 2012-12-19 | 中芯国际集成电路制造(上海)有限公司 | 一种半导体器件的制造方法 |
CN102983076A (zh) * | 2011-09-07 | 2013-03-20 | 中国科学院微电子研究所 | 半导体集成电路制造方法 |
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