JP2009054705A - 半導体基板、半導体装置およびその製造方法 - Google Patents
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Abstract
【解決手段】本発明の一態様に係る半導体基板は、第1の半導体領域と、前記第1の半導体領域上に前記第1の半導体領域と略等しい結晶から形成され、表面に垂直な方向を軸にして所定の角度だけ前記第1の半導体領域と単位格子の結晶軸の方向がずれている第2の半導体領域と、を有する。
【選択図】図2
Description
B.Doris et al., Symp. on VLSI Tech. Dig. of Tech. Papers, pp.86-87, 2004.
(半導体装置の構成)
図1は、本発明の第1の実施の形態に係る半導体装置の斜視図である。また、図2は、図1に示した切断線II−IIにおける切断面を図中の矢印の方向に見た断面図である。また、図3は、図1に示した切断線III−IIIにおける切断面を図中の矢印の方向に見た断面図である。
図4A(a)〜(c)、図4B(d)〜(f)、図4C(g)〜(i)、図4D(j)〜(k)は、本発明の第1の実施の形態に係る半導体装置の製造工程を示す断面図である。なお、これらの図が示す断面は、図2が示す断面に対応する。
本発明の第1の実施の形態によれば、キャリア移動度を向上させるために最適な結晶軸に対するチャネル方向を有し、かつ好ましいレイアウトで形成することのできるn型FinFET10とp型FinFET20を同一の半導体基板2上に有する半導体装置1を形成することができる。
本発明の第2の実施の形態は、フィン21を構成する結晶と半導体基板2を構成する結晶の単位格子の結晶軸の方向が一致している点において第1の実施の形態と異なる。なお、第1の実施の形態と同様の点については、簡単のために説明を省略する。
図5は、本発明の第2の実施の形態に係る半導体装置の断面図である。なお、同図が示す断面は、図2が示す断面に対応する。
図6A(a)〜(c)、図6B(d)〜(e)は、本発明の第2の実施の形態に係る半導体装置の製造工程を示す断面図である。なお、これらの図が示す断面は、図5が示す断面に対応する。
本発明の第2の実施の形態によれば、第1の実施の形態と異なる構成の半導体装置1により、第1の実施の形態と同様の効果を得ることができる。なお、酸化膜4がフィン11と半導体基板2の間に形成されているため、フィン11内にホットキャリアのインパクトイオン化現象により生じた正孔が半導体基板2側に抜け出すことができなくなり、第1の実施の形態とよりも半導体装置1の動作信頼性において劣る可能性があるが、このホットキャリアのインパクトイオン化現象による問題が半導体装置1の動作信頼性にあまり影響を与えない程度のレベルのアプリケーションであればよい。
本発明の第3の実施の形態は、半導体装置1の一部の製造方法において第1の実施の形態と異なる。なお、第1の実施の形態と同様の点については、簡単のために説明を省略する。
図7(a)〜(c)は、本発明の第3の実施の形態に係る半導体装置の製造工程を示す断面図である。なお、これらの図が示す断面は、図2が示す断面に対応する。
本発明の第3の実施の形態によれば、アモルファス領域7を形成する際に、フィン11の側面が素子分離領域3に覆われているため、フィン11の厚さが薄く、アモルファス領域7を形成するための不純物注入によるダメージに耐えきれずに破損、倒壊等するおそれがある場合であっても、素子分離領域3により支えることができる。なお、再結晶化によりダメージが修復するため、再結晶化後は破損、倒壊等のおそれがない。
本発明の第4の実施の形態は、n型およびp型FinFET10、20のチャネル領域11b、21bに歪みを与える歪み付与膜15、25が形成される点において第1の実施の形態と異なる。なお、第1の実施の形態と同様の点については、簡単のために説明を省略する。
図8は、本発明の第4の実施の形態に係る半導体装置の断面図である。図8に示した断面は、図2に示した第1の実施の形態の半導体装置1の断面に対応する。
本発明の第4の実施の形態によれば、歪み付与膜15、25を形成することにより、チャネル領域11c、21cのキャリア移動度を向上させ、n型FinFET10およびp型FinFET20の電流特性を向上させることができる。
本発明は、上記各実施の形態に限定されず、発明の主旨を逸脱しない範囲内において種々変形実施が可能である。例えば、フィン11、21の表面にSi等の結晶をエピタキシャル成長させて、フィン11、21の厚さを増すことにより電気抵抗率を下げることができる。なお、SiGe結晶、SiC結晶等のSiと異なる格子定数を有する結晶をエピタキシャル成長させた場合は、フィン11、21のチャネル領域11c、21cに適切な歪みを与えて、キャリア移動度を向上させることができる。
(1) 半導体基板と、
前記半導体基板上に前記半導体基板と軸角の略等しい結晶から形成され、前記第1の基板と単位格子の結晶軸の方向が略一致する第1のフィンを有する第1のトランジスタと、
前記半導体基板上に前記半導体基板と軸角の略等しい結晶から形成され、前記半導体基板の表面に垂直な方向を軸にして所定の角度だけ前記第1の半導体基板と単位格子の結晶軸の方向がずれている第2のフィンを有する第2のトランジスタと、
を備えることを特徴とする半導体装置。
(2) 単位格子の結晶軸の1つが表面に垂直な方向を向き、2つが表面に平行な面に沿った方向を向く半導体基板と、
前記半導体基板上に前記半導体基板と軸角の略等しい結晶から形成され、前記第1の基板と単位格子の結晶軸の方向が略一致する第1のフィンを有する第1のトランジスタと、
前記半導体基板上に前記半導体基板と軸角の略等しい結晶から形成され、結晶軸の1つが表面に垂直な方向を向き、2つが前記第1の半導体基板の表面に平行な面に沿った前記第1の半導体基板の単位格子の結晶軸の方向と異なる方向を向く第2のフィンを有する第2のトランジスタと、
を備えることを特徴とする半導体装置。
Claims (5)
- 第1の半導体領域と、
前記第1の半導体領域上に前記第1の半導体領域と略等しい結晶から形成され、表面に垂直な方向を軸にして所定の角度だけ前記第1の半導体領域と単位格子の結晶軸の方向がずれている第2の半導体領域と、
を有することを特徴とする半導体基板。 - 半導体基板と、
前記半導体基板上に形成され、第1のフィンを有する第1のトランジスタと、
前記半導体基板上に形成され、上面の面方位が前記第1のフィンの上面の面方位と等しい第2のフィンを有し、前記第2のフィンの側面部の結晶軸に対するチャネル方向が前記第1のフィンの側面部の結晶軸に対するチャネル方向と異なり、かつフィンの配置される方向が前記第1のフィン型トランジスタのフィンの配置される方向と前記半導体基板の表面に平行な面内において実質的に平行、または垂直な第2のトランジスタと、
を備えることを特徴とする半導体装置。 - 前記第1のトランジスタは、前記第1のフィンの側面の面方位が{100}であり、チャネル方向が{100}面の<100>方向であるn型トランジスタであり、
前記第2のトランジスタは、前記第2のフィンの側面の面方位が{110}であり、チャネル方向が{110}面の<110>方向であるp型トランジスタである、
ことを特徴とする請求項2に記載の半導体装置。 - 第1の基板上に、前記第1の基板と主面の面方位が同一な第2の基板を、双方の主面内の結晶軸の方向が主面に垂直な方向を軸として所定の角度だけ相対的にずれた状態で接合する工程と、
前記第2の基板をパターニングして第1のフィンおよび第2のフィンを形成する工程と、
前記第1のフィンを選択的にアモルファス化する工程と、
前記アモルファス化した第1のフィンを前記第1の基板を下地として再結晶化させ、前記第1の基板と単位格子の結晶軸の方向を略一致させる工程と、
を含むことを特徴とする半導体装置の製造方法。 - 前記第1および第2の基板の主面の面方位が{100}であり、
前記所定の角度は(45+90×n)°(nは整数)である、
ことを特徴とする請求項4に記載の半導体装置の製造方法。
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Application Number | Priority Date | Filing Date | Title |
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JP2007218459A JP2009054705A (ja) | 2007-08-24 | 2007-08-24 | 半導体基板、半導体装置およびその製造方法 |
US12/192,461 US8039843B2 (en) | 2007-08-24 | 2008-08-15 | Semiconductor wafer, semiconductor device and method of fabricating the same |
US13/239,848 US20120009744A1 (en) | 2007-08-24 | 2011-09-22 | Semiconductor wafer, semiconductor device and method of fabricating the same |
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CN104835848A (zh) * | 2014-02-11 | 2015-08-12 | 美国博通公司 | 提供具有介电隔离的finFET技术的基于块状finFET的器件 |
GB2549685B (en) * | 2015-02-24 | 2020-12-09 | Hfc Semiconductor Corp | Dual fin integration for electron and hole mobility enhancement |
GB2549685A (en) * | 2015-02-24 | 2017-10-25 | Ibm | Dual fin integration for electron and hole mobility enhancement |
CN107251204A (zh) * | 2015-02-24 | 2017-10-13 | 国际商业机器公司 | 用于电子和空穴迁移率增强的双鳍集成 |
WO2016135588A1 (en) * | 2015-02-24 | 2016-09-01 | International Business Machines Corporation | Dual fin integration for electron and hole mobility enhancement |
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US20090072276A1 (en) | 2009-03-19 |
US8039843B2 (en) | 2011-10-18 |
US20120009744A1 (en) | 2012-01-12 |
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