JP5355692B2 - 半導体装置及びその製造方法 - Google Patents
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Description
III-V族半導体は、絶縁膜で覆われたSi(111)面の絶縁膜開口部(言い換えるとSi露出部)に選択的に、<111>方向の優先方向をもって成長させることが可能である。図1(a)(b)は、この例を模式的に示している。図1(a)のように、絶縁膜としてのSiO2 膜1に覆われたSi(111)表面の所望の場所に、SiO2 開口領域2を形成する。図1(a)の構造に対しIII-V族半導体を気相成長する場合、図1(b)のようにSiO2 開口領域2の上に選択的に、上面が(111)面、側面が(0-11),(01-1),(1-10),(-110),(-101),(10-1)面である六角柱形状のIII-V族半導体3からなる構造を形成することができる。
本明細書では、ある特定の結晶方向を<hkl>で、それと等価な結晶方向を総称して[hkl]で示す。同様に、ある特定の結晶面を(hkl)で、それと等価な面を総称して{hkl}で示す。(hkl)面と<hkl>方向とは、(hkl)面の垂直方向が<hkl>方向となる関係にある。
図4は、本発明の第1の実施形態に係わるMISFETの素子構造を示す断面図であり、特にチャネル長方向に沿った断面を示している。
本発明の第2の実施形態では、チャネル領域23がGeからなることを除いて第1の実施形態と同じ構造のMISFETを、Geチャネル領域の形成方法を除いて第1の実施形態と同じ形成方法により形成する。即ち、基板面に垂直方向の結晶方位が<110>であるSiからなるソース/ドレイン領域21,22と、チャネル長方向が<-111>であるGeからなるチャネル領域23を有するMISFETを、ダミーチャネル領域を除去する工程を経て、ソース端とドレイン端とに夫々現れた(-111)面と(1-1-1)面とをシード部としてGeを横方向成長させることによって形成する。
図10は、本発明の第3の実施形態に係わるMISFETの素子構造を示す断面図であり、特にチャネル長方向に沿った断面を示している。なお、図10中の41,51〜57は、図4中の11,21〜27に対応している。
図12は、本発明の第4の実施形態に係わるFin型MISFETの素子構造を示す斜視図である。なお、図12中の71〜73,81〜87は、図4中の11〜13,21〜27に対応している。
以上、具体例を参照しつつ本発明の実施の形態について説明した。しかし、本発明はこれらの具体例に限定されるものではない。即ち、これら具体例に、当業者が適宜設計変更を加えたものも、本発明の特徴を備えている限り、本発明の範囲に包含される。例えば、前述した各具体例が備える各要素及びその配置、材料、条件、形状、サイズなどは、例示したものに限定されるわけではなく適宜変更することができる。
2…SiO2 開口領域
3…III-V族半導体
10…SOI基板(支持基板)
11,41,71…Si基板
12,72…埋め込み絶縁膜(BOX)
13,73…Si層(SOI層)
5,21,51,81…ソース領域
6,22,52,82…ドレイン領域
23,53,83…チャネル領域
24,54,84…ゲート絶縁膜
25,55,85…ゲート電極
26,56,86…側壁絶縁膜
27,57,87…層間絶縁膜
29… in-situ doped Si層
31,61,91…ダミーゲート絶縁膜
32,62,92…ダミーゲート電極
33…溝部
34…BOX掘り込み領域
Claims (7)
- 表面と垂直方向な結晶方位が[110]方向のSi1-x Gex(0≦x<0.5)を表面部に有する支持基板の表面部上に、ゲート長方向が前記[110]方向と直交する[111]方向となるようにダミーゲートを形成する工程と、
前記ダミーゲートをマスクに用いて前記基板の表面部にソース/ドレイン領域を形成する工程と、
前記ソース/ドレイン領域の形成後に、前記ダミーゲートの側部に絶縁膜を埋め込み形成する工程と、
前記絶縁膜をマスクに用いて前記ダミーゲートをエッチングし、更に前記ソース/ドレイン領域間の前記基板の表面部をエッチングする工程と、
前記基板の表面部のエッチングにより露出した前記ソース/ドレイン領域の端部をシードとして用い、前記ソース/ドレイン領域間にIII-V族半導体又はGeからなるチャネル領域を成長する工程と、
前記チャネル領域上にゲート絶縁膜を介してゲート電極を形成する工程と、
を含むことを特徴とする半導体装置の製造方法。 - 前記チャネル領域を成長する前に、前記露出した前記ソース/ドレイン領域の端部に対し、{111}面のエッチングレートが他の面よりも遅い異方性ウェットエッチング、又はH2 雰囲気中の高温熱処理を用いて、{111}面を平滑化することを特徴とする請求項1記載の半導体装置の製造方法。
- 前記支持基板は、埋め込み絶縁膜上に前記Si1-x Gex からなる半導体層が形成されたSOI基板であり、前記基板の表面部のエッチング時に、前記半導体層だけでなく、前記埋め込み絶縁膜の一部をエッチングすることを特徴とする請求項1記載の半導体装置の製造方法。
- 前記チャネル領域の周囲全面に前記ゲート絶縁膜を介して前記ゲート電極を形成することを特徴とする請求項3記載の半導体装置の製造方法。
- 支持基板の表面部に、表面と垂直方向な結晶方位が[110]方向のSi1-x Gex(x<0.5)からなり、前記[110]方向と直交する[111]方向に離間して設けられ、且つチャネル長方向の側面の面方位が前記[110]方向と直交する{111}面に形成されたソース/ドレイン領域と、
前記ソース/ドレイン領域間に設けられた、チャネル長方向の結晶方位が[111]のIII-V族半導体又はGeからなるチャネル領域と、
前記チャネル領域上にゲート絶縁膜を介して設けられたゲート電極と、
を具備したことを特徴とする半導体装置。 - 前記チャネル領域のチャネル長方向と垂直な断面の形状が{110}面からなる多角形であることを特徴とする請求項5に記載の半導体装置。
- 前記チャネル領域のチャネル長方向の長さが150nm以下であることを特徴とする請求項5に記載の半導体装置。
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