CN110957273A - 制造半导体装置的方法及全绕栅极场效晶体管 - Google Patents

制造半导体装置的方法及全绕栅极场效晶体管 Download PDF

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CN110957273A
CN110957273A CN201910904928.5A CN201910904928A CN110957273A CN 110957273 A CN110957273 A CN 110957273A CN 201910904928 A CN201910904928 A CN 201910904928A CN 110957273 A CN110957273 A CN 110957273A
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layer
semiconductor
oxide layer
gate
forming
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CN110957273B (zh
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乔治·凡利亚尼提斯
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

一种制造半导体装置的方法及全绕栅极场效晶体管。制造半导体装置的方法包含：形成单晶氧化层于基材上。在形成单晶氧化层后，形成隔离结构，以定义出主动区域。形成栅极结构于主动区域内的单晶氧化层上。形成源极/漏极结构。

Description

制造半导体装置的方法及全绕栅极场效晶体管
技术领域
本揭露是关于一种半导体装置及其制造方法，且特别是一种具单晶氧化层的半导体装置及其制造方法。
背景技术
做为场效晶体管或铁电装置的介电层是高可靠半导体装置的关键元件的一。在未来的半导体装置中，可能需要使用结晶氧化物为栅极介电层。
发明内容
因此，本揭露的一实施例的一态样是提供一种制造半导体装置的方法，形成单晶氧化层于基材上。在形成单晶氧化层后，形成隔离结构，以定义出主动区域。形成栅极结构于主动区域内的单晶氧化层上。形成源极/漏极结构。
本揭露的一实施例的另一态样是提供一种制造半导体装置的方法，形成第一半导体层于半导体基材上。形成由单晶氧化层和位于单晶氧化层上的第二半导体层所组成的一或多对材料层，并接续形成顶部单晶氧化层。通过蚀刻顶部单晶氧化层、一或多对材料层、第一半导体层及半导体基材的一部分，来形成鳍结构。形成隔离绝缘层。形成牺牲栅极结构于鳍结构上。于源极/漏极区域内，去除在一或多对材料层中的顶部单晶氧化层及单晶氧化层。形成源极/漏极磊晶层于源极/漏极区域内。形成层间介电层。去除牺牲栅极结构，借以形成栅极间隙。去除在一或多对材料层中的第一半导体层于栅极间隙内。形成栅极介电层在栅极间隙中。形成栅极电极结构在栅极间隙中。
本揭露的一实施例的又一态样是提供一种全绕栅极场效晶体管(gate-all-around field effect transistor，GAAFET)，包含第一半导体线及第二半导体线，设置于底部鳍结构上，且第一半导体线和第二半导体线的每一者包含通道区域及源极/漏极区域。第一栅极介电层，包覆第一半导体线的通道区域。第二栅极介电层，包覆第二半导体线的通道区域。栅极电极，设置于第一栅极介电层及第二栅极介电层上，其中第一栅极介电层和第二栅极介电层的每一者包含单晶氧化层，单晶氧化层设置于通道区域的上表面及底表层上。栅极电极的一部分是设置在第一半导体线的通道区域与第二半导体线的通道区域之间。
附图说明
当结合随附附图阅读时，自以下详细描述将最佳地理解本揭露的一实施例的态样。应注意，根据工业中的标准实务，附图中的各特征并非按比例绘制。实际上，可出于论述清晰的目的任意增减所说明的特征的尺寸。
图1是绘示根据本揭露的一实施例的制造半导体FET装置的各个阶段的一者的示意图；
图2是绘示根据本揭露的一实施例的制造半导体FET装置的各个阶段的一者的示意图；
图3是绘示根据本揭露的一实施例的制造半导体FET装置的各个阶段的一者的示意图；
图4是绘示根据本揭露的一实施例的制造半导体FET装置的各个阶段的一者的示意图；
图5是绘示根据本揭露的一实施例的制造半导体FET装置的各个阶段的一者的示意图；
图6是绘示根据本揭露的一实施例的制造半导体FET装置的各个阶段的一者的示意图；
图7是绘示根据本揭露的一实施例的制造半导体FET装置的各个阶段的一者的示意图；
图8是绘示根据本揭露的一实施例的制造半导体FET装置的各个阶段的一者的示意图；
图9是绘示根据本揭露的一实施例的制造半导体FET装置的各个阶段的一者的示意图；
图10是绘示根据本揭露的一实施例的制造半导体FET装置的各个阶段的一者的示意图；
图11是绘示根据本揭露的一实施例的制造半导体FET装置的各个阶段的一者的示意图；
图12是绘示根据本揭露的一实施例的制造半导体FET装置的各个阶段的一者的示意图；
图13是绘示根据本揭露的一实施例的制造半导体FET装置的各个阶段的一者的示意图；
图14是绘示根据本揭露的一实施例的制造半导体FET装置的各个阶段的一者的示意图；
图15是绘示根据本揭露的另一实施例的制造半导体FET装置的各个阶段的一者的示意图；
图16是绘示根据本揭露的另一实施例的制造半导体FET装置的各个阶段的一者的示意图；
图17A与图17B是绘示根据本揭露的另一实施例的制造半导体FET装置的各个阶段的一者的示意图；
图18是绘示根据本揭露的另一实施例的制造半导体FET装置的各个阶段的一者的示意图；
图19A至图19C是绘示根据本揭露的另一实施例的制造FET装置的各个阶段的一者的示意图；
图20A至图20C是绘示根据本揭露的另一实施例的制造半导体FET装置的各个阶段的一者的示意图；
图21A至图21C是绘示根据本揭露的另一实施例的制造半导体FET装置的各个阶段的一者的示意图；
图22A与图22B是绘示根据本揭露的另一实施例的制造半导体FET装置的各个阶段的一者的示意图；
图23A与图23B是绘示根据本揭露的另一实施例的制造半导体FET装置的各个阶段的一者的示意图；
图24A至图24C是绘示根据本揭露的另一实施例的制造半导体FET装置的各个阶段的一者的示意图；
图25A与图25B是绘示根据本揭露的另一实施例的制造半导体FET装置的各个阶段的一者的示意图；
图26A与图26B是绘示根据本揭露的另一实施例的制造半导体FET装置的各个阶段的一者的示意图；
图27A与图27B是绘示根据本揭露的另一实施例的制造半导体FET装置的各个阶段的一者的示意图；
图28A至图28D是绘示根据本揭露的另一实施例的制造半导体FET装置的各个阶段的一者的示意图；
图29A与图29B是绘示根据本揭露的另一实施例的制造半导体FET装置的各个阶段的一者的示意图；
图30A至图30C是绘示根据本揭露的另一实施例的制造半导体FET装置的各个阶段的一者的示意图；
图31A至图31C是绘示根据本揭露的另一实施例的制造半导体FET装置的各个阶段的一者的示意图；
图32A至图32D是绘示根据本揭露的另一实施例的制造半导体FET装置的各个阶段的一者的示意图；
图33A至图33C是绘示根据本揭露的一实施例的半导体FET装置的各种栅极结构的示意图。
【符号说明】
10/100：基材
20：单晶氧化层
22：下层
24：上层
26：间隙
28：沟槽
30：浅沟槽隔离区域
31/135：绝缘材料层
40/140：栅极结构
42/165：栅极介电层
44/144：栅极电极层
46/146：硬遮罩
48/148：侧壁间隙壁
50：源极/漏极磊晶层
60/160：层间介电层
65：接触蚀刻停止层
70：金属栅极电极
72/172：功函数调节层
74/174：主体栅极电极层
102：底部鳍结构
105：第一半导体层
107：第三半导体层
110：单晶氧化层
120：第二半导体层
130：鳍结构
144：牺牲电极层
150：源极/漏极磊晶层
170：金属栅极结构
122/124：遮罩层
A-A’/B-B’：线
T：厚度
W：宽度
具体实施方式
以下揭露提供许多不同实施例或例示，以实施发明的不同特征。以下叙述的成份和排列方式的特定例示是为了简化本揭露的一实施例。这些当然仅是做为例示，其目的不在构成限制。举例而言，第一特征形成在第二特征之上或上方的描述包含第一特征和第二特征有直接附接的实施例，也包含有其他特征形成在第一特征和第二特征之间，以致第一特征和第二特征无直接附接的实施例。为简化及清楚，各种特征可以不同的尺寸任意绘示。
此外，空间相对性用语，例如“下方(beneath)”、“在…之下(below)”、“低于(lower)”、“在…之上(above)”、“高于(upper)”等，是为了易于描述附图中所绘示的元件或特征和其他元件或特征的关系。空间相对性用语除了附图中所描绘的方向外，还包含元件在使用或操作时的不同方向。装置可以其他方式定向(旋转90度或在其他方向)，而本文所用的空间相对性描述也可以如此解读。此外，术语“由……制成”可意谓“包含”或者“由……组成”任一者。在本揭露的一实施例中，除有特别说明，用语“A、B及C的一者”可意指“A、B及/或C”(A、B、C、A及B、A及C、B及C，或A、B及C)，且并非意指A的其中一元件、B的其中一元件及C的其中一元件。
针对根据本揭露的一实施例的场效晶体管(field-effect transistor，FET)或铁电装置(ferroelectric device)，结晶介电层是单晶，并对于通道具有特定结晶相，对称且陡峭的界面。当需要结晶氧化物做为栅极介电层时，通过多种方法来沉积氧化层在通道上，例如在非晶质或多晶相中的化学沉积(Chemical Vapor Deposition，CVD)或原子层沉积(tomic Layer Deposition，ALD)。当栅极替换技术使用于FET装置时，此沉积是在后段(或依制成而定于中段)中进行，此沉积在形成层间介电(interlayer dielectric，ILD)层后，此沉积后接着进行化学机械研磨(chemical mechanical polishing，CMP)及虚设栅极去除。在此沉积后，使用高温退火以将氧化层结晶至标的晶相。在栅极替换技术中，栅极介电层的氧化层是形成于夹窄的空间上。，此夹窄的空间是由去除虚设电极和虚设栅极介电层后的侧壁间隙壁所形成。
通常，结晶温度(需要用来转换非晶氧化层为单晶氧化层)是非常高的，当考量到此热处理是在后段(或于中段)制程中进行，其不容许结晶温度高于例如400℃。此特性限制了可在较低温度结晶的氧化物材料的选择。在一些情况下，结晶的退火制程并不一定会实现氧化物的完全结晶或实现所欲的结晶相(完全结晶、斜方晶、单斜晶、立方体晶或正方晶)。此外，透过退火，氧化物的结晶可能造成其部分总厚度(例如：接近通道的区域)为过渡区域的介电质，此过渡区域具有非理想结晶和性质。再者，当氧化膜形成在非平面且不平整的表面(例如：去除虚设(牺牲)栅极后的栅极空间)上和/或在非晶层上(如侧壁间隙壁)，氧化层可能不会被形成为单晶。
在本揭露的一实施例中，单晶氧化层是在半导体制造操作的早期阶段中形成。更特定地说，结晶氧化层是形成于大且平坦的表面上，在此表面上，未曾进行过蚀刻操作或图案化操作。在一些实施例中，单晶氧化层是在形成做为独立隔离层的浅沟槽隔离(shallowtrench isolation，STI)或鳍结构前，形成于基材的装置区域上。在一些实施例中，在对准标记或其他非电路元件形成于基材的切割道中后，形成单晶氧化层。
图1至图4是绘示根据本揭露的一实施例的制造FET装置的各个阶段的示意图。应理解的是，额外的操作可以于图1至图4中所示的制程之前、之中或之后提供，且在方法的额外实施例中，一些下述的操作可以被取代或省略。操作及/或制程的顺序为可交替的。再者，在本揭露的一实施例中，源极与漏极是可交替使用的，且源极/漏极是指源极与漏极其中至少一者。
如图1所示，提供基材10。在一些实施例，基材10包含位于其至少一表面部分上的单晶半导体层，如但不受限于：硅(Si)、锗(Ge)、硅化锗(SiGe)、砷化镓(GaAs)、锑化铟(InSb)、磷化镓(GaP)、锑化镓(GaSb)、砷化铟铝(InAlAs)、砷化铟镓(InGaAs)、锑磷化镓(GaSbP)、锑化砷镓(GaAsSb)及磷化铟(InP)的单晶半导体材料。在某些实施例中，基材10是由结晶的Si、SiGe或Ge所制成。在一些实施例中，基材10可包含其表面区域、一或多层缓冲层(图未绘示)。缓冲层可用以从基材的晶格常数至源极/漏极区域的晶格常数逐渐改变晶格常数。缓冲层可由磊晶成长单晶半导体材料所形成，如但不受限于：Si、Ge、GeSn、SiGe、GaAs、InSb、GaP、GaSb、InAlAs、InGaAs、GaSbP、GaAsSb、氮化镓(GaN)、GaP及InP的单晶半导体材料。在一特定实施例中，基材10包含磊晶成长于硅基材10上的SiGe缓冲层。SiGe缓冲层的锗浓度可由最底缓冲层的30原子％锗增加至最顶缓冲层的70原子％锗。
其上形成有半导体装置的基材的主要表面的晶向为(100)、(110)或(111)，其视其上所形成的结晶氧化物的种类而定。
如图2所示，于基材10上形成单晶氧化层20。如前所述，单晶氧化层20是形成于大且平坦的表面上。特别地，在基材的至少一装置区域(其中形成有半导体电路)上，未进行会产生不平整表面型态的蚀刻或图案化制程，而单晶氧化层20形成在此平坦的装置区域上。在一些实施例中，单晶氧化层20是直接形成于基材10上。
在一些实施例中，单晶氧化层是由选自于由二氧化铪(HfO2)、La2Hf2O7、三氧化二钇(Y2O3)、钛酸锶(SrTiO3)及二氧化锆铪(HfZrO2)的组成群组所制成的一者所制成。在某些实施例中，La2Hf2O7或Y2O3是形成于(100)硅基材上。在其他实施例中，SrTiO3是形成于一(100)锗基材上。只要氧化物具有实质类似于基材的结晶常数(晶格匹配)，可使用镧系与锕系氧化物或其三元组合物。
在一些实施例中，单晶氧化层20的厚度是在约0.5nm至约10nm的范围中，且在其他实施例中，厚度是在约1nm至约5nm的范围中。可通过CVD、ALD、分子束磊晶(molecular beamepitaxy，MBE)或其他适合的磊晶膜形成方法来形成单晶氧化层20。在一些实施例中，成长温度(例如：基材温度)是在约650℃至约1000℃的范围中。在一些实施例中，于形成结晶氧化物(即单晶氧化层20)后，在约650℃至约1000℃范围的温度进行退火操作以改善结晶度。
在其他实施例中，基材10上形成非晶质或多晶氧化层，接着在约650℃至约1000℃范围的温度进行退火操作，以转换非晶质或多晶氧化层为单晶氧化层20。在一些实施例中，温度是在约300℃至约650℃的范围中。
然后，如图3所示，于单晶氧化层20上形成包含下层22与上层24的硬遮罩层。在一些实施例中，下层22为氧化硅，上层24为氮化硅。硬遮罩层可通过CVD形成。
接着，如图4所示，通过一或多个微影与蚀刻制程图案化硬遮罩层，以形成间隙26。更进一步，如图5所示，使用图案化的硬遮罩层来蚀刻单晶氧化层20。在一些实施例中，硬遮罩层的蚀刻及单晶氧化层20的蚀刻是持续进行。
然后，如图6所示，基材10是被沟槽蚀刻，以形成沟槽28。接着，如图7所示，形成包含一或多层的绝缘材料层31于基材上。绝缘层的绝缘材料可包含通过低压化学气相沉积(low-pressure chemical vapor deposition，LPCVD)、电浆CVD或流动式CVD所形成的氧化硅、氮化硅、氮氧化硅(SiON)、SiOCN、SiCN、掺氟硅酸盐玻璃(fluorine-doped silicateglass，FSG)或低介电常数介电材料。如图8所示，在绝缘层的形成后，可进行退火操作。然后，进行平坦化操作，例如化学机械研磨(chemical mechanical polishing，CMP)方法及/或回蚀方法，如此单晶氧化层20的上表面由绝缘材料层暴露，且形成浅沟槽隔离(STI)区域30。在一些实施例中，平坦化操作停止于较低硬遮罩层(即前述的下层22)或较上硬遮罩层(即前述的上层24)，接着通过适当的湿式及/或干式蚀刻操作，去除剩下的硬遮罩层。
接下来，如图9所示，形成牺牲(虚设)栅极结构40。牺牲栅极结构40包含牺牲栅极介电层42、牺牲栅极电极层44及残余的硬遮罩层46。在一些实施例中，牺牲栅极介电层42包含一或多层的绝缘材料，例如氧化硅基材料。在一实施例中，使用通过CVD形成的氧化硅。在一些实施例中，牺牲栅极介电层42的厚度为在约1nm至约5nm的范围。于单晶氧化层20及STI(即前述区域30)上，通过第一毯覆性沉积牺牲栅极介电层42，形成牺牲栅极结构40。牺牲栅极电极层44接着毯覆性沉积于牺牲栅极介电层，且于牺牲栅极电极层44上形成硬遮罩层46。牺牲栅极电极层44包含如多晶硅或非晶硅的硅。在一些实施例中，牺牲栅极电极层44的厚度为在约100nm至约200nm的范围。在一些实施例中，牺牲栅极电极层44是做为平坦化操作的标的。牺牲栅极介电层及牺牲栅极电极层是使用CVD沉积，包含LPCVD与电浆辅助化学气相沉积(plasma enhanced chemical vapor deposition，PECVD)、物理气相沉积(physical vapor deposition，PVD)、ALD或其他适合的制程。接续，于牺牲栅极电极层上硬遮罩层46。硬遮罩层46包含一或多层，例如垫SiN层及氧化硅遮罩层。然后，在遮罩层上进行图案化操作，且图案化牺牲栅极电极层。再者，如图9所示，在面对牺牲栅极电极层44及硬遮罩层46的相对的两侧，形成侧壁间隙壁48。
接着，如图10所示，通过适合的蚀刻操作，去除未被牺牲栅极结构40覆盖的单晶氧化层20。接下来，如图11所示，于图11中所示的源极/漏极区域上，形成半导体材料的一或多层，如源极/漏极磊晶层50。于n通道FET，源极/漏极磊晶层50包含Si、SiP、SiC及SiCP的一或多层。于p通道FET，源极/漏极磊晶层50包含Si、SiGe及Ge。于p通道FET，源极/漏极区域中亦可包含硼(B)。使用CVD、ALD或MBE磊晶成长方法，来形成源极/漏极磊晶层50。
然后，如图12所示，于源极/漏极磊晶层50及牺牲栅极结构40上，形成层间介电(Inter-Layer Dielectric，ILD)层60。ILD层60包含含有硅、氧、碳及/或氢的化合物，例如氧化硅、SiCOH及SiOC。有机材料，例如聚合物，可被使用为ILD层60。如图13所示，于形成ILD层60后，进行平坦化操作，例如CMP，如此暴露牺牲栅极电极层44的顶部分。在一些实施例中，如图13所示，于形成ILD层60前，形成接触蚀刻停止层65，例如氮化硅层或氧化硅层。
然后，去除牺牲栅极电极层44及牺牲栅极介电层42，借以形成栅极间隙。牺牲栅极结构可使用电浆干蚀刻及/或湿式蚀刻去除。当牺牲栅极电极层44是多晶硅且ILD层60是氧化硅时，可使用如如四甲基氢氧化铵(Tetramethylammonium hydroxide，TMAH)溶液的湿式蚀刻剂，以选择性地去除牺牲栅极电极层44。使用电浆干式蚀刻及/或湿式蚀刻，接着去除牺牲栅极介电层42。
如图14所示，在去除牺牲栅极结构后，于单晶氧化层20上形成金属栅极电极70，在栅极间隙内做为栅极电极层。金属栅极电极层(即金属栅极电极70)包含功函数调节材料(即功函数调节层72)及主体栅极电极层74的一或多层。
功函数调节层72是由如如氮化钛(TiN)、氮化钽(TaN)、TaAlC、碳化钛(TiC)、碳化钽(TaC)、钴(Co)、铝(Al)、铝钛(TiAl)、铪钛(HfTi)、硅化钛(TiSi)、TaSi或TiAlC的单一层的导电材料制成，或者是由前述材料的两个或多个的多层的导电材料制成。于n通道FET，使用TaN、TaAlC、TiN、TiC、Co、TiAl、HfTi、TiSi及TaSi的一个或多个做为功函数调节层。于p通道FET，使用TiAlC、Al、TiAl、TaN、TaAlC、TiN、TiC及Co的一个或多个做为功函数调节层。通过ALD、PVD、CVD、电子束蒸发或其他适合的制程，可形成功函数调节层72。再者，功函数调节层72可个别地形成n通道FET及p通道FET，其中，n通道FET及p通道FET可使用不同的金属层。
主体栅极电极层74包含导电材料的一或多层，例如铝、铜、钛、钽、钨、钴、钼、氮化钽、硅化镍、硅化钴、TiN、氮化钨(WN)、TiAl、氮化铝钛(TiAlN)、TaCN、TaC、钽硅氮(TaSiN)、金属合金、其他适合的材料及/或前述的组合。通过CVD、ALD、电镀或其他适合的方法，可形成主体栅极电极层74。金属栅极电极层亦沉积于ILD层60的上表面上。接着，使用如CMP来平坦化形成于ILD层60上的金属栅极电极层，直到暴露ILD层60的顶表面。在一些实施例中，于平坦化操作后，凹陷金属栅极电极层(即金属栅极电极70)，且于凹陷的栅极电极层上形成覆盖绝缘层(图未绘示)。覆盖绝缘层包含氮化硅基材料(例如：SiN)的一或多层。通过沉积绝缘材料接续平坦化操作，可形成覆盖绝缘层。
应理解的是，FET经过更进一步的互补式金属氧化半导体(complementary metal-oxide-semiconductor，CMOS)制程，以形成如接触/介层窗、内连接金属层、介电层及/或钝化层等的各种形态。
如图14所示，先形成做为栅极介电层的单晶氧化层于平面的基材上，然后进行形成金属栅极电极的栅极替换操作。据此，栅极介电层不被形成于栅极间隙，此栅极间隙通过移除牺牲栅极基材所形成的。在这种配置中，单晶氧化层20沉积于侧壁间隙壁48的底部与基材10之间。再者，无单晶氧化层位于侧壁间隙壁48与金属栅极电极70之间，因此功函数调节层72直接接触侧壁间隙壁48。如此一来，由于无绝缘层位于侧壁间隙壁48与金属栅极电极70之间，故有可能增加在金属栅极电极70下方的有效的栅极长度。
如图15至图28D是绘示根据本揭露的一实施例的制造半导体FET装置的各种阶段的示意图。应理解的是，额外的操作可以于图15至图28D中所示的制程之前、之中或之后提供，且在方法的附加实施例中，一些下述的操作可以被取代或省略，且在方法的额外实施例中，一些下述的操作可以被取代或省略。操作及/或制程的顺序可为可替换的。参照图1至图14说明的前述实施例，可使用于图15至图28D相同或相似的材料、配置、尺寸及/或制程，且其细节的说明可被省略。
如图15所示，提供基材100。在一些实施例中，基材100包含在其至少一表面部分的结晶半导体层。基材100可包含如(但不限于)Si、Ge、SiGe、GaAs、InSb、GaP、GaSb、InAlAs、InGaAs、GaSbP、GaAsSb及InP的单晶半导体材料。在某些实施例，基材100是由结晶Si、SiGe或Ge所制成。
如图16所示，做为牺牲层的第一半导体层105于基材100上形成。在一些实施例中，第一半导体层105可做为缓冲半导体层的功用。由磊晶成长如(但不限于)Si、Ge、GeSn、SiGe、GaAs、InSb、GaP、GaSb、InAlAs、InGaAs、GaSbP、GaAsSb、GaN、GaP及InP的单晶半导体材料，可形成第一半导体层。在一些实施例中，基材100是单晶硅，且第一半导体层105是磊晶成长于基材100上的单晶硅锗(SiGe)。SiGe层的锗浓度可由最底缓冲层的30原子％锗，增加至最顶缓冲层的0原子％锗。在一些实施例中，第一半导体层是由SixGe1-x所制成，且基材是由SizGe1-z所制成，其中x<z≤1。在特定实施例中，0.2<x<0.6且0.7<z≤1。在一些实施例中，第一半导体层105的厚度为在约5nm至约30nm的范围。使用CVD、ALD或MBE的磊晶成长方法，来形成第一半导体层105。
接着，如图17A及图17B所示，在第一半导体层105上形成由单晶氧化层110与在单晶氧化层110上的第二半导体层120所组成的一或多对材料层，然后形成顶部单晶氧化层110。单晶氧化层110的形成是相同或相似于如前述的单晶氧化层20的形成。使用CVD、ALD或MBE的磊晶成长方法，来形成第二半导体层120。如图17A及图17B所示，形成两对单晶氧化层110与第二半导体层120。然而，对数并不限于此，其可为一或多于两对。在一些实施例中，对数可高达20对。
在对中的单晶氧化层110及顶部单晶氧化层的每一者的厚度为在约0.5nm至约10nm的范围，且在其他实施例，其厚度在约1nm至约5nm的范围。在一些实施例中，顶部单晶氧化层110的厚度是大于或小于在每对材料层中的顶部单晶氧化层110的厚度。在一些实施例中，此些对材料层中的单晶氧化层110的厚度是不同的。
在一些实施例中，第一半导体层105是由SixGe1-x所制成，而第二半导体层120是由SiyGe1-y所制成，其中x<y≤1。在特定实施例中，0.2<x<0.6且0.7<y≤1。在一些实施例中，第二半导体层120是如基材100的相同的材料。第二半导体层120的厚度为在约5nm至约40nm的范围，且在其他实施例中，其厚度为在约10nm至约30nm的范围。
接着，如图18所示，使用一个或多个微影与蚀刻操作，来图案化顶结晶氧化层(即顶部单晶氧化层)、结晶氧化物(即单晶氧化层110)层与第二半导体层120所组成的一或多对材料层、第一半导体层105及部分的半导体基材100为一或多个鳍结构130。
在一些实施例中，于顶部单晶氧化层110上形成第一遮罩层122及第二遮罩层124。第一遮罩层122是垫氧化层，其是由氧化硅所制成，并可通过热氧化来形成。第二遮罩层124是由SiN所制成，其是通过CVD(包含LPCVD、PECVD、PVD、ALD或其他适合的制程)所形成。使用图案化操作(包含光学微影及蚀刻)，来图案化遮罩层至遮罩图案。
然后，使用图案化遮罩层122与124，来图案化顶结晶氧化层(即顶部单晶氧化层)的堆叠层、结晶氧化物(即单晶氧化层110)层与第二半导体层120所组成的一或多对材料层、第一半导体层105及部分的半导体基材100，借以形成以X方向延伸的鳍结构130。八个鳍结构130是以X方向排列。然而，鳍结构的数量并不以八个为限，且可为1个至7个或多于八个。在一些实施例中，于鳍结构130的两侧形成一个或多个虚设鳍结构，以在图案化的操作中提升图案保真度。如图18所示，鳍结构130具有由顶结晶氧化层(即顶部单晶氧化层)构成的上层部分、结晶氧化物(即单晶氧化层110)层与第二半导体层120所组的一或多对以及第一半导体层105，且鳍结构130具有由部分半导体基材100所构成的底部鳍结构。在一些实施例中，沿着Y方向的鳍结构130上部的宽度为在约5nm至约40nm，在其他实施例中，其宽度为在约10nm至约25nm。
通过任何适合的方法，可图案化鳍结构130。举例来说，使用一个或多个微影制程〔包含双图案(double-patterning)或多重图案(multi-patterning)〕，可图案化结构。一般而言，相较于使用单一且直接的光微影制程，结合微影及自对准(self-aligned)制程的双图案或多重图案允许所制得的图案可例如具有较小的间距。举例来说，在一实施例中，在基材上形成牺牲层，且使用光微影制程，牺牲层是被图案化。使用自对准制程，沿着图案化的牺牲层的边形成间隙壁。然后，移除牺牲层，且余留的间隙壁可接着用于图案化鳍结构130。
在形成鳍结构130后，于基材上形成包含绝缘材料的一或多层的绝缘材料层135，以使鳍结构130可完全地嵌入绝缘层中。绝缘层的绝缘材料可包含通过LPCVD、电浆CVD或流动式CVD形成的氧化硅、氮化硅、SiON、SiOCN、SiCN、FSG或低介电常数介电材料。在绝缘层的形成后，可进行退火操作。然后，进行平坦化操作，例如CMP方法及/或回蚀方法。再者，如图19A至图19C所示，凹陷绝缘材料层135，以使第一半导体层105由绝缘材层至少部分地被暴露出，借以形成隔离绝缘层(即绝缘材料层135)(例如：STI)。图19A是透视示意图，图19B是绘示图19A的沿着线A-A’的剖视示意图，而图19C是绘示图19A的沿着线B-B’的剖视示意图。
如图20A至图20B所示，在形成隔离绝缘层(即绝缘材料层135)后，形成牺牲(虚设)栅极结构140。图20A是透视示意图，图20B是绘示图20A的沿着线A-A’的剖视示意图，而图20C是绘示图20A的沿着线B-B’的剖视示意图。在鳍结构的上部上形成牺牲栅极结构140，此鳍结构包含顶部单晶氧化层110、单晶氧化层110与第二半导体层120的多对层及第一半导体层105的部分。牺牲栅极结构140包含牺牲栅极介电层142及牺牲栅极电极层144。在一些实施例中，于牺牲栅极电极层144上形成残余的硬遮罩层146。牺牲栅极介电层142包含绝缘材料的一或多层，例如氧化硅基材料。在一实施例中，使用通过CVD形成的氧化硅。在一些实施例中，牺牲栅极介电层142的厚度为在约1nm至约5nm的范围。
于鳍结构上，通过第一毯覆性沉积牺牲栅极介电层，形成牺牲栅极结构140。于鳍结构上，牺牲栅极电极层接着毯覆性沉积于牺牲栅极介电层上，如此，鳍结构完全嵌在牺牲栅极电极层中。牺牲栅极电极层包含如多晶硅或非晶硅的硅。在一些实施例中，牺牲栅极电极层的厚度为在约100nm至约200的范围。在一些实施例中，牺牲栅极电极层为平坦化操作的对象。使用的CVD(包含LPCVD与PECVD)、PVD、ALD或其他适合的制程，沉积牺牲栅极介电层及牺牲栅极电极层。接续地，于牺牲栅极电极层上，形成硬遮罩层。在一些实施例中，遮罩层包含垫SiN层及氧化硅遮罩层。
然后，如图20A至图20C所示，在遮罩层上进行图案化操作，且图案化牺牲栅极电极层为牺牲栅极结构140。牺牲栅极结构140包含牺牲栅极介电层142、牺牲栅极电极层144(例如多晶硅)及硬遮罩146。如图20A至图20C所示，通过图案化牺牲栅极结构，堆叠的鳍结构部分地暴露于牺牲栅极结构140的相对侧，借以定义源极/漏极(S/D)区域。在图20A至图20C中，形成一个牺牲栅极结构，然而牺牲栅极结构的数量不限于一个。在一些实施例中，两个或多个牺牲栅极结构以X方向排列。在特定实施例中，于牺牲栅极结构的两侧形成一个或多个虚设牺牲栅极结构，以提升图案保真度。
再者，于牺牲栅极结构140上形成侧壁间隙壁148的覆盖层。覆盖层是以共型的方式被沉积，以使形成在各种表面(例如分别于侧壁、水平的表面及牺牲栅极结构140的顶部)上的覆盖层具有实质相同的厚度。在一些实施例中，覆盖层具有为在约5nm至约20nm范围的厚度。覆盖层包含SiN、SiON及SiCN或任何其他适合的介电材料的一种或多种。通过ALD、CVD或任何其他适合的方法，可形成覆盖层。接着，如图21A至图21C所示，通过异向性蚀刻，去除覆盖层的底部，借以形成侧壁间隙壁148。图21A是透视示意图，图21B是绘示图21A的沿着线A-A’的剖视示意图，且图21C是绘示图21A的沿着线B-B’的剖视示意图。在一些实施例中，硬遮罩层146的上部是被暴露的。在一些实施例中，如图21B所示，其中一个鳍结构是设置于侧壁间隙壁148之下。在其他实施例中，无鳍结构是设置于侧壁间隙壁148之下。
接续地，如图22A及22B所示，使用一个或多个蚀刻操作，来去除顶部单晶氧化层110及在此些对材料层中的单晶氧化层110。图22A是透视示意图，而图22B是绘示图22A的沿着线A-A’的剖视示意图。可使用湿式蚀刻及/或干式蚀刻来去除对第一半导体层105、第二半导体层120及侧壁间隙壁148具选择性的结晶氧化物。在一些实施例中，在侧壁间隙壁148下方的部分结晶氧化层(即单晶氧化层110)的稍微被蚀刻。
然后，如图23A及23B所示，形成源极/漏极磊晶层150。图23A是透视示意图，且图23B是绘示图23A的沿着线A-A’的剖视示意图。如图23B所示，源极/漏极磊晶层150包绕第二半导体层120且覆盖暴露的第一半导体层105的上部。做为n通道FET，源极/漏极磊晶层150包含Si、SiP、SiC及SiCP的一或多层，或者做为p通道FET，源极/漏极磊晶层150包含Si、SiGe及Ge的一或多层。做为p通道FET，源极/漏极亦可包含硼(B)。使用CVD、ALD或MBE的磊晶成长方法，来形成源极/漏极磊晶层150。如图23B所示，在一些实施例中，分别形成源极/漏极磊晶层150于个别的源极/漏极区域上。在其他实施例中，邻近的源极/漏极磊晶层150是合并的。
接下来，于源极/漏极磊晶层150及牺牲栅极结构140上，形成ILD层160。ILD层160的材料包含Si、氧、碳及/或氢，材料例如氧化硅、SiCOH及SiOC。有机材料，例如聚合物，可被使用于ILD层160。如图24A至图24C所示，在形成ILD层160后，进行平坦化操作(例如CMP)，以使牺牲栅极电极层144的顶部被暴露出。图24A为透视示意图，图24B是绘示图24A的沿着线A-A’的剖视示意图，图24C是绘示图24A的沿着线B-B’的剖视示意图。
然后，如图25A及图25B所示，去除包含牺牲电极层(即牺牲栅极电极层144)与牺牲栅极介电层142的牺牲栅极结构140，借以形成栅极间隙149。图25A是透视示意图，且图25B是绘示图25A的沿着线A-A’的剖视示意图。在牺牲栅极结构140的去除期间，ILD层160保护源极/漏极磊晶层150。使用电浆干式蚀刻及/或湿式蚀刻可去除牺牲栅极结构。当牺牲栅极电极层144是多晶硅，且ILD层160是氧化硅，可使用如TMAH溶液的湿式蚀刻剂以选择性地去除牺牲栅极电极层144。使用电浆干式蚀刻及/或湿式蚀刻，接着去除牺牲栅极介电层142。在一些实施例中，由于在牺牲栅极的去除期间的侧向蚀刻，侧壁间隙壁148的水平部分可能出现。
如图26A及图26B所示，在去除牺牲栅极结构后，去除第一半导体层105。图26A是透视示意图，且图26B是绘示图26A的沿着线A-A’的栅极间隙149内的剖视示意图。由于第一半导体层105是由与于基材100(底部鳍结构102)及第二半导体层120不同材料所制成，通过适合的化学溶液，第一半导体层105可选择性地被去除。余留的第二半导体层120为FET的通道区域。
如图27A与27B所示，在去除第一半导体层105后，形成栅极介电层165。图27A为透视示意图，而图27B是绘示图27A的沿着线A-A’的栅极间隙149内的剖视示意图。在一些实施例中，栅极介电层165是由与单晶氧化层110相同的材料所制成。在其他实施例中，栅极介电层165是由与单晶氧化层110不同的材料所制成。在特定实施例中，栅极介电层165包含一或多层的介电材料，介电材料例如HfO2、HfSiO、HfSiON、HfTaO、HfTiO、HfZrO、氧化锆、氧化铝、氧化钛、氧化铪-氧化铝(HfO2-Al2O3)合金、其他适合的高介电常数介电材料及/或前述的结合。
通过CVD、ALD或任何适合的方法可形成栅极介电层165。在一实施例中，为了确保栅极介电层的形态与每个通道区域周围具有一致的厚度，使用如ALD的高度共形沉积制程，形成栅极介电层165。在一实施例中，栅极介电层165的厚度是等同于或小于单晶氧化层110，且栅极介电层165的厚度为在约0.5nm至约5nm的范围。
在一些实施例中，由于栅极介电层165的相对低的沉积温度，例如300℃至500℃，栅极介电层165是非晶硅或多晶硅的。如图27B所示，每个第二半导体层120的顶表面与底表面是已被单晶氧化层110覆盖。因此，栅极介电层165是直接地形成在第二半导体层120的侧面上、最底部的单晶氧化层110上及栅极间隙149的余留内壁上。因此，在第二半导体层120(通道区域)的顶表面与底表面的栅极介电质的有效厚度，是大于第二半导体层120的侧面上的栅极介电质的有效厚度。
在一些实施例中，进行退火操作以结晶化所沉积的栅极介电层165。在这样的情形下。整个栅极介电质是被结晶化。
接着，如图28A与图28B所示，在栅极间隙149内，形成金属栅极结构170。图28A是透视示意图，且图28B是绘示图28A的沿着线A-A’的栅极间隙149内的剖视示意图。金属栅极结构170包含功函数调节材料(即功函数调节层172)与主体栅极电极层174的一或多层。
功函数调节层172是由如TiN、TaN、TaAlC、TiC、TaC、Co、Al、TiAl、HfTi、TiSi、TaSi或TiAlC的单一层的导电材料所制成，或者是由两个或多个前述材料的所组成的多层导电材料所制成。于n通道FET，使用TaN、TaAlC、TiN、TiC、Co、TiAl、HfTi、TiSi及TaSi的一个或多个做为功函数调节层。于p通道FET，使用TiAlC、Al、TiAl、TaN、TaAlC、TiN、TiC及Co的一个或多个做为功函数调节层。通过ALD、PVD、CVD、电子束蒸发或其他适合的制程，可形成功函数调节层172。再者，功函数调节层172可个别地形成，其中，n通道FET及p通道FET可使用不同的金属层。
主体栅极电极层174包含导电材料的一或多层，例如例如铝、铜、钛、钽、钨、钴、钼、氮化钽、硅化镍、硅化钴、TiN、WN、TiAl、TiAlN、TaCN、TaC、TaSiN、金属合金、其他适合的材料及/或前述的组合。通过CVD、ALD、电镀或其他适合的方法，可形成主体栅极电极层174。金属栅极电极层亦沉积于ILD层160的上表面上。接着，使用如CMP来平坦化形成于ILD层160上的金属栅极电极层，直到暴露ILD层160的顶表面。在一些实施例中，于平坦化操作后，凹陷金属栅极电极层(即金属栅极结构170)，且于凹陷的栅极电极层上形成覆盖绝缘层(图未绘示)。覆盖绝缘层包含一或多层氮化硅基材料(例如：SiN)。通过沉积绝缘材料接续平坦化操作，可形成覆盖绝缘层。
可理解的是，全绕栅极场效晶体管(gate-all-around field effecttransistor，GAA FET)经过更进一步的CMOS制程，以形成如接触/介层窗、内连接金属层、介电层及/或钝化层等的各种特征。
图28C是绘示图28A的沿着线A-A’的剖视示意图，且图28D是绘示图28A的沿着线B-B’的剖视示意图。如图28C所示，栅极介电质包绕每个第二半导体层120。栅极介电质包含侧部分(由栅极介电层165所制成)及结晶氧化层(即单晶氧化层110)，其中侧部分是设置于于第二半导体层(做为线)的通道区域的侧表面，结晶氧化层是设置于第二半导体层120的上表面与下表面。在一些实施例中，无功函数调节层172是设置于第二半导体层120的邻近通道区域间。换言之，第二半导体层120的邻近通道区域间的间隙被栅极介电质完全地填满。在一些实施例中，其中第二半导体层120的通道区域的宽度W与厚度T满足1<W/T≤20。在其他实施例中，2<W/T≤10。
如图28D所示，在源极/漏极区域中，第一半导体层105仍在第二半导体层120的源极/漏极区域与底部鳍结构102之间。无单晶氧化层设置于第二半导体层120的源极/漏极区域中。相对的，第一半导体层105与结晶氧化层(即单晶氧化层110)是设置于侧壁间隙壁148的底部与底部鳍结构102之间。
在前述的实施例中，形成如牺牲层的第一半导体层105或中介层。在其他实施例中，未形成第一半导体层105，且单晶氧化层110与第二半导体层120所组成的一或多对材料层是直接形成于基材100上。
在前述的实施例中，顶部单晶氧化层及最底部的单晶氧化层的厚度是视栅极介电层165的沉积调整而定，以使包绕第二半导体层120的栅极介电质的厚度是实质一致的(如±10％)。
图29A至图32C是绘示根据本揭露的另一实施例的制造半导体FET装置的各个阶段的示意图。应理解的是，额外的操作可以于图29A至图32C中所绘示的制程之前、之中或之后提供，且在方法的额外实施例中，一些下述的操作可以被取代或省略。操作及/或制程的顺序可为可替换的。参照图1至图28D说明的前述实施例，可使用于29A至图32C相同或相似的材料、配置、尺寸及/或制程，且其细节的说明可被省略。
图29A是绘示制造半导体FET装置的各个阶段的一者的透视示意图，图29B是绘示图29A的沿着线A-A’的剖视示意图。在此实施例中，于第一半导体层105形成于基材后，一或多个堆叠结构形成于第一半导体层105上。每个堆叠结构包含底单晶氧化层110、于单晶氧化层110上的第二半导体层120及顶部单晶氧化层110。再者，于第一半导体层105上，可替换地形成一个或多个堆叠结构及一个或多个第三半导体层107。在一些实施例中，第三半导体层107是以与基材100及第二半导体层120不同的材料所制成。在一些实施例中，第三半导体层107是由与第一半导体层105相同的材料所制成。
在图29A与图29B中，两对堆叠结构将第三半导体层107夹于其中间。然而，堆叠结构的数量并不限于此，而可为一或多于两对。在一些实施例中，堆叠结构的数量高达20。当堆叠结构的数量为N(N为自然数)，则第三半导体层的数量为N-1。
然后，进行相同或相似于图18至图25B的制造操作，且如图30A至图30C所示，形成栅极间隙149。图30A是透视示意图，图30B是绘示图30A的沿着线A-A’的栅极间隙149内的剖视示意图，且图30C是绘示图30A的沿着线B-B’的剖视示意图。如图31A至图31C所示，在去除牺牲栅极结构后，接着去除第一半导体层105及第三半导体层107。图31A是透视示意图，图31B是绘示图31A的沿着线A-A’的栅极间隙149内的剖视示意图，且图31C是绘示图31A的沿着线B-B’的剖视示意图。相较于基材100(底鳍结构102)与第二半导体层120，当第一半导体层105与第三半导体层107是以不同的材料所制成时，通过适合的化学溶液，可选择性地去除第一半导体层及第三半导体层。余留的第二半导体层120为FET的通道区域。
接着，进行相同或相似于图27A至图28D的制造操作，如图32A至图32D所示，于栅极间隙149内形成栅极介电层165与金属栅极结构170。图32A是透视示意图，图32B与图32C是绘示图32A的沿着线A-A’的栅极间隙149内的剖视示意图，且图32D是绘示图32A的沿着线B-B’的剖视示意图。如图32C所示，在此实施例中，通过栅极介电质(单晶氧化层110与栅极介电层165)及至少一功函数金属层(即功函数调节层172)，包绕每个第二半导体层120(通道区域)。在一些实施例中，无主体金属栅极电极(即主体栅极电极层174)是设置于通道区域之间，且在其他实施例中，至少一部分的主体金属栅极电极(即主体栅极电极层174)是设置于通道区域之间。单晶氧化层110是设置于侧壁间隙壁148之下，但不在源极/漏极区域中。
图33A至图33C是绘示根据本揭露的一实施例的各种栅极结构的示意图。
图33A对应于图14的FET，图33B对应于图28A至图28D的GAA FET，且图33C对应于图32A至图32D的GAA FET。“氧化层1”是指单晶氧化层，且“层2”是指结晶氧化层、非晶氧化层或多晶氧化层的一者。在一些实施例中，其中通道区域的宽度W与厚度T满足1<W/T≤20。在其他实施例中，2<W/T≤10。在一些实施例中，T的范围为在约2nm至约10nm，且W的范围为在约5nm至约20nm。
相较于先前技术，此处所述的各种实施例或例示提供各种优点。举例来说，在本揭露的一实施例中，在装置区域中的平坦表面上，形成单晶氧化层，且无图案化操作无于此平坦表面上。在具有目标结晶度半导体基材上，这样的沉积方法允许在原子层级上有精准的沉积控制，导致单晶氧化层成长。在一些实施例中，单晶氧化层可在无任何额外的退火制程下获得。此外，由于单晶氧化层是于制造阶段的早期形成，氧化物一旦达到完全的结晶度，只要制程温度低于氧化层的熔点(例如HfO2的2758℃)，任何后续热处理将不会改变结晶度。使用单晶氧化层做为栅极介电质，可获得具有无过渡区域的通道的陡峭界面，实现栅极的长度缩减。
应理解的是，并非所有的优点均于须于此处讨论，没有特定的优点需列于所有的实施例或例示中，且其他实施例或例示可提供不同的优点。
根据本揭露的一实施例的一态样，在一种制造半导体装置的方法中，形成单晶氧化层于基材上。在形成单晶氧化层后，形成隔离结构，以定义出主动区域。形成栅极结构于主动区域内的单晶氧化层上。形成源极/漏极结构。在一或多个前述与下述的实施例中，单晶氧化层是由选自于由二氧化铪(HfO2)、铪镧复合氧化物(La2Hf2O7)、三氧化二钇(Y2O3)、钛酸锶(SrTiO3)及二氧化锆铪(HfZrO2)所组成的族群的一者所制成。在一或多个前述与下述的实施例中，在形成栅极结构后，去除形成于源极/漏极区域上的单晶氧化层。在一或多个前述与下述的实施例中，形成源极/漏极结构包含，磊晶地形成源极/漏极半导体磊晶层于被去除的单晶氧化层所在的源极/漏极区域上。在一或多个前述与下述的实施例中，栅极结构包含功函数调节层、栅极电极层及侧壁间隙壁，且单晶氧化层是设置于侧壁间隙壁的底部与基材之间。在一或多个前述与下述的实施例中，功函数调节层是与侧壁间隙壁相接触。在一或多个前述与下述的实施例中，单晶氧化层是在实质自650℃至1000℃范围中的温度上形成。在或多个前述与下述的实施例中，于形成单晶氧化层后，在实质自650℃至1000℃的范围中温度上进行退火操作。
根据本揭露的一实施例的另一态样，在一种制造半导体装置的方法中，形成第一半导体层于半导体基材上。形成由单晶氧化层和位于单晶氧化层上的第二半导体层所组成的一或多对材料层，并接续形成顶部结晶氧化层(即顶部单晶氧化层)。通过蚀刻顶部结晶氧化层(即顶部单晶氧化层)、一或多对材料层、第一半导体层及半导体基材的一部分，来形成鳍结构。形成隔离绝缘层。形成牺牲栅极结构于鳍结构上。于源极/漏极区域内，去除在一或多对材料层中的顶部单晶氧化层及单晶氧化层。形成源极/漏极磊晶层于源极/漏极区域内。形成层间介电层。去除牺牲栅极结构，借以形成栅极间隙。去除在一或多对材料层中的第一半导体层于栅极间隙内。形成栅极介电层在栅极间隙中。形成栅极电极结构在栅极间隙中。在一或多个前述与下述的实施例中，单晶氧化层及顶部单晶氧化层是由选自由二氧化铪(HfO2)、铪镧复合氧化物(La2Hf2O7)、三氧化二钇(Y2O3)、钛酸锶(SrTiO3)及二氧化锆铪(HfZrO2)所组成的族群的一者所制成。在一或多个前述与下述的实施例中，第一半导体层是由SixGe1-x所制成，且第二半导体层是由SiyGe1-y所制成，其中x<y≤1。在一或多个前述与下述的实施例中，形成侧壁间隙壁于牺牲栅极结构的相对的侧面上，其中顶部单晶氧化层及一或多对的材料层是在侧壁间隙壁的下方。在一或多个前述与下述的实施例中，栅极介电层是由与在一或多对材料层中的顶部单晶氧化层及单晶氧化层相同的材料所制成。在一或多个前述与下述的实施例中，栅极介电层是非晶质。在一或多个前述与下述的实施例中，栅极介电层的厚度小于顶部单晶氧化层及在一或多对材料层中的单晶氧化层其中至少一者的厚度。在一或多个前述与下述的实施例中，顶部单晶氧化层的厚度不同于一或多对材料层中的单晶氧化层。在一或多个前述与下述的实施例中，第二半导体层的宽度W及第二半导体层的厚度T满足2<W/T≤10。
根据本揭露的一实施例的又一态样，在制造半导体装置的方法中，形成第一半导体层于半导体基材上。交替地形成堆叠结构与一或多个第三半导体层。堆叠结构的每一者包含底部结晶氧化层(即底部单晶氧化层)、于底部单晶氧化层上的第二半导体和顶部结晶氧化层(即顶部单晶氧化层)。通过蚀刻堆叠结构形成鳍结构、一或多层第三半导体层、第一半导体层与半导体基材的一部分。形成牺牲栅极结构于鳍结构上。于源极/漏极区域内，去除在堆叠结构内的顶部单晶氧化层与底部单晶氧化层。形成源极/漏极磊晶层于源极/漏极区域内。形成层间介电层。去除牺牲栅极结构，借以形成栅极间隙。去除在栅极间隙中的第一半导体层与一或多层的第三半导体层。形成栅极电极结构在栅极间隙中。在一或多个前述与下述的实施例中，顶部结晶氧化层(即顶部单晶氧化层)与底部结晶氧化层(即底部单晶氧化层)是由选自由二氧化铪(HfO2)、铪镧复合氧化物(La2Hf2O7)、三氧化二钇(Y2O3)、钛酸锶(SrTiO3)及二氧化锆铪(HfZrO2)所组成的族群的一者所制成。在一或多个前述与下述的实施例中，栅极电极结构的部分是设置于在堆叠结构的一者中的底部结晶氧化层(即底部单晶氧化层)与在邻近堆叠结构的者中的顶部结晶氧化层(即顶部单晶氧化层)。
根据本揭露的一实施例的再一态样，半导体装置包含通道、设置于通道上的栅极介电层、设置于栅极介电层上的栅极电极层、设置于栅极电极层的相对的两面上的侧壁间隙壁与源极和漏极。栅极介电层包含结晶氧化层，且栅极介电层延伸至低于侧壁间隙壁。在一或多个前述与下述的实施例中，结晶氧化层是由选自由二氧化铪(HfO2)、铪镧复合氧化物(La2Hf2O7)、三氧化二钇(Y2O3)、钛酸锶(SrTiO3)及二氧化锆铪(HfZrO2)所组成的族群的一者所制成。在一或多个前述与下述的实施例中，栅极电极层包含功函数调节层与金属栅极电极层，且功函数调节层与侧壁间隙壁相接触。
根据本揭露的一实施例的又另一态样，一种全绕栅极场效晶体管(gate-all-around field effect transistor，GAAFET)，包含设置于底部鳍结构上且包括通道区域的半导体线、包覆通道区域的栅极介电层和设置于栅极介电层上的栅极电极。栅极介电层包含设置于上表面的单晶氧化层和半导体线的通道区域的下表面。在一或多个前述与下述的实施例中，单晶氧化层是由选自由二氧化铪(HfO2)、铪镧复合氧化物(La2Hf2O7)、三氧化二钇(Y2O3)、钛酸锶(SrTiO3)及二氧化锆铪(HfZrO2)所组成的族群的一者所制成。在一或多个前述与下述的实施例中，栅极介电层包含设置于半导体线的通道区域的侧表面的侧部，且侧部是由与结晶氧化层(即单晶氧化层)相同的材料制成。在一或多个前述与下述的实施例中，栅极介电层的侧部是非晶质。在一或多个前述与下述的实施例中，单晶氧化层的厚度是不同于栅极介电层的侧部的厚度。在一或多个前述与下述的实施例中，GAA FET还包含包覆半导体线的源极/漏极区域且设置于底部鳍结构上的源极/漏极磊晶层。在一或多个前述与下述的实施例中，GAA FET还包含设置于栅极电极的相对侧面的侧壁间隙壁。中介层与单晶氧化层隙设置在侧壁间隙壁与底部鳍结构之间。在一或多个前述与下述的实施例中，无单晶氧化层是设置于半导体线的源极/漏极区域。在一或多个前述与下述的实施例中，GAAFET还包含一或多个额外的半导体线，每个半导体线包含通道区域与源极/漏极区域。栅极介电层包覆一或多个额外半导体线的每一者的通道区域。在一或多个前述与下述的实施例中，栅极电极包含功函数调节层与金属栅极电极层，且无功函数调节层是设置于在半导体线中邻近的通道区域与一或多个额外的半导体线之间。在一或多个前述与下述的实施例中，半导体线的通道区域的宽度W与厚度T满足2<W/T≤10。
根据本揭露的一实施例的又再一态样，一种全绕栅极场效晶体管(gate-all-around field effect transistor，GAAFET)，包含第一半导体线及第二半导体线，设置于底部鳍结构上，且第一半导体线和第二半导体线的每一者包含通道区域及源极/漏极区域。第一栅极介电层，包覆第一半导体线的通道区域。第二栅极介电层，包覆第二半导体线的通道区域。栅极电极，设置于第一栅极介电层及第二栅极介电层上，其中第一栅极介电层和第二栅极介电层的每一者包含单晶氧化层，单晶氧化层设置于通道区域的上表面及底表层上。栅极电极的一部分是设置在第一半导体线的通道区域与第二半导体线的通道区域之间。在一或多个前述与下述的实施例中，单晶氧化层是由选自由二氧化铪(HfO2)、铪镧复合氧化物(La2Hf2O7)、三氧化二钇(Y2O3)、钛酸锶(SrTiO3)及二氧化锆铪(HfZrO2)所组成的族群的一者所制成。在一或多个前述与下述的实施例中，栅极介电层包含设置于第二半导体线的通道区域的侧面上的侧部，且栅极介电层是由与结晶氧化层(即单晶氧化层)相同的材料所制成。在一或多个前述与下述的实施例中，GAA FET还包含设置于第一半导体线的源极/漏极区域与底部鳍结构之间的第一中介半导体层，和设置于第二半导体线的源极/漏极区与第一半导体层的源极/漏极区域之间的第一中介半导体层。在一或多个前述与下述的实施例中，第一半导体线与第二半导体线的通道区域的宽度W与厚度T满足2<W/T≤10。
前述内容概述若干实施例的特征以使得熟悉此项技术者可较佳地理解本揭露的一实施例的内容态样。熟悉此项技术者应理解，其可容易地使用本揭露的一实施例的内容做为设计或修改其他制程及结构的基础用于进行本文中所介绍的实施例的相同的目的及/或达成相同的优点。熟悉此项技术者应同时意识到，此等等效建构不偏离本揭露的一实施例的内容的精神及范畴，且其可在本文中进行各种变化、替代及修饰而不偏离本揭露的一实施例的内容的精神及范畴。

Claims (10)

1.一种制造半导体装置的方法，其特征在于，该制造半导体装置的方法包含：
形成一单晶氧化层于一基材上；
在形成该单晶氧化层后，形成一隔离结构，以定义出一主动区域；
形成一栅极结构于该主动区域内的该单晶氧化层上；以及
形成一源极/漏极结构。
2.根据权利要求1所述的制造半导体装置的方法，其特征在于，其中该单晶氧化层是由选自于由二氧化铪(HfO2)、铪镧复合氧化物(La2Hf2O7)、三氧化二钇(Y2O3)、钛酸锶(SrTiO3)及二氧化锆铪(HfZrO2)所组成的族群的一者所制成。
3.根据权利要求1所述的制造半导体装置的方法，其特征在于，其中
该栅极结构包含一功函数调节层、一栅极电极层及多个侧壁间隙壁；以及
该单晶氧化层是设置于所述多个侧壁间隙壁的多个底部与该基材之间。
4.根据权利要求3所述的制造半导体装置的方法，其特征在于，其中该功函数调节层是与该侧壁间隙壁相接触。
5.一种制造半导体装置的方法，其特征在于，该制造半导体装置的方法包含：
形成一第一半导体层于一半导体基材上；
形成由一单晶氧化层和位于该单晶氧化层上的一第二半导体层所组成的一或多对材料层，并接续形成该顶部单晶氧化层；
通过蚀刻该顶部单晶氧化层、该一或多对材料层、该第一半导体层及该半导体基材的一部分，来形成一鳍结构；
形成一隔离绝缘层；
形成一牺牲栅极结构于该鳍结构上；
于一源极/漏极区域内，去除在该一或多对材料层中的该顶部单晶氧化层及该单晶氧化层；
形成一源极/漏极磊晶层于该源极/漏极区域内；
形成一层间介电层；
去除该牺牲栅极结构，借以形成一栅极间隙；
去除在该一或多对材料层中的该第一半导体层于该栅极间隙内；
形成一栅极介电层在该栅极间隙中；以及
形成一栅极电极结构在该栅极间隙中。
6.根据权利要求5所述的制造半导体装置的方法，其特征在于，其中该第一半导体层是由SixGe1-x所制成，且该第二半导体层是由SiyGe1-y所制成，其中x<y≤1。
7.根据权利要求5所述的制造半导体装置的方法，其特征在于，其中该栅极介电层的一厚度小于该顶部单晶氧化层及在该一或多对材料层中的该单晶氧化层其中至少一者的一厚度。
8.根据权利要求5所述的制造半导体装置的方法，其特征在于，其中该顶部单晶氧化层的一厚度不同于该一或多对材料层中的该单晶氧化层。
9.根据权利要求5所述的制造半导体装置的方法，其特征在于，其中该第二半导体层的一宽度W及该第二半导体层的一厚度T满足2<W/T≤10。
10.一种全绕栅极场效晶体管(gate-all-around field effect transistor，GAAFET)，其特征在于，该全绕栅极场效晶体管包含：
一第一半导体线及一第二半导体线，设置于一底部鳍结构上，且该第一半导体线和该第二半导体线的每一者包含一通道区域及一源极/漏极区域；
一第一栅极介电层，包覆该第一半导体线的该通道区域；
一第二栅极介电层，包覆该第二半导体线的该通道区域；
一栅极电极，设置于该第一栅极介电层及该第二栅极介电层上，
其中该第一栅极介电层和该第二栅极介电层的每一者包含一单晶氧化层，该单晶氧化层设置于该通道区域的一上表面及一底表层上；以及
该栅极电极的一部分是设置在该第一半导体线的该通道区域与该第二半导体线的该通道区域之间。
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