CN101569005A - 形成具有中间层的半导体器件的方法及该半导体器件的结构 - Google Patents
形成具有中间层的半导体器件的方法及该半导体器件的结构 Download PDFInfo
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- 229910052751 metal Inorganic materials 0.000 claims abstract description 75
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- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823857—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
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- H01L21/82345—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures
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Abstract
叠层(30)位于衬底(10)上。叠层包括介质层(16)和金属层(26)之间的层(24)。该层包括卤素和金属。在一个实施例中,卤素是氟。在一个实施例中,叠层是用于晶体管的控制电极叠层。在一个例子中,控制电极叠层是用于MOSFET的栅叠层。在一个例子中,该层包括氟化铝。
Description
技术领域
本发明一般涉及半导体器件,并且更具体地,涉及在导电材料和介质材料之间具有中间层的半导体器件。
背景技术
在硅CMOS(互补金属氧化物半导体)制造领域中,正在考虑使用金属栅。优选的是对PMOS和NMOS器件使用不同的金属,使得可以对每种类型器件的功函数进行优化。功函数的改变将影响阈值电压(VT)。对于PMOS器件,期望功函数接近5.2eV的硅价带边缘,然而对于NMOS器件,则期望功函数接近4.1eV的硅导带边缘。此外,材料在用于激活随后形成的源区和漏区的温度下应当是热稳定的。
如果选择的材料不具有期望的功函数,则包括增加的DIBL(漏感应势垒降低)的短沟道效应可能会不期望地出现。例如,可能会加剧VT下降,增加亚阈值摆动。
然而,被考虑用于PMOS器件和NMOS器件的栅的当前材料不能满足上面的要求。因此,存在对于具有用于PMOS或NMOS器件的期望功函数的结构以及用于这种结构的制造工艺的需要。
附图说明
通过实例的方式说明本发明,且本发明不受附图限制,其中相同的附图标记表示相同的元件。
图1示出根据实施例形成介质层和第一中间层之后的半导体衬底的一部分的横截面图。
图2示出根据实施例形成第一金属电极和图案化掩模之后的图1的半导体衬底;
图3示出根据实施例去除NMOS区域中部分第一中间层和第一金属电极之后的图2的半导体衬底;
图4示出根据实施例形成第二中间层和第二金属电极之后的图3的半导体衬底;
图5示出根据实施例形成多晶硅栅电极之后的图4的半导体衬底;
图6示出根据实施例图案化图5的半导体衬底之后的图5的半导体衬底;以及
图7示出进一步处理之后的图6的半导体衬底。
本领域的技术人员应理解,附图中的元件是简单明了描绘的,且没有必要按照比例描绘。例如,附图中一些元件的尺寸相对于其他元件来说可能被夸大以帮助增进对本发明实施例的理解。
具体实施方式
在一个实施例中,使用位于导电材料(例如,电极)和介质材料之间的中间层来设置NMOS和PMOS MOSFET(金属氧化物半导体场效应晶体管)器件的功函数。在一个实施例中,提供衬底并在衬底上形成第一叠层,并且形成第一叠层包括在衬底上形成介质层、在介质层上形成包括卤素和金属的第一层以及在第一层上形成金属层。通过在介质材料(例如,高介质常数的介质)和导电材料(例如,金属栅电极)之间放置中间层,例如AlF3,可以调制金属/介质的界面偶极子以增加有效金属功函数。因而,界面可用来修改MOSFET中的界面电特性。另外,如果中间层包括诸如氟的卤素,那么倘若将用氟掺杂介质作为形成中间层的结果,那么可以改善电应力下的VT不稳定性。氟可以是期望的,因为它可以替换当形成高介电常数的介质时产生的不希望的氯(Cl)杂质。此外,中间层可用在其他器件中,如DRAM(动态随机存取存储器)电容器和MIM(金属-绝缘体-金属)电容器。在一些实施例中,中间层(或多于一个中间层)在控制电极叠层内。控制电极叠层可以是栅叠层(例如,MOSFET的栅叠层)、电容器的叠层(例如,它可包括金属、介质和中间层)、用于DRAM的叠层、非易失性存储器(NVM)的叠层,或另外类似器件的叠层。
图1示出包括衬底12、介质层16和第一中间层18的半导体器件10。衬底12可以是金属、半导体衬底等或者上述材料的组合。在优选实施例中,衬底是半导体衬底12并且包括隔离区14,例如浅沟槽隔离(STI)区。半导体衬底12可以是任何半导体材料或材料的组合,例如砷化镓、硅锗、绝缘体上硅(SOI)(例如,全耗尽SOI(FDSOD)、硅、单晶硅等以及上述材料的组合。
在图中所示的实施例中的介质层16是第一栅绝缘层16,如高介电常数(high-k或hi-k)材料(例如,HfO2、HfxZr1-xO2或HfxZryOz)、二氧化硅或上述材料的组合。高k材料具有大于二氧化硅的介电常数的介电常数。介质层16可以由任何合适的工艺,如热生长、化学气相沉积(CVD)、原子层沉积(ALD)、物理气相沉积(PVD)等或上述工艺的组合形成。
如将在进一步讨论后理解,第一中间层18是在介质层16和导电层之间,如金属栅电极之间的中间层。在图中所示的实施例中,第一中间层18是PMOS晶体管的中间层。在一个实施例中,第一中间层18是任意的金属卤化物,如金属氟化物、金属氯化物、金属溴化物、金属碘化物或上述材料的组合。优选金属氟化物,因为氟比其他卤素更具电负性。如果第一中间层18是金属氟化物,则它可以是氟化铷(RbF)、氟化锂(LiF)、氟化铯(CsF)、氟化镁(MgF2)、氟化锶(SrF)、以及氟化钪(ScF)、氟化铝(AlF3)、金属和氟的任意组合(例如,包括铝和氟的材料,如氟化的氧化铝(Al2O3))等或上述材料的组合。如将在下面解释的一些金属氟化物,如氟化铷(RbF)、氟化锂(LiF)、氟化铯(CsF)、氟化镁(MgF2)、氟化锶(SrF)和氟化钪(ScF)可以更适合设置NMOS器件的功函数。
在图中所示的实施例中,由于第一中间层18用在PMOS半导体器件中,所以希望对于第一中间层18所选的材料包括与诸如氟的卤素组合的相对电负性的金属。一种合适的材料是包括铝和氟的材料,如AlF3。特别地,由于AlF3包括高浓度的电负性氟原子以及与其他金属相比相对电负性的金属阳离子(铝),因而AlF3是PMOS器件的优选中间层。期望AlF3中元素的高电负性能将PMOS器件的有效功函数增加到所希望的水平。具有较高电负性的金属具有较高的真空功函数。另外,金属-介质(金属-半导体)界面处的有效功函数(势垒高度)也与接触金属和介质的相对电负性有关。这是因为作为原子吸引共享电子到自身的能力的电负性确定在金属-介质界面处发生多少电荷交换。本界面处的电荷交换导致界面电偶极子,而界面电偶极子部分地确定有效功函数(或势垒高度)。因此,界面电偶极子的数量和极性取决于接触金属和介质的相对电负性。
另外,AlF3具有大约1260摄氏度的熔化温度,该熔化温度大于典型地用于激活源区和漏区中掺杂剂的温度。(掺杂剂激活通常发生在大约1000摄氏度)。而且,由于据报道AlF3不吸水(H2O),所以可用作栅氧化物的AlF3将与下面的氧化铪(HfO2)层很好地工作。此外,据报道AlF3具有优良的机械强度。
如果第一中间层18是AlF3,它可以通过任何合适的工艺形成在介质层16上,如PVD(例如,来自AlF3靶的溅射或者Al在Ar/F2环境中的反应溅射)、ALD、CVD、电子束沉积等或上述工艺的组合。另外,第一层18是AlF3,它可以通过将预先被形成(例如,通过CVD、ALD或PVD形成)的铝层氟化来形成。
如果第一中间层18是氟化的Al2O3,则它可以通过形成Al2O3并随后将其氟化而形成。不管是氟化Al还是Al2O3(例如,通过ALD、CVD或PVD),都可通过使用F2、CF4、CxHyFz、NF3等或上述组合的气体或等离子体来发生氟化。
第一中间层18可在大约1至大约15埃厚之间。优选使第一中间层18尽可能薄以实现期望的功函数但足够薄以至不能恶化半导体器件的电容。电容(C)被定义为介电常数(κ)乘以真空的电容率(ε0)再乘以电容器的面积(A)的积除以介质的厚度(t),如下所示:
由于电容与介质厚度成反比,所以期望将金属卤化物层的厚度降到最小。另外,金属卤化物可以具有比也可以恶化电容值的介质层更低的介电常数。
在一个实施例中,介质层16是高k介质,并且第一中间层18是AlF3,其具有大约为4的介电常数。在该实施例中,如果AlF3太厚,它将不期望地抵消高介电常数介质的高介电常数,因而绝缘的AlF3和高k介质将共同有效地作为栅氧化物,其中栅氧化物具有仅比单独的高k介质具有更低的介电常数;这是不希望的。优选的是第一中间层18不负面影响栅氧化物,并代替作为金属栅和栅氧化物之间的功函数调制中间层。然而,第一层18的一部分或全部可作为栅氧化物的一部分。
如图2所示,形成第一中间层18后,在第一中间层18上形成第一金属电极20。第一金属电极20可以是特别适合PMOS器件的氮化钼、氮氧化钼、氮化钨、氧化钌、钌、氮化钛、氧化铱等或上述材料的组合,或者可以是特别适合NMOS器件的碳化钽、氮化硅钽(tantalumsilicon nitride)、氮化钽、氮化钛、碳化铪、氮化铪、碳化锆、氮化锆、与另外的金属合金的碳化钽等或上述材料的组合。在图中所示的实施例中,第一金属电极20是PMOS器件的栅电极。第一金属电极20可通过任何合适的工艺形成,如CVD、ALD、PVD、溅射等或上述工艺的组合。
如图2所示,在半导体器件10上形成第一图案化掩模22。在所示的实施例中,第一图案化掩模22形成在PMOS器件将被形成在其中的半导体器件的区域(PMOS区域)上。因而第一图案化掩模22暴露NMOS器件将被形成在其中的半导体器件10的区域(NMOS区域)。(尽管未示出,本领域的技术人员认识到半导体衬底12可包括掺p型或n型的阱区,这取决于在阱区中是形成NMOS还是PMOS器件)。第一图案化掩模22可为任何合适的掩模,如光刻胶。
如图3所示,在暴露NMOS区域中的半导体器件10的区域之后,可以去除第一金属电极20和第一中间层18的暴露部分。在一个实施例中,第一金属电极20可通过在过氧硫酸(piranha)或SC-1(标准清洗剂1)中的湿法蚀刻去除。过氧硫酸清洗剂由硫酸、过氧化氢和水组成。SC-1清洗剂由氢氧化氨、过氧化氢和水组成。在一个实施例中,可在湿法蚀刻中通过HPO4、HNO3、CH3COOH、HCl、任何其他合适的化学品或上述化学品的组合来去除第一中间层18。在一个实施例中,可使用包括HCl、Br2、Cl2、任何其他合适的化学品或上述化学品的组合的气体来去除第一中间层18。在一个实施例中,四甲基氢氧化氨(TMAH)可以单独使用,或者与如上面描述的那些的任何合适的化学品结合使用。可使用对第一中间层18有选择性的化学等离子体来干法蚀刻第一电极20,然后可以使用上述的化学品的湿法蚀刻来去除中间层18。
如图4所示,在去除半导体器件10的NMOS区域中的部分第一金属电极20和第一中间层18后,在半导体器件上形成第二中间层24和第二金属电极26。在所示的实施例中,第二中间层24和第二金属电极26形成在NMOS区域中的介质层16上,以及形成在PMOS区域中的介质层16、第一中间层18和第一金属电极20上。第二中间层24可以是之前讨论的用于第一中间层18的任何材料,而且可通过之前讨论的用于第一中间层18的任何工艺形成。如在图中所示的实施例中,由于第二中间层24是NMOS区域的中间层,该中间层最好是最适合NMOS器件的中间层材料,例如RbF、LiF、CsF、MgF2、SrF、ScF等或上述材料的组合。对于NMOS器件,优选的是中间层包括与诸如氟的卤素组合的相对电正性的金属。
如图5所示,形成第二中间层24和第二金属电极26之后,可以形成多晶硅栅电极28。多晶硅栅电极28可通过任何合适的工艺形成,如CVD。多晶硅栅电极28比下面的介质层16、第一中间层18、第一金属电极20、第二中间层24和第二金属电极26厚得多(甚至比图中所示的厚得多)。在一个实施例中,多晶硅栅电极28大约1000埃厚。
如图7所示,形成多晶硅栅电极28之后,如果存在,则栅叠层被图案化以形成NMOS栅叠层30和PMOS栅叠层32。在图示的实施例中,NMOS栅包括介质层16、第二中间层24、第二金属电极26和多晶硅栅电极28的一部分。在图示的实施例中,PMOS栅包括介质层16、第一中间层18、第一金属电极20、第二中间层24、第二金属电极26和多晶硅栅电极28的一部分。期望的是第二中间层24足够薄以至于不连续(例如,大约1至大约15埃),使得第一金属电极20和第二金属电极26彼此电连接。如果第二中间层24不够薄,则它(以及或许是第二金属电极26)可在PMOS区域中去除。因而,PMOS栅叠层可不包括第二中间层24或第二金属电极26。
在一个实施例中,当形成NMOS栅叠层30时,可使用(掩模以及)任何合适的化学品,如Cl2、HBr、CF4、CH2F2等或上述化学品的组合来图案化多晶硅栅电极28。可使用任何合适的工艺,例如之前讨论的将第一金属电极20从NMOS区域去除的掩模和蚀刻工艺来蚀刻第二金属电极26。可使用任何合适的工艺,例如之前讨论的将第一中间层18从NMOS区域去除的掩模和化学品来去除第二中间层24。
在一个实施例中,当形成PMOS栅叠层32时,可使用(掩模以及)如之前讨论的用于图案化NMOS栅叠层30的任何合适的化学品来图案化多晶硅28。可使用之前讨论的用于图案化第二中间层24和第二金属电极26的任何合适的工艺来图案化第一中间层18、第一金属电极20、第二中间层24(如果存在)以及第二金属电极26(如果存在)。
图案化NMOS栅叠层30和PMOS栅叠层32后,执行常规的工艺以形成NMOS源/漏区36、PMOS源/漏区38以及隔片34。NMOS源/漏区36和PMOS源/漏区38可包括扩展区和晕环(halo)区(未示出)。隔片34可为任何合适的隔片,例如氮化物隔片、L形隔片或包括材料(例如,氮化物和氧化物)的组合的隔片。形成隔片34后,使用常规工艺将介质层16的暴露部分去除(即图案化介质层16)。执行未图示的后续常规工艺形成特征,例如层间介质层和互连层以连接半导体衬底12上的各种器件。
至此应当明白,本发明提供了具有栅电极叠层的半导体器件的方法,其中栅电极叠层包括栅电极和中间层,使得栅电极叠层具有对器件来说所期望的功函数。所述的中间层也可用于其他器件,如DRAM电容器和MIM电容器结构。例如,在DRAM和MIM电容器中,期望可在顶电极和介质之间、在底电极和介质之间或这两者之间形成具有金属和卤素(例如氟)的中间层。因而,在MIM结构的实施例中,半导体衬底12可为金属衬底。
在前述的说明书中,本发明已参照特定实施例进行了描述。然而本领域的普通技术人员应当明白,在不脱离由下面的权利要求书所阐明的本发明的范围的情况下,可以做出各种修改和变化。因此,说明书和附图应被视为例证性的而非限制性的,并且所有此类的修改都旨在包括在本发明的范围内。
尽管本发明已参照特定的导电类型或电势极性进行了描述,但是本领域的技术人员应当明白,导电类型和电势极性可以相反。
以上参照特定实施例描述了益处、其他优点和问题的解决方案。然而,益处、优点、问题的解决方案以及可引起任何益处、优点或问题的解决方案发生或使之变得更加明确的任何要素,不应被视为任何或所有权利要求的决定性的、必需的或必要的特征或要素。如此处使用的,术语“包括”、“包括了”及其任何其他的变化,旨在覆盖非排它的内含物,使得包括一系列要素的工艺、方法、产品或装置不仅仅包括那些要素,还可包括未明显列出的或者这些工艺、方法、产品或装置原有的其他要素。在此使用的,术语“一(a)”或“一(an)”定义为一个或多个。此外,说明书和权利要求书中的术语“前”、“后”、“顶”、“底”、“上”、“下”等,即便需要,也是用于例证性目的而不必用于描述一成不变的相对位置。应理解的是,这样使用的术语可在适当的情况下互换,使得在此描述的发明的实施例,例如能够在与此处那些已说明的或另外已描述相比的其他方向操作。
Claims (24)
1.一种方法,包括:
提供衬底;以及
在所述衬底上形成第一叠层,其中形成所述第一叠层包括:
在所述衬底上形成介质层;
在所述介质层上形成包括卤素和金属的第一层;以及
在所述第一层上形成金属层。
2.如权利要求1所述的方法,其中形成所述第一叠层还包括在所述金属层上形成多晶硅层。
3.如权利要求1所述的方法,其中形成所述第一叠层还包括图案化所述金属层和所述第一层。
4.如权利要求1所述的方法,其中所述第一层包括氟化铝。
5.如权利要求1所述的方法,其中所述第一层包括从由氟化铷、氟化锂、氟化铯、氟化镁、氟化锶、氟化钙和氟化钪组成的组中选择的至少一种材料。
6.如权利要求1所述的方法,其中所述卤素以氟为特征。
7.如权利要求1所述的方法,其中所述第一叠层以控制电极叠层为特征,并且所述衬底包括半导体材料。
8.如权利要求7所述的方法,其中MOSFET器件以P沟道晶体管为特征。
9.如权利要求1所述的方法,其中形成所述介质层包括形成以高介电常数材料为特征的介质层。
10.如权利要求1所述的方法,其中形成所述金属层包括形成包括从由氮化钼、氮氧化钼、氮化钨、氧化钌、钌、氮化钛、氧化铱组成的组中选择的至少一种材料的金属层。
11.如权利要求1所述的方法,其中形成所述金属层包括形成包括从由碳化钽、氮化钽、氮化硅钽、氮化钛、碳化铪、氮化铪、碳化锆、氮化锆和碳化钛组成的组中选择的至少一种材料的金属层。
12.如权利要求1所述的方法,还包括:
在所述衬底上形成第二叠层,其中形成所述第二叠层包括:
在所述衬底上形成包括卤素和金属的第二层;以及
在所述第二层上形成第二金属层;其中所述第二层以不同于所述第一层的组分为特征。
13.如权利要求12所述的方法,其中所述第二层形成在所述第一层之上。
14.如权利要求12所述的方法,其中形成所述第二叠层还包括:
在形成所述第二层之前去除所述衬底的第一区域之上的所述金属层并且去除所述第一区域之上的所述第一层,其中所述第二叠层形成在所述第一区域中。
15.如权利要求12所述的方法,其中所述叠层以用于第一MOSFET器件的栅叠层为特征,且所述第二叠层以用于第二MOSFET器件的栅叠层为特征,其中所述第一MOSFET器件以P沟道晶体管为特征,且所述第二MOSFET器件以N沟道晶体管为特征。
16.如权利要求1所述的方法,其中:
形成所述介质层包括形成包括铪、锆和氧的层;
形成所述第一层包括形成包括氟化铝的层;以及
形成所述金属层包括形成包括从由氮化钼和氮化钨组成的组中选择的至少一种材料的层。
17.一种形成MOSFET器件结构的方法,所述方法包括:
提供包括半导体材料的衬底;以及
在所述衬底上形成栅叠层,所述栅叠层包括所述衬底上的栅介质、所述栅介质上包括氟和金属的层以及包括氟和金属的所述层上的金属层。
18.如权利要求17所述的方法,其中所述栅叠层还包括所述金属层上的多晶硅层。
19.一种装置,包括:
衬底;以及
位于所述衬底上的叠层,所述叠层包括:
介质层;
所述介质层上包括卤素和金属的第一层;以及
所述第一层上的金属层。
20.如权利要求19所述的装置,其中卤素以氟为特征。
21.如权利要求19所述的装置,还包括:
第二叠层,所述第二叠层包括:
第二介质层;
所述第二介质层上包括卤素和金属的第二层,其中所述第二层以不同于所述第一层的组分为特征;以及
所述第二层上的第二金属层。
22.如权利要求21所述的装置,其中所述第二金属层以不同于所述金属层的组分为特征,并且所述第二介质层以与所述介质层相同的组分为特征。
23.如权利要求19所述的装置,其中所述第一层包括氟化铝。
24.如权利要求19所述的装置,其中所述第一叠层以控制电极叠层为特征,且所述衬底包括半导体材料。
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US11/420,525 | 2006-05-26 | ||
US11/420,525 US7445976B2 (en) | 2006-05-26 | 2006-05-26 | Method of forming a semiconductor device having an interlayer and structure therefor |
PCT/US2007/064482 WO2007140037A2 (en) | 2006-05-26 | 2007-03-21 | Method of forming a semiconductor device having an interlayer and structure thereof |
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US (1) | US7445976B2 (zh) |
JP (1) | JP5254220B2 (zh) |
CN (1) | CN101569005B (zh) |
TW (1) | TWI415255B (zh) |
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CN110957273A (zh) * | 2018-09-26 | 2020-04-03 | 台湾积体电路制造股份有限公司 | 制造半导体装置的方法及全绕栅极场效晶体管 |
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Publication number | Publication date |
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JP5254220B2 (ja) | 2013-08-07 |
US7445976B2 (en) | 2008-11-04 |
US20070272975A1 (en) | 2007-11-29 |
CN101569005B (zh) | 2012-07-04 |
TW200746413A (en) | 2007-12-16 |
TWI415255B (zh) | 2013-11-11 |
WO2007140037A2 (en) | 2007-12-06 |
JP2009538542A (ja) | 2009-11-05 |
WO2007140037A3 (en) | 2008-12-24 |
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