TWI625792B - 半導體元件及其製作方法 - Google Patents

半導體元件及其製作方法 Download PDF

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TWI625792B
TWI625792B TW103119927A TW103119927A TWI625792B TW I625792 B TWI625792 B TW I625792B TW 103119927 A TW103119927 A TW 103119927A TW 103119927 A TW103119927 A TW 103119927A TW I625792 B TWI625792 B TW I625792B
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layer
dielectric layer
sidewall
disposed
patterned
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TW201546906A (zh
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許家福
邱春茂
徐世杰
郭龍恩
張幼弟
柯建村
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聯華電子股份有限公司
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Priority to US14/324,092 priority patent/US9761690B2/en
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Priority to US15/667,629 priority patent/US10164052B2/en
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    • H01L29/66409Unipolar field-effect transistors
    • H01L29/66477Unipolar field-effect transistors with an insulated gate, i.e. MISFET
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    • H01L29/40Electrodes ; Multistep manufacturing processes therefor
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    • H01L29/40Electrodes ; Multistep manufacturing processes therefor
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    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007Multistep manufacturing processes
    • H01L29/66075Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409Unipolar field-effect transistors
    • H01L29/66477Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66545Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
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    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
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    • H01L29/76Unipolar devices, e.g. field effect transistors
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    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/7833Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's

Abstract

本發明是揭露一種製作半導體元件的方法。首先提供一基底,然後形成一介質層於基底上。接著形成一堆疊結構於介質層上、圖案化堆疊結構以形成一閘極結構於介質層上、形成一襯墊層於介質層及閘極結構上以及去除部分襯墊層及部分介質層以形成一側壁子。

Description

半導體元件及其製作方法
本發明是關於一種製作半導體元件的方法,尤指一種於圖案化堆疊結構以形成閘極結構時保留介質層的方法。
在習知半導體產業中,多晶矽係廣泛地應用於半導體元件如金氧半導體(metal-oxide-semiconductor,MOS)電晶體中,作為標準的閘極填充材料選擇。然而,隨著MOS電晶體尺寸持續地微縮,傳統多晶矽閘極因硼穿透(boron penetration)效應導致元件效能降低,及其難以避免的空乏效應(depletion effect)等問題,使得等效的閘極介電層厚度增加、閘極電容值下降,進而導致元件驅動能力的衰退等困境。因此,半導體業界更嘗試以新的閘極填充材料,例如利用功函數(work function)金屬來取代傳統的多晶矽閘極,用以作為匹配高介電常數(High-K)閘極介電層的控制電極。
然而,在現今金屬閘極電晶體製作過程中,特別是在製作出閘極結構並接著形成後續側壁子的過程中,所使用的蝕刻氣體容易因過蝕刻、底切等現象,而蝕穿側壁子滲入閘極結構底部,造成閘極結構底部高介電常數介電層以及/或底部金屬阻隔層(bottom barrier metal,BBM)腐蝕(erosion)的情形,進而影響元件效能。因此如何改良現今製程以解決上述問題即為現今一重要課題。
因此本發明是揭露一種製作半導體元件的方法及相對結構,以解決上述習知製程中損害到高介電常數介電層的問題。
本發明較佳實施例是揭露一種製作半導體元件的方法。首先提供一基底,然後形成一介質層於基底上。接著形成一堆疊結構於介質層上、圖案化堆疊結構以形成一閘極結構於介質層上、形成一襯墊層於介質層及閘極結構上以及去除部分襯墊層及部分介質層以形成一側壁子。
本發明另一實施例是揭露一種半導體元件,其包含一基底;一介質層設於基底上;一閘極結構設於介質層上;以及一側壁子設於閘極結構旁以及部分介質層上。
12‧‧‧基底
14‧‧‧淺溝隔離
16‧‧‧介質層
18‧‧‧堆疊結構
20‧‧‧高介電常數介電層
22‧‧‧底部金屬阻隔層
24‧‧‧矽層
26‧‧‧硬遮罩
28‧‧‧閘極結構
30‧‧‧輕摻雜汲極
32‧‧‧襯墊層
34‧‧‧側壁子
36‧‧‧源極/汲極區域
38‧‧‧接觸洞蝕刻停止層
40‧‧‧層間介電層
42‧‧‧功函數金屬層
44‧‧‧低阻抗金屬層
46‧‧‧導電層
48‧‧‧主側壁子
第1圖至第5圖為本發明較佳實施例製作一半導體元件之示意圖。
請參照第1圖至第5圖,第1圖至第5圖為本發明較佳實施例製作一半導體元件之示意圖。如第1圖所示,首先提供一基底12,例如一晶圓(wafer)或矽覆絕緣(SOI)基底等,且基底中設有複數個淺溝隔離(shallow trench isolation,STI)14。隨後全面性覆蓋一介質層16於基底12與淺溝隔離14上,並再形成一堆疊結構18於基底12上,其中形成堆疊結構18的方式包含依序於介質層上16形成一高介電常數介電層20、一底部金屬阻隔(bottom barrier metal,BBM) 層22、一矽層24以及一硬遮罩26。
在本實施例中,介質層16較佳包含矽化物層,例如二氧 化矽(SiO2)、氮化矽(SiN)或氮氧化矽(SiON),但不排除可選自高介電常數的介電材料,底部金屬阻隔層22較佳包含氮化鈦(TiN),矽層24較佳包含單晶矽、摻雜多晶矽或非摻雜多晶矽,而硬遮罩26可選自由碳化矽(SiC)、氮氧化矽(SiON)、氮化矽(SiN)、氮碳化矽(SiCN)以及氮硼化矽(SiBN)等所構成的群組,但不侷限於此。本實施例之硬遮罩26雖較佳為一單層硬遮罩,但並不侷限於此,又可選擇性採用一由例如氧化矽及氮化矽所構成的複合式硬遮罩,此變化型也屬本發明所涵蓋的範圍。
另外,本實施例是以金屬閘極置換製程中後閘極(gate last) 製程之先高介電常數介電層(high-k first)製程為例,故高介電常數介電層20較佳為一具有I型剖面之高介電常數介電層,其材料包含介電常數大於4的介電材料,例如係選自氧化鉿(hafnium oxide,HfO2)、矽酸鉿氧化合物(hafnium silicon oxide,HfSiO4)、矽酸鉿氮氧化合物(hafnium silicon oxynitride,HfSiON)、氧化鋁(aluminum oxide,Al2O3)、氧化鑭(lanthanum oxide,La2O3)、氧化鉭(tantalum oxide,Ta2O5)、氧化釔(yttrium oxide,Y2O3)、氧化鋯(zirconium oxide,ZrO2)、鈦酸鍶(strontium titanate oxide,SrTiO3)、矽酸鋯氧化合物(zirconium silicon oxide,ZrSiO4)、鋯酸鉿(hafnium zirconium oxide,HfZrO4)、鍶鉍鉭氧化物(strontium bismuth tantalate,SrBi2Ta2O9,SBT)、鋯鈦酸鉛(lead zirconate titanate,PbZrxTi1-xO3,PZT)、鈦酸鋇鍶(barium strontium titanate,BaxSr1-xTiO3,BST)、或其組合所組成之群組。
在本實施例中,形成高介電常數介電層20的方法包括原 子層沉積(atomic layer deposition,ALD)製程或有機金屬化學氣相沉積法(metal-organic chemical vapor deposition,MOCVD),但不以此為限。
然後如第2圖所示,形成一圖案化遮罩,例如一圖案化光 阻層(圖未示)於硬遮罩26上,並利用此圖案化光阻層當作遮罩進行一圖案轉移製程,以單次蝕刻或逐次蝕刻方式去除部分未被圖案化光阻層所遮蓋的硬遮罩26、矽層24、底部金屬阻隔層22以及高介電常數介電層20,以於介質層16上形成一閘極結構28。換句話說,閘極結構28較佳包含圖案化之高介電常數介電層20、圖案化之底部金屬阻隔層22、圖案化之犧牲層24以及圖案化之硬遮罩26。
如第3圖所示,然後進行一側壁子製程,例如可先形成一 襯墊層32並覆蓋閘極結構28與介質層16。在本實施例中,襯墊層32可包含二氧化矽或氮化矽,但不侷限於此。
接著如第4圖所示,進行一回蝕刻製程,以單次或多次蝕 刻方式去除部分襯墊層32與部分介質層16,以形成一側壁子34於閘極結構28側壁。依據本發明之較佳實施例,所形成的側壁子34較佳跨坐在蝕刻後的介質層16上,且由於部分介質層16較佳在前述回蝕刻過程中與襯墊層32一同被去除,因此側壁子34的邊緣較佳切齊於介質層16的邊緣。至此即完成本發明較佳實施例製作一半導體元件的流程。然後可進行一輕摻雜離子佈植製程,以於側壁子34兩側的基底12中形成一輕摻雜汲極30。輕摻雜離子佈植製程所 植入之離子可依據電晶體的型態有所調整,例如若所製備的電晶體為NMOS電晶體時可將N型摻質植入基底,反之若製備的電晶體為PMOS電晶體時可將P型摻質植入基底12。需注意的是,本實施例雖於製作側壁子34後才於基底12中形成輕摻雜汲極30,但不侷限於此順序,形成輕摻雜汲極30的時間點又可選擇在形成側壁子34之前,此變化型也屬本發明所涵蓋的範圍。
請再參照第4圖,本發明另揭露一種半導體元件結構,其 主要包含一基底12、一介質層16設於基底12上、一閘極結構28設於介質層16上以及一側壁子34設於閘極結構28旁與部分介質層16上。如圖中所示,閘極結構28包含一圖案化之高介電常數介電層20、一圖案化之底部金屬阻隔層22設於圖案化之高介電常數介電層20上、一圖案化之矽層24設於圖案化之底部金屬阻隔層22上以及一圖案化之硬遮罩26設於圖案化之矽層24上。
依據本發明之較佳實施例,介質層16包含二氧化矽,圖 案化之底部金屬阻隔層22包含氮化鈦,圖案化之矽層24包含非晶矽或多晶矽,而側壁子34則包含二氧化矽或氮化矽。另外以介質層16與整個閘極結構28所設置的相對位置而言,介質層16的寬度較佳大於閘極結構28的整體寬度,且介質層16的邊緣較佳切齊於側壁子34的邊緣。
依據本發明一實施例,迨完成前述側壁子34製程後,如 第5圖所示,可繼續進行後續電晶體製程,例如先形成一主側壁子48於側壁子34側壁,然後再形成一源極/汲極區域36於主側壁子48兩側的基底12中。接著形成一接觸洞蝕刻停止層38覆蓋閘極結 構28,並形成一層間介電層40於接觸洞蝕刻停止層38上。需注意的是,形成接觸洞蝕刻停止層38之前又可視產品需求形成磊晶層與矽化金屬層等元件,由於該些製程乃此領域者所熟知技藝,在此不另加贅述。
之後可進行一金屬閘極置換(replacement metal gate)製 程,將閘極結構28轉換為一金屬閘極。金屬閘極置換製程可包括先進行一選擇性之乾蝕刻或濕蝕刻製程,例如利用氨水(ammonium hydroxide,NH4OH)或氫氧化四甲銨(Tetramethylammonium Hydroxide,TMAH)等蝕刻溶液來去除閘極結構28中的矽層24以形成一凹槽(圖未示)。之後再形成一包含U型功函數金屬層42與低阻抗金屬層44的導電層46於該凹槽內,並再搭配進行一平坦化製程以形成一金屬閘極。
在本實施例中,功函數金屬層42較佳用以調整形成金屬 閘極之功函數,使其適用於N型電晶體(NMOS)或P型電晶體(PMOS)。若電晶體為N型電晶體,功函數金屬層42可選用功函數為3.9電子伏特(eV)~4.3eV的金屬材料,如鋁化鈦(TiAl)、鋁化鋯(ZrAl)、鋁化鎢(WA1)、鋁化鉭(TaAl)、鋁化鉿(HfAl)或TiAlC(碳化鈦鋁)等,但不以此為限;若電晶體為P型電晶體,功函數金屬層42可選用功函數為4.8eV~5.2eV的金屬材料,如氮化鈦(TiN)、氮化鉭(TaN)或碳化鉭(TaC)等,但不以此為限。功函數金屬層42與低阻抗金屬層44之間可包含另一阻障層(圖未示),其中阻障層的材料可包含鈦(Ti)、氮化鈦(TiN)、鉭(Ta)、氮化鉭(TaN)等材料。低阻抗金屬層44則可選自銅(Cu)、鋁(Al)、鎢(W)、鈦鋁合金(TiAl)、鈷鎢磷化物(cobalt tungsten phosphide,CoWP)等低電阻材料或其組合。
綜上所述,本發明主要在圖案化堆疊結構以形成閘極結構的過程中僅以蝕刻製程去除部分硬遮罩、矽層、底部金屬阻隔層以及高介電常數介電層等但不去除任何介質層,使後續形成的側壁子可跨坐在介質層上。由於介質層的寬度較佳大於整個閘極結構的整體寬度,本發明可利用突出的介質層來提升閘極結構底部的結構強度,進而避免後續製作側壁子時所使用的蝕刻氣體侵蝕到閘極結構底部的高介電常數介電層以及/或底部金屬阻隔層等材料層。
以上所述僅為本發明之較佳實施例,凡依本發明申請專利範圍所做之均等變化與修飾,皆應屬本發明之涵蓋範圍。

Claims (16)

  1. 一種製作半導體元件的方法,包含:提供一基底;形成一介質層於該基底上;形成一堆疊結構於該介質層上;圖案化該堆疊結構以形成一閘極結構於該介質層上;形成一襯墊層於該介質層及該閘極結構上;去除部分該襯墊層及部分該介質層以形成一第一側壁子;以及形成一第二側壁子於該第一側壁子以及該介質層側壁,其中該第二側壁子底部低於該第一側壁子底部。
  2. 如申請專利範圍第1項所述之方法,其中該介質層包含二氧化矽。
  3. 如申請專利範圍第1項所述之方法,其中該堆疊結構包含一高介電常數介電層、一底部金屬阻隔層設於該高介電常數介電層上、一矽層設於該底部金屬阻隔層上以及一硬遮罩設於該矽層上。
  4. 如申請專利範圍第3項所述之方法,其中該底部金屬阻隔層包含氮化鈦。
  5. 如申請專利範圍第3項所述之方法,其中該矽層包含非晶矽或多晶矽。
  6. 如申請專利範圍第1項所述之方法,其中該襯墊層包含二氧化矽 或氮化矽。
  7. 如申請專利範圍第1項所述之方法,另包含回蝕刻部分該襯墊層及部分該介質層以形成跨坐於該介質層上之該第一側壁子。
  8. 如申請專利範圍第1項所述之方法,另包含回蝕刻部分該襯墊層及部分該介質層以形成該第一側壁子,且該第一側壁子之邊緣切齊於該介質層之邊緣。
  9. 一種半導體元件,包含:一基底;一介質層設於該基底上;一閘極結構設於該介質層上;一第一側壁子設於該閘極結構旁以及部分該介質層上;以及一第二側壁子於該第一側壁子以及該介質層側壁,其中該第二側壁子底部低於該第一側壁子底部。
  10. 如申請專利範圍第9項所述之半導體元件,其中該介質層包含二氧化矽。
  11. 如申請專利範圍第9項所述之半導體元件,其中該閘極結構包含一圖案化之高介電常數介電層、一圖案化之底部金屬阻隔層設於該圖案化之高介電常數介電層上、一圖案化之矽層設於該圖案化之底部金屬阻隔層上以及一圖案化之硬遮罩設於該圖案化之矽層上。
  12. 如申請專利範圍第11項所述之半導體元件,其中該圖案化之底部金屬阻隔層包含氮化鈦。
  13. 如申請專利範圍第11項所述之半導體元件,其中該圖案化之矽層包含非晶矽或多晶矽。
  14. 如申請專利範圍第9項所述之半導體元件,其中該第一側壁子包含二氧化矽或氮化矽。
  15. 如申請專利範圍第9項所述之半導體元件,其中該介質層之寬度大於該閘極結構之寬度。
  16. 如申請專利範圍第9項所述之半導體元件,其中該介質層之邊緣切齊於該第一側壁子之邊緣。
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