TW201743446A - 半導體裝置及其形成方法 - Google Patents

半導體裝置及其形成方法 Download PDF

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TW201743446A
TW201743446A TW106102864A TW106102864A TW201743446A TW 201743446 A TW201743446 A TW 201743446A TW 106102864 A TW106102864 A TW 106102864A TW 106102864 A TW106102864 A TW 106102864A TW 201743446 A TW201743446 A TW 201743446A
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Taiwan
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gate
gate stack
dielectric
stack
semiconductor device
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TW106102864A
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TWI618242B (zh
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林志翰
謝文碩
黃明傑
陳嘉仁
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台灣積體電路製造股份有限公司
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Abstract

一種半導體裝置，包含：一閘極隔離插塞，其進一步包含具有一底部部分及兩個側壁部分之U型層，以及與該底部部分重疊之內部區，且該內部區與兩個側壁部分接觸；一第一電晶體，具有一第一閘極堆疊，且該第一閘極堆疊的第一末端與該閘極隔離插塞的內部區及U型層接觸；以及一第二電晶體，具有一第二閘極堆疊，且該第二閘極堆疊的第二末端與該閘極隔離插塞的內部區及U型層接觸，該第一閘極堆疊及該第二閘極堆疊位於該閘極隔離插塞的相對側。

Description

半導體裝置及其形成方法
本發明實施例係關於半導體裝置及其形成方法。
金屬氧化物半導體(MOS)裝置為積體電路中的基本構成元件。現存的MOS裝置通常具有閘極電極，其具有利用摻雜操作如離子佈植或熱擴散，以p型或n型雜質摻雜之多晶矽。閘極電極的功函數被調整至矽的能帶邊緣(band-edge)。對於n型金屬氧化物半導體(NMOS)裝置，功函數可被調整至接近矽的導帶(conduction band)。對於p型金屬氧化物半導體(PMOS)裝置，功函數可被調整至接近矽的價帶(valence band)。調整多晶矽閘極電極的功函數可藉由選擇適當的雜質而達成。
具有多晶矽閘極電極MOS裝置顯示載子空乏效應，其亦稱作為多晶矽空乏效應(poly depletion effect)。多晶矽空乏效應發生在施加的電場將載子從接近閘極介電質的閘極區消除(sweep away)而形成空乏層時。於n型摻雜多晶矽層中，空乏層包含離子化固定的(non-mobile)供體位置，其中在p型摻雜多晶矽層中，空乏層包含離子化固定的受體位置。空乏效應造成有效閘極介電質厚度的增加，使得反轉層(inversion layer)更加難以在半導體的表面產生。
多晶矽空乏問題可藉由形成金屬閘極電極或金屬矽化物閘極電極加以解決，其中使用於NMOS裝置及PMOS裝置中的金屬閘極亦可具有能帶邊緣(band-edge)功函數。NMOS裝置及PMOS裝置對於功函數具有不同的需求，因此可使用雙閘極(dual-gate)CMOS裝置。
在金屬閘極電極的形成中，先形成長型虛設閘極，其接著被蝕刻，使得長型虛設閘極的一部分彼此分開。接著，填充介電材料於長型虛設閘極之蝕刻部分所留下的開口中，接著研磨介電材料，留下部分介電材料於虛設閘極的剩餘部分之間，接著以金屬閘極取代虛設閘極之分開部分。
在一些實施例中，提供一種半導體裝置，包括：一閘極隔離插塞，包括：一U型層，包括一底部部分及兩個側壁部分；以及一內部區，與該底部部分重疊，其中該內部區與上述兩個側壁部分接觸；一第一電晶體，包括一第一閘極堆疊，其中該第一閘極堆疊的一第一末端與該閘極隔離插塞的內部區及U型層接觸；以及一第二電晶體，包括一第二閘極堆疊，該第一閘極堆疊及該第二閘極堆疊位於該閘極隔離插塞的相對側，其中該第二閘極堆疊的一第二末端與該閘極隔離插塞的內部區及U型層接觸。
在另一些實施例中，亦提供一種半導體裝置，包括：一長條狀閘極堆疊；一閘極隔離插塞，將該長條狀閘極堆疊分為一第一閘極堆疊及一第二閘極堆疊，其中該閘極隔離插塞包括：一外部層，包括一底部部分及兩個側壁部分；以及一 內部區，與該底部部分重疊並接觸，其中該外部層的兩個側壁部分及該內部區的一頂表面實質上與彼此共平面，且該第一閘極堆疊及該第二閘極堆疊與該內部區之相對的側壁接觸；一第一鰭式場效電晶體(FinFET)，包括：一第一半導體鰭板，其中該第一閘極堆疊跨過(cross over)該第一半導體鰭板；以及一第二鰭式場效電晶體，包括：一第二半導體鰭板，其中該第二閘極堆疊跨過該第二半導體鰭板。
在另一些實施例中，亦提供一種半導體裝置的形成方法，包括：形成一長條狀虛設閘極堆疊；蝕刻該長條狀虛設閘極堆疊以形成一第一開口，其中該第一開口將該長條狀虛設閘極堆疊分為一第一虛設閘極堆疊及一第二虛設閘極堆疊；沉積一介電層，其中該介電層延伸於該第一開口中；形成一介電區，填充該第一開口之剩餘空間；於該介電層、該介電區、該第一虛設閘極堆疊及該第二虛設閘極堆疊上實行一平坦化製程；移除該第一虛設閘極堆疊及該第二虛設閘極堆疊以分別形成一第二開口及一第三開口；蝕刻面向該第二開口及該第三開口的介電層的部分直到該介電區的側壁暴露於該第二開口及該第三開口中；以及分別以一第一取代閘極及一第二取代閘極填充該第二開口及該第三開口。
2‧‧‧半導體晶圓
20‧‧‧基底
22‧‧‧隔離區
24‧‧‧半導體鰭板
26‧‧‧閘極介電質
28‧‧‧虛設閘極電極
30‧‧‧硬遮罩
32、32A、32B‧‧‧虛設閘極堆疊
34、34A、34B‧‧‧閘極間隔物
36‧‧‧層間介電質
38‧‧‧源極/汲極區
40‧‧‧源極/汲極矽化物區
42‧‧‧源極/汲極接觸插塞
44‧‧‧光阻
46‧‧‧開口
48、48’‧‧‧介電層
49‧‧‧側壁
50、50’‧‧‧介電區
51‧‧‧側壁
52‧‧‧閘極隔離插塞
54A、54B‧‧‧開口
58A、58B‧‧‧取代閘極堆疊
60‧‧‧閘極電極
62‧‧‧閘極介電質
66A、66B‧‧‧閘極接觸插塞
68‧‧‧層間介電質
70‧‧‧接觸蝕刻停止層
72‧‧‧源極/汲極接觸插塞
74‧‧‧虛線
100、102、104、106‧‧‧電晶體
148’‧‧‧介電層
150’‧‧‧介電區
152‧‧‧閘極隔離插塞
200‧‧‧半導體裝置之形成方法
202~216‧‧‧半導體裝置之形成方法的步驟
R1、R2‧‧‧凹陷距離
T1‧‧‧厚度
W1、W2‧‧‧寬度
本發明實施例之各態樣可透過閱讀以下詳細說明及所附圖式得到最佳的理解。應注意的是，依照工業上的標準實施，許多特徵並未按照比例繪製。事實上，各特徵的尺寸可能任意的放大或縮小以便清楚說明。
第1A-1C、2A-2B、3、4A-4B、5A-5C、6A-6D、7A-7C、8、9A-9B、10A-10B圖顯示在一些實施例中，形成鰭式場效電晶體(FinFETs)及閘極隔離插塞的中間階段之剖面圖、上視圖及透視圖。
第11圖顯示在一些實施例中，一裝置晶粒(device die)不同區域中的兩個閘極隔離插塞。
第12圖顯示在一些實施例中，形成FinFET及閘極隔離結構之流程圖。
以下發明實施例公開許多不同的實施方法或是例子來實行發明之不同特徵，以下描述具體的元件及其排列的例子以闡述本發明實施例。當然這些僅是例子且非意圖用於限定。例如，在描述中提及第一個元件形成於第二個元件上時，其可以包括第一個元件與第二個元件直接接觸的實施例，也可以包括有其它元件形成於第一個元件與第二個元件之間的實施例，其中第一個元件與第二個元件並未直接接觸。此外，在不同實施例中可能使用重複的標號或標示，這些重複僅為了簡單清楚地敘述本發明實施例，不代表所討論的不同實施例及/或結構之間有特定的關係。
此外，其中可能用到與空間相關的用詞，像是“在...下方”、“下方”、“下部”、“上方”、“上部”及類似的用詞，這些關係詞係為了便於描述圖示中一(些)元件或特徵與另一(些)元件或特徵之間的關係，這些空間關係詞包括使用中或操作中的裝置之不同方位，以及圖示中所描述的方位。裝置可能被轉向 不同方位(旋轉90度或其他方位)，則其中使用的空間相關形容詞也可相同地照著解釋。
一些示例性實施例提供一閘極隔離結構及其形成方法。一些實施例說明形成閘極隔離結構之中間階段。一些實施例之變化將被描述。在各圖式和說明性實施例中，相似的符號標記用於表示相似的元件。
第1A至10B圖顯示在一些實施例中，形成鰭式場效電晶體及閘極隔離插塞的中間階段之剖面圖、上視圖及透視圖。第1A至10B圖顯示之步驟亦於第12圖所示之流程圖中示意說明。
第1A圖顯示一些實施例中之開始步驟及產生的結構。提供基底20，其為半導體晶圓2的一部分。基底20可為半導體基底，例如為矽基底，亦可使用其它材料，如矽化鍺、碳化矽等。基底20亦可為塊狀半導體基底或絕緣層上矽(silicon-on-insulator)基底。
形成隔離區22以延伸於基底20中。隔離區22可為，例如，淺溝槽隔離(STI)區。淺溝槽隔離區22的形成可包含蝕刻半導體基底20以形成溝槽(未繪示)，及以介電材料填充溝槽以形成淺溝槽隔離區22。淺溝槽隔離區22可由氧化矽所形成，雖然亦可使用其它介電材料，例如，氮化物。
半導體鰭板24突出於淺溝槽隔離區22的頂表面外，且重疊於下方之半導體帶(strip)，其為淺溝槽隔離區22之間的半導體基底20的一部分。半導體鰭板24的形成可包含形成淺溝槽隔離區22使頂表面與半導體鰭板24之頂表面齊平及凹 蝕淺溝槽隔離區22。淺溝槽隔離區22被移除的部分之間的半導體材料部份因此成為半導體鰭板24。半導體鰭板24及一些或實質上全部的半導體帶可由矽或其它含矽化合物形成，包含但不限於碳化矽、矽化鍺等。
虛設閘極堆疊32形成於淺溝槽隔離區22及半導體鰭板24之上，相應的步驟顯示於第12圖所示流程圖的步驟202。虛設閘極堆疊32包含閘極介電質26以及於閘極介電質26之上的虛設閘極電極28。在這些實施例中，可於後續步驟中移除虛設閘極電極28下方之部分閘極介電質26，於此閘極介電質26為虛設閘極介電質。在一些實施例中，在虛設閘極電極28下方之部分閘極介電質26亦可留在最終裝置中，於此閘極介電質26作為產生的FinFET之閘極介電質。在本發明的一些實施例中，閘極介電質26包含氧化矽。在一些可選的實施例中，亦可使用其它材料，如氮化矽、碳化矽等以形成閘極介電質26。閘極介電質26可藉由氧化半導體鰭板24而形成，因此閘極介電質26順應地(conformally)形成於半導體鰭板24上，如第1A圖所示。在一些可選的實施例中，閘極介電質26透過沉積形成，因此除了圖示的部份外，更將包含位於淺溝槽隔離區22頂表面上之水平部分。閘極介電質26的各個水平部分利用虛線繪示。
虛設閘極電極28可包含多晶矽。在一些實施例中，虛設閘極堆疊32進一步包含硬遮罩30於虛設閘極電極28之上。硬遮罩30可由，例如，氮化矽所形成，雖然亦可使用其它材料，如碳化矽、氮氧化矽等。在一些可選的實施例中，未形成硬遮罩30。因此，以虛線繪示第1A圖中的硬遮罩30以表明其 可形成或可不形成。在接續的圖示中，並未繪示硬遮罩30，而其可存在或可不存在。
如第1A圖所示，虛設閘極堆疊32跨過(cross over)複數個半導體鰭板24。第1B圖顯示虛設閘極堆疊32之上視圖。在一些實施例中，第1A圖所示之剖面圖取自於第1B圖中包含線1A-1A之平面。應理解的是，雖然第1A及1B圖為了圖示簡明僅繪示虛設閘極堆疊32跨過兩個半導體鰭板24，但虛設閘極堆疊32可跨過三、四或更多數量之半導體鰭板上(並延伸於其側壁上)。
請參照第1B圖，閘極間隔物34形成於虛設閘極堆疊32的側壁上。閘極間隔物34可形成圍繞虛設閘極堆疊32之環。閘極間隔物34可由氧化物、氮化物、氮氧化物、碳化物等形成。在一些示例性實施例中，閘極間隔物34包含氧化矽層及位於氧化矽層之上的氮化矽層，其中氧化矽層在剖面圖中可具有L型，且氮化矽層位於氧化矽層的平行段(horizontal leg)上。
進一步參照第1B圖，層間介電質(ILD)36圍繞。第1C圖繪示第1B圖所示結構之剖面圖，其中剖面圖取自第1B圖中包含線1C-1C之平面。層間介電質36的頂表面與虛設閘極堆疊32的頂表面及閘極間隔物34的頂表面共平面。層間介電質36可毯覆(blanket)形成至高於虛設閘極堆疊32之頂表面的高度，接著以平坦化製程(例如，化學機械研磨(CMP))移除層間介電質36多餘的部分，其中多餘的部分高於虛設閘極堆疊32及閘極間隔物34的頂表面。層間介電質36可包含流動氧化物(flowable oxide)，其利用，例如流動化學氣相沉積(flowable chemical vapor deposition(FCVD))形成。層間介電質36亦可為利用旋轉塗佈(spin-on coating)所形成之旋塗式玻璃。層間介電質36亦可由磷矽酸鹽玻璃(Phospho-Silicate Glass(PSG))、硼矽酸鹽玻璃(Boro-Silicate Glass(BSG))、硼摻雜磷矽酸鹽玻璃(BPSG)、四乙氧基矽烷(TEOS)氧化物、TiN、SiOC或其它低介電常數無孔介電材料形成。
在一些實施例中，如第1C圖所示，源極及汲極區(下文稱為源極/汲極區)38形成於未被虛設閘極堆疊32覆蓋之半導體鰭板24的相對端部(opposite end portion)中。源極/汲極區38可藉由佈植半導體鰭板24的末端部分，或藉由凹蝕(recess)半導體鰭板24的末端部分形成凹槽且接著於凹槽中再生長(re-grow)源極/汲極區加以形成。源極/汲極矽化物區40可形成於源極/汲極區38的表面上。源極/汲極接觸插塞42可延伸形成於層間介電質36之中以電性連接源極/汲極區38。源極/汲極接觸插塞42可由鎢或其它導電材料/金屬形成。在一些可選的實施例中，源極/汲極矽化物區40及接觸插塞42於後續階段形成，而並未在此階段形成，例如，於第10B圖所示層間介電質68的形成之後。相似地，源極/汲極接觸插塞42可於開始步驟或於後續階段形成，因此源極/汲極接觸插塞42以虛線表示。
請參照第2A圖，光阻44形成並圖案化。第2B圖繪示第2A圖所示結構之上視圖。如第2B圖所示，光阻44覆蓋虛設閘極堆疊32的末端部分，而未覆蓋虛設閘極堆疊32的中間部分。接著透過光阻44中的開口蝕刻虛設閘極堆疊32。相應的步驟顯示於第12圖所示流程圖的步驟204。於此，如第2A及2B圖 所示，移除虛設閘極堆疊32的中間部分。在一些示例性實施例中，長條狀虛設閘極堆疊32因此被切割成與彼此斷開的兩個分離(discrete)部分。剩餘的部分稱為虛設閘極堆疊32A及32B。在第1B圖之虛設閘極堆疊32跨過三、四或更多個半導體鰭板24的一些實施例中，虛設閘極堆疊32可被切割成三、四或更多個分離部分。此外，虛設閘極堆疊32的每一分離部分可跨過一、二或更多個半導體鰭板24，以形成單一鰭板FinFET或多鰭板FinFET。在虛設閘極堆疊32的蝕刻後，移除光阻44，例如，於灰化(ashing)製程中。
由於虛設閘極堆疊32的蝕刻，開口46形成於虛設閘極堆疊32A及32B之間。此外，開口46形成於閘極間隔物部分34A及34B之間，閘極間隔物部分34A及34B為閘極間隔物34的平行相對(opposite)部分。各個閘極間隔物部分34A及34B具有暴露於開口46之側壁。如第2A圖所示，當虛設閘極介電質26具有以虛線表示之平行部分時，暴露的水平部分可暴露於開口46。此外，閘極介電質26的暴露水平部分可在虛設閘極堆疊32的蝕刻中移除，或可在虛設閘極堆疊32的蝕刻中留下(且薄化)。
之後，以介電層/區48及50填充開口46，如第3圖所示。相應的步驟顯示於第12圖所示流程圖的步驟206。介電層48及50由不同的介電材料形成，其擇自於相同群組的介電材料，包含氧化物基(oxide-based)介電材料、氮化物基(nitride-based)介電材料、氮氧化物基(oxynitride-based)介電材料、碳氧化物基(oxycaride-based)介電材料、碳化物基(caride-based)介電材料等，但不限於此。在一些示例性實施例中，介電層48 由氧化物形成，如氧化矽，介電層50由氮化物形成，如氮化矽。此外，形成介電層48的材料不同於形成閘極間隔物34的材料。在閘極間隔物34具有多層結構的一些實施例中，形成閘極介電層48的材料不同於側壁與介電層48實體(physical)接觸之閘極間隔物34的部分的材料。
在一些實施例中，藉由順應性(conformal)沉積方法形成介電層48，因此其垂直部分之厚度接近於水平部分之厚度。在一些示例性實施例中，利用原子層沉積(ALD)、低壓化學氣相沉積(LPCVD)或其它可使用的沉積方法形成介電層48。在一些實施例中，介電層48的厚度T1可在約1nm至約5nm之間的範圍。介電層/區50填充未被介電層48填充的開口46的剩餘空間(第2A圖)。介電層48的形成可包含原子層沉積、化學氣相沉積(CVD)或其它沉積方法，只要可完全地剩餘的開口46。介電層48及50具有高於虛設閘極堆疊32A及32B之頂表面的部分。
請參照第4A及4B圖，於晶圓2上實行平坦化製程以移除介電層48及50的多餘部分，如第3圖所示。相應的步驟顯示於第12圖所示流程圖的步驟208。移除高於虛設閘極堆疊32A及32B的頂表面之部分介電層48及50。於此，虛設閘極堆疊32A及32B被暴露。同時，在一些實施例中，層間介電質36(未繪示於第4A圖中，請參照第1C圖)亦被暴露。介電層48及50的剩餘部分於下文組合稱作為閘極隔離插塞52，其包含剩餘的介電層48’及剩餘的內部介電區50’，內部介電區50’位於介電層48’的底部部分之上。
第4B圖繪示第4A圖所示結構之上視圖。如第4B圖所示，閘極隔離插塞52將虛設閘極堆疊32A及32B彼此分開。閘極隔離插塞52及虛設閘極堆疊32A及32B於上視圖中組合形成帶狀物(strip)，且上述帶狀物位於閘極間隔物34的相對部分34A及34B之間。
接著蝕刻虛設閘極堆疊32A及32B。虛設閘極電極28及硬遮罩30(第4A圖)，若有的話，於蝕刻中移除。相應的步驟顯示於第12圖所示流程圖的步驟210。在本發明的一些實施例中，閘極介電質26未被移除，因此在虛設閘極電極28的移除之後被暴露。產生的結構如第5A及5B圖所示，其分別繪示剖面圖及上視圖。在一些可選的實施例中，閘極介電質26被移除，因此半導體鰭板24被暴露。開口54A及54B形成於被移除的虛設閘極電極28(以及可能地閘極介電質26)留下的空間中。如第5B圖所示，閘極隔離插塞52及閘極間隔物34定義各個開口54A及54B，且開口54A及54B更進一步藉由閘極隔離插塞52與彼此分開。閘極隔離插塞52的寬度表示為W1。
第5C圖顯示在一些實施例中，第5A及5B圖所示結構之透視圖。閘極間隔物34被繪示成透明的以顯示隱藏於閘極間隔物34後方的結構。實際上，閘極間隔物34可為透明或部透明的，其取決於閘極間隔物34的材料及厚度。閘極間隔物34、源極/汲極區及層間介電質36的末端部分未顯示於第5C圖中。如第5C圖所示，閘極隔離插塞52包含由介電層48’所形成的槽(basin)以及位於槽中的介電區50’。
之後，於一蝕刻步驟中移除暴露於開口54A及54B 的介電層48’之側壁部分。相應的步驟顯示於第12圖所示流程圖的步驟212。產生的結構如第6A及6B圖所示，分別繪示其剖面圖及透視圖。利用侵蝕介電層48’且實質上(substantially)未侵蝕介電區50’及閘極間隔物34的蝕刻氣體或蝕刻溶液實行蝕刻。如此一來，暴露於開口54A及54B的介電層48’的側壁部分被移除，而與閘極間隔物部分34A及34B接觸的介電層48’的側壁部分在蝕刻後仍存在。在一些實施例中，上述蝕刻可為等向性的，其可為乾蝕刻或濕蝕刻。產生的閘極介電層48’為包含一底部部分及兩個側壁部分之U型層，且側壁部分的底端與底部部分連接。介電區50’位於介電層48’的底部部分上。
第6C圖繪示第6A及6B圖所示結構之上視圖。用於對照，第6C圖亦以虛線繪示被移除的介電層48’的側壁部分。其顯示透過蝕刻，閘極隔離插塞52的寬度由W1減少至W2，其中W2可等於或稍微小於(W1-2T1)。據此，如第6A、6B及6C圖所示之蝕刻步驟亦稱作為閘極隔離插塞52的薄化(thinning)。因此，藉由形成槽狀(basin-shaped)介電層48’及接著蝕刻介電層48’的兩個側壁部分，閘極隔離插塞52的寬度減少。可理解的是，當閘極隔離插塞52的尺寸非常小時，例如，達到微影製程的極限時，進一步縮小閘極隔離插塞52的尺寸是困難的。有利地，本發明的實施例提供具有縮小尺寸之閘極隔離插塞。寬度W2可小於微影製程可達到的最小尺寸。
在介電層48’的側壁部分的蝕刻中，可橫向地(laterally)凹蝕介電層48’的側壁部分，因而形成如第6D圖所示之彎曲的(curved)側壁。此外，介電區50’的側壁亦可為彎曲 的，且面向開口54A及54B之介電區50’的側壁的中間部分突出剩餘的部分之外。
此外，在虛設閘極堆疊32A及32B(第4A圖)的蝕刻期間，可完全地移除閘極介電質26並暴露半導體鰭板24。產生的結構如第6D圖所示。據此，虛設閘極介電質26的移除可與閘極隔離插塞52的薄化整合為相同的蝕刻步驟。於第6D圖中，僅繪示閘極間隔物部分34A，而未繪示閘極間隔物部分34B(第6B圖)，雖其仍然存在。在一些可選的實施例中，在閘極隔離插塞52的薄化中，閘極介電質26被薄化，其頂部部分被移除且底部部分仍殘留於半導體鰭板24上，如第6B圖所示。
第7A、7B及7C圖分別繪示取代閘極堆疊58A及58B的形成之剖面圖、透視圖及上視圖。相應的步驟顯示於第12圖所示流程圖的步驟214。取代閘極堆疊58A及58B包含閘極電極60。在本發明的一些實施例中，閘極電極60由金屬、金屬合金、金屬矽化物、金屬氮化物等形成，且可具有複合結構，複合結構包含由TiN、TiAl、Co、Al及/或類似物形成的複數層。各個金屬及結構經過選擇，使得產生的取代閘極電極60具有適當的功函數。例如，當產生的FinFET為n型FinFET時，閘極電極60的功函數低於4.5eV，當產生的FinFET為p型FinFET時，閘極電極60的功函數高於4.5eV。
在一些實施例中，取代閘極堆疊58A及58B進一步包含閘極介電質62(第7A及7C圖)，其可與半導體鰭板24實體接觸，或可與剩餘的閘極介電質26接觸。在閘極介電質26仍存在之一些可選的實施例中，未形成額外的閘極介電質，且閘極電 極60可與閘極介電質26及閘極隔離插塞52實體接觸。閘極介電質62可包含高介電常數(high-k)材料，例如，氧化鉿(hafnium oxide)、氧化鋯(zirconium oxide)、氧化鑭(lanthanum oxide)等，且亦可包含氧化矽層作為高介電常數介電材料半導體鰭板24之間的界面層。
如第7A圖所示，介電層48’的底部部分具有彎曲的側壁，而彎曲的側壁具有頂部部分、底部部分以及比頂部部分及底部部分更為凹陷(recessed)之中間部分。
第7C圖繪示取代閘極堆疊58A及58B的上視圖。閘極隔離插塞52將取代閘極堆疊58A及58B互相分開。取代閘極堆疊58A及58B組合可視為被閘極隔離插塞52分開成部分58A及部分58B之長條狀(elongated)閘極堆疊帶。閘極隔離插塞52及取代閘極堆疊58A及58B組合形成於上視圖中具有一致寬度的帶狀物(strip)，且上述帶狀物位在閘極間隔物34的相對部分34A及34B之間。亦言之，每一連續的(其可為直線的)閘極間隔物部分34A及/或34B與取代閘極堆疊58A、閘極隔離插塞52及取代閘極堆疊58B的側壁接觸。閘極介電質62以虛線表示以表明其可形成或可不形成。
在產生的結構中，形成FinFET 100及102，其分別具有取代閘極58A及58B。取代閘極58A及58B共用共同的閘極間隔物34A及34B。此外，取代閘極58A及58B均鄰接(abut)閘極隔離插塞52。
第8圖繪示一些實施例中，FinFET 100或102(標示為100/102)的一部分的上視圖。應理解的是，介電層48’可具有 由閘極隔離插塞52的薄化所造成之彎曲的側壁49。彎曲的側壁49具有比各末端部分更為凹陷之中間部分，且凹陷距離R1可大於約5Å。凹陷距離R1亦可在約5Å至約5nm之間的範圍。
第9A及9B圖分別繪示一些實施例中，FinFET 100及102的透視圖及上視圖。在這些實施例中，介電區50’亦具有由閘極隔離插塞52的薄化所造成之彎曲的側壁51。彎曲的側壁51具有往取代閘極58A/58B突出較多之中間部分，且突出距離R2(第9B圖)可大於約5Å。突出距離R2亦可在約5Å至約5nm之間的範圍。
第10A圖繪示層間介電質68及層間介電質68中的閘極接觸插塞66A及66B的形成之剖面圖。相應的步驟顯示於第12圖所示流程圖的步驟216。形成層間介電質68的材料可擇自相同於形成層間介電質36(第1C圖)之候選材料。接觸插塞66A及66B分別位於閘極堆疊58A及58B之上且分別與閘極堆疊58A及58B接觸。應理解的是，雖然閘極介電質26繪示於圖示中，但在一些實施例中，它們可能存在或不存在。
第10B圖繪示電晶體100之剖面圖，其中剖面圖取自於第10A圖中包含線10B-10B之平面。源極/汲極接觸插塞72延伸形成至層間介電質36及68之中。此外，亦繪示接觸蝕刻停止層70。應理解的是，源極/汲極接觸插塞72的下部部分(lower portion)可於此階段形成，或可於第1C圖所示之步驟中形成，其中下部部分標示為42。
第11圖繪示具有閘極隔離插塞52之電晶體100及102，以及具有閘極隔離插塞152之電晶體104及106。在一些實 施例中，電晶體100及102屬於形成於第一裝置區中的第一裝置型，而電晶體104及106屬於形成於不同於第一裝置區之第二裝置區中的第二裝置型，其中第一裝置型與第二裝置型不同。在一些示例性實施例中，電晶體100及102為核心裝置(位於核心區中)、記憶裝置(位於記憶區中)等，而電晶體104及106為輸入/輸出(IO)裝置(位於IO區中)。閘極隔離插塞52包含具有U型形狀的介電層48’，而閘極隔離插塞152包含具有槽型形狀的介電層148’及介電區150’。在一些實施例中，電晶體100及102需須盡可能的小，故閘極隔離插塞52亦須盡可能的小。因此，薄化閘極隔離插塞52以具有U型形狀。另一方面，閘極隔離插塞152須具有足夠大的寬度以維持施用於電晶體104及106的閘極之高電壓。因此，未薄化閘極隔離插塞152。在一些實施例中，閘極隔離插塞52及152的相應部分共用一些製程步驟。例如，層48’及148’可共用相同的沉積製程，而區域50’及150’可共用相同的沉積製程及相同的CMP製程。因此，可同時地形成閘極隔離插塞52及152，但是閘極隔離插塞52經薄化，而閘極隔離插塞152並未實行薄化。
應理解的是，雖然以FinFET 100、102、104及106作為例子，但本發明實施例的概念亦可使用於平面電晶體。平面電晶體的結構及形成方法以及相應的閘極隔離插塞與第1A至11圖所示者相似，除了使用的是平面主動區而非半導體鰭板24。
本發明的一些實施例具有有利的特徵。請參照第10A圖，若閘極隔離插塞52並未薄化，則閘極隔離插塞52的邊 緣可能位於以虛線74所示之位置，而閘極接觸插塞66B將部分著陸(land)於取代閘極58A上。藉由使閘極隔離插塞52變薄，閘極堆疊58A變得較長，部分著陸至少將可減少、或實質上消失。
在本發明的一些實施例中，一裝置包含：閘極隔離插塞，其進一步包含具有一底部部分及兩個側壁部分之U型層，以及與底部部分重疊之內部區，上述內部區與兩個側壁接觸；一第一電晶體具有第一閘極堆疊，且第一閘極堆疊的第一末端與閘極隔離插塞的內部區及U型層接觸；一第二電晶體具有第二閘極堆疊，且第二閘極堆疊的第二末端與閘極隔離插塞的內部區及U型層接觸，上述第一閘極堆疊及第二閘極堆疊位於閘極隔離插塞的相對側。
在本發明的一些實施例中，一裝置包含：長條狀(elongated)閘極堆疊以及將長條狀閘極堆疊分開為第一閘極堆疊及第二閘極堆疊之閘極隔離插塞，上述閘極隔離插塞包含具有一底部部分及兩個側壁部分之外部層，以及與底部部分重疊且接觸之內部區，外部層的兩個側壁部分的頂表面以及內部區的頂表面實質上(substantially)與彼此共平面，上述第一閘極堆疊及第二閘極堆疊與內部區之相對的側壁接觸；一第一FinFET具有第一半導體鰭板，其中第一閘極堆疊跨過(cross over)第一半導體鰭板；一第二FinFET具有第二半導體鰭板，其中第二閘極堆疊跨過第二半導體鰭板。
在本發明的一些實施例中，一方法包含：形成長條狀虛設閘極堆疊，以及蝕刻長條狀虛設閘極堆疊以形成第一開口，上述第一開口將長條狀虛設閘極堆疊分開成第一虛設閘 極堆疊及第二虛設閘極堆疊；以及沉積介電層且延伸於第一開口之中，介電區填充第一開口的剩餘空間。上述方法更包含：於介電層、介電區、第一虛設閘極堆疊及第二虛設閘極堆疊上實行平坦化製程；移除第一虛設閘極堆疊及第二虛設閘極堆疊以分別形成第二開口及第三開口；蝕刻面向(face)第二開口及第三開口的介電層的部分，直到介電區的側壁暴露於第二開口及第三開口；以及分別以第一取代閘極及第二取代閘極填充第二開口及第三開口。
前述內文概述了許多實施例的特徵，使所屬技術領域中具有通常知識者可以更佳的了解本發明實施例的各個方面。所屬技術領域中具有通常知識者應該可理解，他們可以很容易的以本發明實施例為基礎來設計或修飾其它製程及結構，並以此達到相同的目的及/或達到與本發明介紹的實施例相同的優點。所屬技術領域中具有通常知識者也應該了解這些相等的結構並不會背離本發明的發明精神與範圍。本發明實施例可以作各種改變、置換、修改而不會背離本發明的發明精神與範圍。
20‧‧‧基底
22‧‧‧隔離區
48’‧‧‧介電層
50’‧‧‧介電區
52‧‧‧閘極隔離插塞
58A、58B‧‧‧取代閘極堆疊
60‧‧‧閘極電極
62‧‧‧閘極介電質
100、102‧‧‧電晶體

Claims (14)

  1. 一種半導體裝置，包括：一閘極隔離插塞，包括：一U型層，包括一底部部分及兩個側壁部分；一內部區，與該底部部分重疊，其中該內部區與上述兩個側壁部分接觸；一第一電晶體，包括一第一閘極堆疊，其中該第一閘極堆疊的一第一末端與該閘極隔離插塞的內部區及U型層接觸；以及一第二電晶體，包括一第二閘極堆疊，該第一閘極堆疊及該第二閘極堆疊位於該閘極隔離插塞的相對側，其中該第二閘極堆疊的一第二末端與該閘極隔離插塞的內部區及U型層接觸。
  2. 如申請專利範圍第1項所述之半導體裝置，其中該第一閘極堆疊具有一第一長度及一小於該第一長度之第一寬度，且該第二閘極具有一第二長度及一小於該第二長度之第二寬度，且該第一寬度等於該第二寬度，其中該第一閘極堆疊及該第二閘極堆疊的長度方向與同一直線對齊。
  3. 如申請專利範圍第1項所述之半導體裝置，更包括：一第一閘極間隔物部分，與該第一閘極堆疊、該U型層及該第二閘極堆疊接觸；以及一第二閘極間隔物部分，與該第一閘極堆疊、該U型層及該第二閘極堆疊接觸，其中該第一閘極間隔物部分及該第二閘極間隔物部分均為直線狀且與彼此平行。
  4. 如申請專利範圍第1項所述之半導體裝置，其中該U型層的底部部分於該閘極隔離插塞的剖面圖中具有一彎曲側壁，且該彎曲側壁具有一頂部部分、一底部部分及一中間部分，該中間部分較該頂部部分及該底部部分凹陷。
  5. 如申請專利範圍第1項所述之半導體裝置，更包括：一淺溝槽隔離(STI)區，直接地(directly)位在該閘極隔離插塞下方並與其接觸。
  6. 如申請專利範圍第1至5項任一項所述之半導體裝置，其中該閘極隔離插塞的U型層及內部區係由不同的介電材料形成。
  7. 如申請專利範圍第1至5項任一項所述之半導體裝置，其中該內部區及該U型層的至少一者於該閘極隔離插塞的上視圖中具有一彎曲邊緣。
  8. 一種半導體裝置，包括：一長條狀閘極堆疊；以及一閘極隔離插塞，將該長條狀閘極堆疊分為一第一閘極堆疊及一第二閘極堆疊，其中該閘極隔離插塞包括：一外部層，包括一底部部分及兩個側壁部分；一內部區，與該底部部分重疊並接觸，其中該外部層的兩個側壁部分的頂表面及該內部區的頂表面實質上與彼此共平面，且該第一閘極堆疊及該第二閘極堆疊與該內部區之相對的側壁接觸；以及一第一鰭式場效電晶體(FinFET)，包括：一第一半導體鰭板，其中該第一閘極堆疊跨過(cross over)該第一半導體鰭板；以及 一第二鰭式場效電晶體，包括：一第二半導體鰭板，其中該第二閘極堆疊跨過該第二半導體鰭板。
  9. 如申請專利範圍第8項所述之半導體裝置，其中該閘極隔離插塞的底部部分及兩個側壁部分具有實質上相同之厚度。
  10. 如申請專利範圍第8或9項所述之半導體裝置，其中該第一閘極堆疊及該第二閘極堆疊均與該閘極隔離插塞的外部層的底部部分之相對的側壁接觸，或其中該第一閘極堆疊及該第二閘極堆疊均與該閘極隔離插塞的兩個側壁部分之相對的側壁接觸。
  11. 如申請專利範圍第8或9項所述之半導體裝置，其中該外部層的兩個側壁部分的頂表面及該內部區的頂表面實質上與該第一閘極堆疊及該第二閘極堆疊的頂表面共平面。
  12. 一種半導體裝置的形成方法，包括：形成一長條狀虛設閘極堆疊；蝕刻該長條狀虛設閘極堆疊以形成一第一開口，其中該第一開口將該長條狀虛設閘極堆疊分為一第一虛設閘極堆疊及一第二虛設閘極堆疊；沉積一介電層，其中該介電層延伸於該第一開口中；形成一介電區，填充該第一開口之剩餘空間；於該介電層、該介電區、該第一虛設閘極堆疊及該第二虛設閘極堆疊上實行一平坦化製程；移除該第一虛設閘極堆疊及該第二虛設閘極堆疊以分別形成一第二開口及一第三開口； 蝕刻面向該第二開口及該第三開口的介電層的部分直到該介電區的側壁暴露於該第二開口及該第三開口中；以及分別以一第一取代閘極及一第二取代閘極填充該第二開口及該第三開口。
  13. 如申請專利範圍第12項所述之半導體裝置的形成方法，其中蝕刻該部分的介電層的步驟包括一等向性蝕刻。
  14. 如申請專利範圍第12或13項所述之半導體裝置的形成方法，更包括：形成一閘極間隔物，該閘極間隔物包括與該長條狀虛設閘極堆疊的相對的側壁接觸之相對的部分，其中在蝕刻該部分的介電層後，接觸該閘極間隔物的介電層的部分仍存在。
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