TWI683395B - 鰭狀電晶體與鰭狀電晶體的製作方法 - Google Patents

鰭狀電晶體與鰭狀電晶體的製作方法 Download PDF

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TWI683395B
TWI683395B TW104137271A TW104137271A TWI683395B TW I683395 B TWI683395 B TW I683395B TW 104137271 A TW104137271 A TW 104137271A TW 104137271 A TW104137271 A TW 104137271A TW I683395 B TWI683395 B TW I683395B
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epitaxial layer
groove
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TW201717314A (zh
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劉恩銓
童宇誠
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聯華電子股份有限公司
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Priority to US14/981,869 priority patent/US9882054B2/en
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Abstract

本發明提供一種鰭狀電晶體，包含一基底，其上定義有複數條鰭狀結構，一閘極結構橫跨各個鰭狀結構，兩第一凹槽分別位於該閘極結構的兩側，其中各該第一凹槽中更包含有複數個第二凹槽，且各該第二凹槽的位置對應各該鰭狀結構，以及兩磊晶層分別設置於該閘極結構的兩側的該第一凹槽與各該第二凹槽中，其中各該磊晶層具有一第二凹凸輪廓的底面，且各該磊晶層直接接觸該第一凹槽的一底面與各該第二凹槽的一底面。

Description

鰭狀電晶體與鰭狀電晶體的製作方法
本發明係關於一種鰭狀電晶體，特別是有關於鰭狀電晶體包含有一磊晶層具有凹凸輪廓及其製作方法。
近年來，隨著各種消費性電子產品不斷的朝小型化發展，半導體元件設計的尺寸亦不斷縮小，以符合高積集度、高效能和低耗電之潮流以及產品需求。
然而，隨著電子產品的小型化發展，現有的平面電晶體(planar transistor)已經無法滿足產品的需求。因此，目前發展出一種非平面電晶體，例如是鰭狀電晶體(Fin-FET)技術，其具有立體的閘極通道結構，可有效減少基底之漏電，並能降低短通道效應，而具有較高的驅動電流。
然而，隨著電晶體的縮小，作為源極/汲極的磊晶層其體積也跟著隨之縮小，同樣地電連接磊晶層的接觸插塞之體積也變小，也就是說接觸插塞和磊晶層接觸的面積降低，如此造成了接觸插塞之片電阻增加。
本發明提供一種鰭狀電晶體的製作方法，首先，提供一基底，其上定義有複數條鰭狀結構，一淺溝渠隔離設置於相鄰的該鰭狀結構之間以及一閘 極結構橫跨該等鰭狀結構，接著蝕刻未被該閘極結構覆蓋的該等鰭狀結構和未被該閘極結構覆蓋之該淺溝渠隔離，直至完全移除該淺溝渠隔離並且在該基底上形成一第一凹凸輪廓，其中該第一凹凸輪廓包含有一第一凹槽以及複複數個第二凹槽，該等第二凹槽的位置對應該該等鰭狀結構，以及在該第一凹凸輪廓上形成一磊晶層。
本發明又提供一種鰭狀電晶體，包含一基底，其上定義有複數條鰭狀結構，一閘極結構橫跨各個鰭狀結構，兩第一凹槽分別位於該閘極結構的兩側，其中各該第一凹槽中更包含有複數個第二凹槽，且各該第二凹槽的位置對應各該鰭狀結構，以及兩磊晶層分別設置於該閘極結構的兩側的該第一凹槽與各該第二凹槽中，其中各該磊晶層具有一第二凹凸輪廓的底面，且各該磊晶層直接接觸該第一凹槽的一底面與各該第二凹槽的一底面。
本發明特徵在於提供一種具有特殊形狀磊晶層的鰭狀電晶體，此外，有別於傳統在各個鰭狀結構上各別生成磊晶層，然後在各個磊晶層接上共同的電路，本發明等於是將多個磊晶層結合一個較大的磊晶層，因此使用本發明一個較大的磊晶層相較於使用傳統的多個磊晶層，本發明的磊晶層會有較小的電阻值。
10‧‧‧基底
12‧‧‧鰭狀結構
14‧‧‧淺溝渠隔離
16‧‧‧深溝渠隔離
18‧‧‧閘極結構
20‧‧‧閘極電極
22‧‧‧閘極介電層
24‧‧‧側壁子
26‧‧‧遮罩層
30‧‧‧第一凹槽
30a‧‧‧底部
32‧‧‧第二凹槽
32a‧‧‧底部
32b‧‧‧側壁
34‧‧‧第一凹凸輪廓
38‧‧‧凹面
40‧‧‧磊晶層
40a‧‧‧上表面
42‧‧‧第二凹凸輪廓
44‧‧‧磊晶層
44a‧‧‧底面
50‧‧‧接觸插塞
100‧‧‧鰭狀電晶體
114‧‧‧上表面
116‧‧‧上表面
214‧‧‧底部
216‧‧‧底部
W‧‧‧表面寬度
D1‧‧‧深度
D2‧‧‧深度
第1圖至第9圖為根據本發明之較佳實施例所繪示的一種鰭狀電晶體的製作方法之示意圖，其中第2圖為第1圖沿AA’切線方向的側視圖示意圖，第4圖為第3圖沿BB’切線方向的側視圖示意圖，第6圖為第5圖沿CC’切線方向的側視圖示意 圖，第8圖為第7圖沿DD’切線方向的側視圖示意圖。
第10圖繪示本發明另外一實施例的鰭狀電晶體的剖面圖。
第11圖繪示本發明另外一實施例的鰭狀電晶體的剖面圖。
第12圖繪示本發明另外一實施例的鰭狀電晶體的剖面圖。
為使熟習本發明所屬技術領域之一般技藝者能更進一步了解本發明，下文特列舉本發明之較佳實施例，並配合所附圖式，詳細說明本發明的構成內容及所欲達成之功效。
為了方便說明，本發明之各圖式僅為示意以更容易了解本發明，其詳細的比例可依照設計的需求進行調整。在文中所描述對於圖形中相對元件之上下關係，在本領域之人皆應能理解其係指物件之相對位置而言，因此皆可以翻轉而呈現相同之構件，此皆應同屬本說明書所揭露之範圍，在此容先敘明。
第1圖至第9圖為根據本發明之較佳實施例所繪示的一種鰭狀電晶體的製作方法之示意圖，其中第2圖為第1圖沿AA’切線方向的側視圖示意圖，第4圖為第3圖沿BB’切線方向的側視圖示意圖，第6圖為第5圖沿CC’切線方向的側視圖示意圖，第8圖為第7圖沿DD’切線方向的側視圖示意圖。
如第1圖和第2圖所示，首先提供一基底10其上定義有複數個鰭狀結構12，詳細來說，鰭狀結構12係利用去除部分的基底10後始定義出來，也就是說鰭狀結構12係由部分的基底10構成。鰭狀結構12的個數不限，根據不同的需求可以設計不同數量的鰭狀結構12，此外，各個鰭狀結構12彼此互相平行。在相鄰的鰭狀結構12之間設置有一淺溝渠隔離14，淺溝渠隔離14位在基底10上， 材質例如為氧化矽或氮化矽，此外在複數個鰭狀結構12中最旁邊的鰭狀結構12的一側，設置有一深溝渠隔離16，深溝渠隔離16位在基底10上，深溝渠隔離16的上表面116係和淺溝渠隔離14的上表面114切齊，但深溝渠隔離16的底部216較淺溝渠隔離14的底部214深。另外，一閘極結構18橫跨各個鰭狀結構12、深溝渠隔離16和淺溝渠隔離14，閘極結構18可以包含一閘極電極20、一閘極介電層22並且選擇性地包含一側壁子24，閘極介電層22接觸鰭狀結構12、深溝渠隔離16和淺溝渠隔離14，閘極電極20位在閘極介電層22上，而側壁子24位在閘極電極20兩側。
其中，上述閘極介電層22的材料可以包括氧化矽(SiO)、氮化矽(SiN)、氮氧化矽(SiON)，或包含介電常數大於4的介電材料，例如係選自氧化鉿(hafnium oxide，HfO2)、矽酸鉿氧化合物(hafnium silicon oxide，HfSiO4)、矽酸鉿氮氧化合物(hafnium silicon oxynitride，HfSiON)、氧化鋁(aluminum oxide，Al2O3)、氧化鑭(lanthanum oxide，La2O3)、氧化鉭(tantalum oxide，Ta2O5)、氧化釔(yttrium oxide，Y2O3)、氧化鋯(zirconium oxide，ZrO2)、鈦酸鍶(strontium titanate oxide，SrTiO3)、矽酸鋯氧化合物(zirconium silicon oxide，ZrSiO4)、鋯酸鉿(hafnium zirconium oxide，HfZrO4)、鍶鉍鉭氧化物(strontium bismuth tantalate,SrBi2Ta2O9,SBT)、鋯鈦酸鉛(lead zirconate titanate,PbZrxTi1-xO3,PZT)、鈦酸鋇鍶(barium strontium titanate,BaxSr1-xTiO3,BST)、或其組合所組成之群組。閘極電極20的材料可以包括未摻雜的多晶矽、重摻雜的多晶矽、金屬矽化物、或是單層或多層金屬層，金屬層例如功函數金屬層，阻擋層和低電阻金屬層等。但本發明不限於此，而元件材料可以依照實際需求而調整。
如第3圖和第4圖所示，形成一遮罩層26覆蓋閘極結構18、和至少部分的深溝渠隔離16，並且由遮罩層26的開口，曝露出位在閘極結構18兩側的多個鰭狀結構12、淺溝渠隔離14以及部分的深溝渠隔離16，如第4圖所示，深溝渠隔離16具有一表面寬度W，深溝渠隔離16例如可由遮罩層26的開口被曝露出至少四分之一至二分之一的表面寬度W。
如第5圖和第6圖所示，移除曝露的多個鰭狀結構12、淺溝渠隔離14以及部分的深溝渠隔離16，以在閘極結構18兩側各形成一第一凹槽30，以及複數個互相平行排列的第二凹槽32位於第一凹槽30中。因此，由第一凹槽的底部30a以及第二凹槽32的底部32a與第二凹槽32的側壁32b共同組成一第一凹凸輪廓34，第一凹凸輪廓34類似一齒狀。其中第二凹槽32的底部32a較第一凹槽30的底部30a更低。
詳細來說，前述的移除方式可以利用蝕刻方式，一開始採用對矽和氧化矽有高選擇比的蝕刻條件(也就是蝕刻矽的速率遠高於蝕刻氧化矽的速率)，先蝕刻利用矽基底所製成的多個鰭狀結構12以移除部分的各個鰭狀結構12，由於淺溝渠隔離14為氧化矽所製成，所以此時淺溝渠隔離14幾乎未被蝕刻，然後再調整蝕刻條件調整為矽和氧化矽的蝕刻選擇比，舉例來說，例如為2：1(也就是蝕刻矽的速率：蝕刻氧化矽的速率為2：1)，但不限於此，而可以依照實際需求調整，接續同時蝕刻鰭狀結構12和淺溝渠隔離14，直到淺溝渠隔離14完全被移除為止，也就是說在閘極結構18兩側，未被閘極結構18覆蓋的淺溝渠隔離14被蝕刻到完全移除為止。另外在閘極結構18兩側未被閘極結構18覆蓋的鰭狀結構12，在蝕刻淺溝渠隔離14時也同時被蝕刻，而且由於鰭狀結構12被蝕刻的速率大於淺溝渠隔離14被蝕刻的速率，因此被蝕刻後的鰭狀結構12不僅被完全移 除，而且還進一步蝕刻第一凹槽30的底部，並在第一凹槽30內部形成複數個第二凹槽32，各第二凹槽32位置對應到原先鰭狀結構12的位置。上述第一凹凸輪廓34就由一第一凹槽30與複數個第二凹槽32組成，其中位於兩相鄰的第二凹槽32之間的第一凹槽30的底面30a，定義為第一凹凸輪廓34的凸出部分，而該些第二凹槽32的底部32a則定義為第一凹凸輪廓34的凹入部分。
另外，在蝕刻曝露的淺溝渠隔離14和曝露的多個鰭狀結構12時，深溝渠隔離16也可能被部分移除而曝露，因此在剩餘的深溝渠隔離16上會形成一凹面38，凹面38可能緊鄰一第二凹槽32，較佳而言，和第二凹槽32之側壁32b形成一連續的表面。
值得注意的是，由於各第二凹槽32位置對應到各移除前的鰭狀結構12，所以當各第二凹槽32形成後，各第二凹槽32將會曝露出被閘極結構18所覆蓋住而未被移除的鰭狀結構12側壁。此外，前述的蝕刻較佳為乾蝕刻。根據本發明之較佳實施例，第一凹槽的深度D1較佳為100至400埃。第二凹槽32的深度D2較佳為300至600埃。但不限於此，而可以依照實際需求調整。此外，在第一凹槽30與第二凹槽32形成後，可以選擇性對第一凹槽30與第二凹槽32底下的基底10進行一離子摻雜步驟(圖未示)，較佳地，此處植入的離子可以選擇與後續形成的磊晶層(作為電晶體的源/汲極)擁有不同導電型態。如此可進一步避免磊晶層產生漏電流。
如第7圖和第8圖所示，在第一凹凸輪廓34上形成一磊晶層40，磊晶層40直接接觸基底10。更詳細而言，磊晶層40至少直接接觸第一凹槽30的底面30a與第二凹槽32的底面32a。較佳而言，磊晶層40具有一平坦的上表面40a，磊 晶層40接觸第一凹凸輪廓34和深溝渠隔離16，磊晶層40的底部40b也形成有第二凹凸輪廓42，第二凹凸輪廓42和第一凹凸輪廓34互補，使得第二凹凸輪廓42嵌入第一凹凸輪廓34。
最後，如第9圖所示，在磊晶層40上形成一接觸插塞50，接觸插塞50接觸磊晶層40的上表面40a，並且與磊晶層40電連接。此外在形成接觸插塞之前，可以在磊晶層40的上表面40a形成一金屬矽化物(圖未示)。至此本發明之一鰭狀電晶體100的主要結構已完成。
下文將針對本發明之鰭狀電晶體的不同實施樣態進行說明，且為簡化說明，以下說明主要針對各實施例不同之處進行詳述，而不再對相同之處作重覆贅述。此外，本發明之各實施例中相同之元件係以相同之標號進行標示，以利於各實施例間互相對照。
請參考第10圖，其繪示本發明另外一實施例的鰭狀電晶體的剖面圖，其中與上述第一較佳實施例不同之處在於，在第一凹槽30與各第二凹槽32完成後，先額外填入一磊晶層44，其中磊晶層44順形地(conformally)填滿各第二凹槽32，且磊晶層44填入第二凹槽32的部分具有一底面44a，其中底面44a較佳高於第一凹槽的底面30a。接著才在磊晶層44上方形成上述的磊晶層40。其中磊晶層44與磊晶層40可選擇相同或不同的材質，舉例來說，磊晶層44可能為含鍺量較低的矽鍺(SiGe)層，其中含鍺量大約10%-25%，而磊晶層40可能為含鍺量較高的矽鍺(SiGe)層，其中含鍺量大約35%-55%等，但不限於此。在本發明的其他實施例中，請參考第11圖，磊晶層44並未填滿各第二凹槽32，而僅部分填入第二凹槽32中，因此磊晶層44的頂面低於第一凹槽30的底面30a，因為磊晶層40覆蓋 於磊晶層44上，因此磊晶層40覆蓋於第一凹槽30的底面30a。或是如第12圖所示，磊晶層44共形地(conformally)覆蓋在第一凹槽30與第二凹槽32中，其中磊晶層44的底面44a較佳低於第一凹槽的底面30a，上述結構也屬於本發明的涵蓋範圍內。
綜上所述，本發明特徵在於提供一種具有特殊形狀磊晶層的鰭狀電晶體，此外，有別於傳統在各個鰭狀結構上各別生成磊晶層，然後在各個磊晶層接上共同的電路，本發明等於是將多個磊晶層結合一個較大的磊晶層，因此使用本發明一個較大的磊晶層相較於使用傳統的多個磊晶層，本發明的磊晶層會有較小的電阻值。以上所述僅為本發明之較佳實施例，凡依本發明申請專利範圍所做之均等變化與修飾，皆應屬本發明之涵蓋範圍。
10‧‧‧基底
16‧‧‧深溝渠隔離
30a‧‧‧底部
32‧‧‧第二凹槽
32a‧‧‧底部
32b‧‧‧側壁
34‧‧‧第一凹凸輪廓
38‧‧‧凹面
40‧‧‧磊晶層
40a‧‧‧上表面
42‧‧‧第二凹凸輪廓
50‧‧‧接觸插塞
100‧‧‧鰭狀電晶體
116‧‧‧上表面
216‧‧‧底部

Claims (17)

  1. 一種鰭狀電晶體的製作方法，包含：提供一基底其上定義有複數條鰭狀結構，一淺溝渠隔離設置於相鄰的該鰭狀結構之間以及一閘極結構橫跨該等鰭狀結構；蝕刻未被該閘極結構覆蓋的該等鰭狀結構和未被該閘極結構覆蓋之該淺溝渠隔離，直至完全移除該淺溝渠隔離並且在該基底上形成一第一凹凸輪廓，其中該第一凹凸輪廓包含有一第一凹槽以及複複數個第二凹槽，且該等第二凹槽的位置對應該等鰭狀結構，其中該第一凹槽的一底面定義為該第一凹凸輪廓的凸出部分，該等第二凹槽定義為該第一凹凸輪廓的凹入部分；以及在該第一凹凸輪廓上形成一磊晶層。
  2. 如申請專利範圍第1項所述之鰭狀電晶體的製作方法，另包含一深溝渠隔離設置於該基底中，該深溝渠隔離位在該等鰭狀結構中最旁邊的鰭狀結構之一側，並且該深溝渠隔離的底部的深度大於該淺溝渠隔離的底部的深度。
  3. 如申請專利範圍第2項所述之鰭狀電晶體的製作方法，另包含在蝕刻該等鰭狀結構和該淺溝渠隔離之前，形成一遮罩層覆蓋該閘極結構和部分之該深溝渠隔離，使得位在該閘極結構兩側的該等鰭狀結構、該淺溝渠隔離和至少部分之該深溝渠隔離曝露出來。
  4. 如申請專利範圍第3項所述之鰭狀電晶體的製作方法，另包含在蝕刻該等鰭狀結構和該淺溝渠隔離時，同時蝕刻曝露出該深溝渠隔離。
  5. 如申請專利範圍第1項所述之鰭狀電晶體的製作方法，其中該磊晶層 具有一平坦上表面。
  6. 如申請專利範圍第5項所述之鰭狀電晶體的製作方法，另包含在形成該磊晶層之後，形成一接觸插塞接觸該磊晶層的該平坦上表面。
  7. 一種鰭狀電晶體，包含：一基底，其上定義有複數條鰭狀結構；一閘極結構橫跨該等鰭狀結構；兩第一凹槽，分別位於該閘極結構的兩側，其中各該第一凹槽中更包含有複數個第二凹槽，且各該第二凹槽的位置對應各該鰭狀結構；以及兩磊晶層分別設置於該閘極結構的兩側的該第一凹槽與各該第二凹槽中，其中各該磊晶層具有一第二凹凸輪廓的底面，且各該磊晶層直接接觸該第一凹槽的一底面與各該第二凹槽的一底面，其中該閘極結構兩側的該第二凹槽之一底面較該第一凹槽之一底面更低，其中相鄰的各該第二凹槽之間的該第一凹槽之該底面定義成一凸出部。
  8. 如申請專利範圍第7項所述之鰭狀電晶體，另包含二深溝渠隔離設於該基底中，其中該等深溝渠隔離分別位在該磊晶層的二端之該基底中，並且該磊晶層接觸該等深溝渠隔離。
  9. 如申請專利範圍第7項所述之鰭狀電晶體，其中該基底具有一第一凹凸輪廓，該等第二凹槽形成該第一凹凸輪廓的凹入部分，該凸出部形成該第一凹凸輪廓的凸出部分。
  10. 如申請專利範圍第9項所述之鰭狀電晶體，其中各該磊晶層之底部包含該第二凹凸輪廓，該第二凹凸輪廓和該第一凹凸輪廓互補，使得該第二凹凸輪廓嵌入該第一凹凸輪廓。
  11. 如申請專利範圍第7項所述之鰭狀電晶體，其中各第二凹槽互相平行排列。
  12. 如申請專利範圍第7項所述之鰭狀電晶體，其中各該磊晶層具有一平坦上表面。
  13. 如申請專利範圍第7項所述之鰭狀電晶體，其中該磊晶層包含有一第一磊晶層與一第二磊晶層，該第一磊晶層位於該兩第二磊晶層下方，且該第一磊晶層至少位於各該第二凹槽中。
  14. 如申請專利範圍第13項所述之鰭狀電晶體，其中該第一磊晶層的一頂面低於該第一凹槽的一底面。
  15. 如申請專利範圍第14項所述之鰭狀電晶體，其中該第二磊晶層直接覆蓋於該第一凹槽的該底面上。
  16. 如申請專利範圍第13項所述之鰭狀電晶體，其中該第一磊晶層填滿各該第二凹槽，並且覆蓋於該第一凹槽的一底面上，且該第一磊晶層的一頂面高於該第一凹槽的一底面。
  17. 如申請專利範圍第13項所述之鰭狀電晶體，其中該第一磊晶層與該第二磊晶層的組成成分不相同。
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